From 2df77b9ca0d0db860ae455c2688915223f50d049 Mon Sep 17 00:00:00 2001 From: NouranAbdelaziz Date: Mon, 13 Jan 2025 18:19:07 +0200 Subject: [PATCH] update docs --- README.md | 20 +------ docs/EF_QSPI_XIP_CTRL.svg | 1 - docs/_static/EF_QSPI_XIP_CTRL.svg | 1 + hdl/rtl/test.v | 98 +++++++++++++++++++++++++++++++ 4 files changed, 100 insertions(+), 20 deletions(-) delete mode 100644 docs/EF_QSPI_XIP_CTRL.svg create mode 100644 docs/_static/EF_QSPI_XIP_CTRL.svg create mode 100644 hdl/rtl/test.v diff --git a/README.md b/README.md index 5e0a2ef..39bd8b3 100644 --- a/README.md +++ b/README.md @@ -35,22 +35,6 @@ The following table is the result for implementing the EF_QSPI_XIP_CTRL IP with |---|---|---| |EF_QSPI_XIP_CTRL|1973| 250 | |EF_QSPI_XIP_CTRL_AHBL|1973|250| -## The Programmer's Interface - - -### Registers - -|Name|Offset|Reset Value|Access Mode|Description| -|---|---|---|---|---| - -### Clock Gating -The IP includes a clock gating feature that allows selective activation and deactivation of the clock using the ``GCLK`` register. This capability is implemented through the ``ef_util_gating_cell`` module, which is part of the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the clock gating is disabled. To enable behavioral implmentation clock gating, only for simulation purposes, you should define the ``CLKG_GENERIC`` macro. Alternatively, define the ``CLKG_SKY130_HD`` macro if you wish to use the SKY130 HD library clock gating cell, ``sky130_fd_sc_hd__dlclkp_4``. - -**Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to enable the clock gating feature, you need to add ``CLKG_SKY130_HD`` macro to the ``VERILOG_DEFINES`` configuration variable. Update OpenLane2 YAML configuration file as follows: -``` -VERILOG_DEFINES: -- CLKG_SKY130_HD -``` ### The Interface @@ -73,9 +57,7 @@ VERILOG_DEFINES: |dout|output|4|Flash controller SPI data out.| |din|input|4|Flash controller SPI data in.| |douten|output|4|Flash controller data out enable (Active Low)| -## Firmware Drivers: -Firmware drivers for EF_QSPI_XIP_CTRL can be found in the [fw](https://github.com/efabless/EF_QSPI_XIP_CTRL/tree/main/fw) directory. EF_QSPI_XIP_CTRL driver documentation is available [here](https://github.com/efabless/EF_QSPI_XIP_CTRL/blob/main/fw/README.md). -You can also find an example C application using the EF_QSPI_XIP_CTRL drivers [here](). + ## Installation: You can install the IP either by cloning this repository or by using [IPM](https://github.com/efabless/IPM). ##### 1. Using [IPM](https://github.com/efabless/IPM): diff --git a/docs/EF_QSPI_XIP_CTRL.svg b/docs/EF_QSPI_XIP_CTRL.svg deleted file mode 100644 index 8d5f856..0000000 --- a/docs/EF_QSPI_XIP_CTRL.svg +++ /dev/null @@ -1 +0,0 @@ - LINE_SIZE wire clk wire rst_n wire [23:0] addr wire rd wire [3:0] din wire done wire [(LINE_SIZE*8)-1: 0] line sck ce_n wire [3:0] dout wire douten \ No newline at end of file diff --git a/docs/_static/EF_QSPI_XIP_CTRL.svg b/docs/_static/EF_QSPI_XIP_CTRL.svg new file mode 100644 index 0000000..6b26739 --- /dev/null +++ b/docs/_static/EF_QSPI_XIP_CTRL.svg @@ -0,0 +1 @@ + NUM_LINES LINE_SIZE RESET_CYCLES wire clk wire rst_n wire [23:0] addr wire rd wire [3:0] din wire done wire [(LINE_SIZE*8)-1: 0] line wire sck wire ce_n wire [3:0] dout wire douten \ No newline at end of file diff --git a/hdl/rtl/test.v b/hdl/rtl/test.v new file mode 100644 index 0000000..852e52c --- /dev/null +++ b/hdl/rtl/test.v @@ -0,0 +1,98 @@ +module EF_QSPI_XIP_CTRL #( parameter NUM_LINES = 16, + LINE_SIZE = 16, + RESET_CYCLES= 1023 ) +( + input wire clk, + input wire rst_n, + input wire [23:0] addr, + input wire rd, + output wire done, + output wire [(LINE_SIZE*8)-1: 0] line, + + output wire sck, + output wire ce_n, + input wire [3:0] din, + output wire [3:0] dout, + output wire douten +); + + reg first; + reg d_first; + + + reg rd_rd_; + wire rd_done; + wire rst_done; + + wire rd_sck; + wire rd_ce_n; + wire [3:0] rd_din; + wire [3:0] rd_dout; + wire rd_douten; + + wire rst_sck; + wire rst_ce_n; + wire [3:0] rst_din; + wire [3:0] rst_dout; + wire rst_douten; + + assign done = rd_done; + + assign sck = first ? rst_sck : rd_sck; + assign ce_n = first ? rst_ce_n : rd_ce_n; + assign dout = first ? rst_dout : rd_dout; + assign douten = first ? rst_douten : rd_douten; + + assign rd_din = din; + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + rd_rd_ <= 1'b0; + else if(rst_done) + rd_rd_ <= 1'b1; + else if(rd_rd_) + rd_rd_ <= 1'b0; + + wire rd_rd = d_first ? rd_rd_ : rd; + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + first <= 1'b1; + else if(rst_done) + first <= 1'b0; + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + d_first <= 1'b1; + else + d_first <= first; + + FLASH_READER_QSPI #(.LINE_SIZE(LINE_SIZE)) + READER ( + .clk(clk), + .rst_n(rst_n), + .addr(addr), + .rd(rd_rd), + .done(rd_done), + .line(line), + .sck(rd_sck), + .ce_n(rd_ce_n), + .din(rd_din), + .dout(rd_dout), + .douten(rd_douten) + ); + + FLASH_RESET #(.RESET_CYCLES(RESET_CYCLES)) + RESET ( + .clk(clk), + .rst_n(rst_n), + .start(rd), + .done(rst_done), + .sck(rst_sck), + .ce_n(rst_ce_n), + .din(rst_din), + .dout(rst_dout), + .douten(rst_douten) + ); + +endmodule