From 239e6df803cf7630768720b1513fdbe9fffdd826 Mon Sep 17 00:00:00 2001
From: M0stafaRady <mostafa.rady@efabless.com>
Date: Thu, 10 Oct 2024 12:01:10 +0300
Subject: [PATCH] update the design name

---
 verify/uvm-python/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
index 95819bc..cc3b1b1 100644
--- a/verify/uvm-python/Makefile
+++ b/verify/uvm-python/Makefile
@@ -13,7 +13,7 @@ BUS_TYPE ?= AHB
 GL_MACROS += -DFUNCTIONAL 
 # GL_MACROS += "$(RTL_MACROS) -DFUNCTIONAL -DUNIT_DELAY=##1"
 ## netlist Gen 
-DESIGN_NAME = MS_QSPI_XIP_CACHE_ahbl
+DESIGN_NAME = EF_QSPI_XIP_CTRL_ahbl
 PRE_SYS_FILES = $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
 PDK_DIR = $(HOME)/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/
 PDK_FILES = $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v # get this from openlane logs in the future