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Merge pull request #593 from diffblue/verilog_equality
Verilog logical (in)equality expression
2 parents 345f1a8 + 56778dd commit 61e797f

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3 files changed

+41
-2
lines changed

3 files changed

+41
-2
lines changed

src/hw_cbmc_irep_ids.h

+2
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,8 @@ IREP_ID_ONE(ports)
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IREP_ID_ONE(inst)
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IREP_ID_ONE(Verilog)
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IREP_ID_ONE(verilog_assignment_pattern)
54+
IREP_ID_ONE(verilog_logical_equality)
55+
IREP_ID_ONE(verilog_logical_inequality)
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IREP_ID_ONE(verilog_explicit_cast)
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IREP_ID_ONE(verilog_size_cast)
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IREP_ID_ONE(verilog_implicit_typecast)

src/verilog/parser.y

+2-2
Original file line numberDiff line numberDiff line change
@@ -3541,9 +3541,9 @@ expression:
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| expression TOK_PERCENT expression
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{ init($$, ID_mod); mto($$, $1); mto($$, $3); }
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| expression TOK_EQUALEQUAL expression
3544-
{ init($$, ID_equal); mto($$, $1); mto($$, $3); }
3544+
{ init($$, ID_verilog_logical_equality); mto($$, $1); mto($$, $3); }
35453545
| expression TOK_EXCLAMEQUAL expression
3546-
{ init($$, ID_notequal); mto($$, $1); mto($$, $3); }
3546+
{ init($$, ID_verilog_logical_inequality); mto($$, $1); mto($$, $3); }
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| expression TOK_EQUALEQUALEQUAL expression
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{ init($$, ID_verilog_case_equality); mto($$, $1); mto($$, $3); }
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| expression TOK_EXCLAMEQUALEQUAL expression

src/verilog/verilog_typecheck_expr.cpp

+37
Original file line numberDiff line numberDiff line change
@@ -2404,9 +2404,46 @@ exprt verilog_typecheck_exprt::convert_binary_expr(binary_exprt expr)
24042404

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return std::move(expr);
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}
2407+
else if(
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expr.id() == ID_verilog_logical_equality ||
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expr.id() == ID_verilog_logical_inequality)
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{
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// == and !=
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Forall_operands(it, expr)
2413+
convert_expr(*it);
2414+
2415+
tc_binary_expr(expr);
2416+
2417+
// This returns 'x' if either of the operands contains x or z.
2418+
if(
2419+
expr.lhs().type().id() == ID_verilog_signedbv ||
2420+
expr.lhs().type().id() == ID_verilog_unsignedbv ||
2421+
expr.rhs().type().id() == ID_verilog_signedbv ||
2422+
expr.rhs().type().id() == ID_verilog_unsignedbv)
2423+
{
2424+
// Four-valued case. The ID stays
2425+
// ID_verilog_logical_equality or
2426+
// ID_verilog_logical_inequality.
2427+
expr.type() = verilog_unsignedbv_typet(1);
2428+
}
2429+
else
2430+
{
2431+
// On two-valued logic, it's the same as proper equality.
2432+
expr.type() = bool_typet();
2433+
if(expr.id() == ID_verilog_logical_equality)
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expr.id(ID_equal);
2435+
else
2436+
expr.id(ID_notequal);
2437+
}
2438+
2439+
return std::move(expr);
2440+
}
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else if(expr.id()==ID_verilog_case_equality ||
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expr.id()==ID_verilog_case_inequality)
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{
2444+
// === and !==
2445+
// The result is always Boolean, and semantically
2446+
// a proper equality is performed.
24102447
expr.type()=bool_typet();
24112448

24122449
Forall_operands(it, expr)

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