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Continuation of a bug discovered while debugging #422.
When trying to launch the daemon (all pieces compiled with ARCH_PMC=UMC via locally modified PKGBUILD) on a 3500X running on a X570 platform with various UEFI tweaks, it fails with the following message:
ewout@enthoo ~ % sudo systemctl status corefreqd.service× corefreqd.service - CoreFreq Daemon Loaded: loaded (/usr/lib/systemd/system/corefreqd.service; disabled; preset: disabled) Active: failed (Result: exit-code) since Wed 2023-03-15 21:51:28 CET; 20s ago Duration: 1ms Process: 18888 ExecStart=corefreqd -q (code=exited, status=5) Main PID: 18888 (code=exited, status=5) CPU: 628usmrt 15 21:51:28 enthoo systemd[1]: Started CoreFreq Daemon.mrt 15 21:51:28 enthoo corefreqd[18888]: Driver connection error code 13mrt 15 21:51:28 enthoo corefreqd[18888]: Version 0.0.0: 'Permission denied' @ line 9213mrt 15 21:51:28 enthoo systemd[1]: corefreqd.service: Main process exited, code=exited, status=5/NOTINSTALLEDmrt 15 21:51:28 enthoo systemd[1]: corefreqd.service: Failed with result 'exit-code'.ewout@enthoo ~ %
3500X info
(works fine when not compiled with ARCH_PMC=UMC)
CoreFreq development version from branch linux_6_3.
Processor
Frequencies
IPC
TSC
Idle states
Vcore, Power & Thermal
Memory Controller
(Without ARCH_PMC=UMC)
Features
Technologies
Capabilities
ISA
Processor Information
ewout@enthoo ~ % corefreq-cli -sProcessor [AMD Ryzen 5 3500X 6-Core Processor]|- Architecture [Zen2/Matisse]|- Vendor ID [AuthenticAMD]|- Firmware [ 46.72.0-2]|- Microcode [0x08701030]|- Signature [ 8F_71]|- Stepping [ 0]|- Online CPU [ 2/ 2]|- Base Clock [ 99.810]|- Frequency (MHz) Ratio Min 2195.83 < 22 > Max 3593.17 < 36 >|- Factory [100.000] 3600 [ 36 ]|- Performance |- P-State TGT 3593.17 < 36 > |- CPPC Min 499.05 < 5 > Max 4092.23 < 41 > TGT 1996.21 < 20 >|- Turbo Boost [ UNLOCK] XFR 4092.23 [ 41 ] CPB 4092.23 [ 41 ] 1C 2794.69 < 28 > 2C 2195.83 < 22 >|- Uncore [ LOCK] CLK 1297.54 [ 13 ] MEM 3992.42 [ 40 ]Instruction Set Extensions|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]|- AVX512-BF16 [N] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]|- SERIALIZE [N] SYSCALL [Y] RDPID [Y] UMIP [Y]|- VAES [N] VPCLMULQDQ [N] PREFETCH/W [Y] LZCNT [Y]Features|- 1 GB Pages Support 1GB-PAGES [Capable]|- 100 MHz multiplier Control 100MHzSteps [Missing]|- Advanced Configuration & Power Interface ACPI [Capable]|- Advanced Programmable Interrupt Controller APIC [Capable]|- Advanced Virtual Interrupt Controller AVIC [Capable]|- APIC Timer Invariance ARAT [Capable]|- Clear Zero Instruction CLZERO [Capable]|- Core Multi-Processing CMP Legacy [Capable]|- L1 Data Cache Context ID CNXT-ID [Missing]|- Collaborative Processor Performance Control CPPC [Capable]|- Direct Cache Access DCA [Missing]|- Debugging Extension DE [Capable]|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]|- CPL Qualified Debug Store DS-CPL [Missing]|- 64-Bit Debug Store DTES64 [Missing]|- Fast Short REP MOVSB FSRM [Missing]|- Fast-String Operation ERMS [Missing]|- Fused Multiply Add FMA | FMA4 [Capable]|- Hardware Lock Elision HLE [Missing]|- Hardware P-state control HwP [Capable]|- Instruction Based Sampling IBS [Capable]|- Instruction INVLPGB INVLPGB [Missing]|- Instruction INVPCID INVPCID [Missing]|- Long Mode 64 bits IA64 | LM [Capable]|- LightWeight Profiling LWP [Missing]|- Memory Bandwidth Enforcement MBE [Capable]|- Machine-Check Architecture MCA [Capable]|- Instruction MCOMMIT MCOMMIT [Missing]|- Memory Protection Extensions MPX [Missing]|- Model Specific Registers MSR [Capable]|- Memory Type Range Registers MTRR [Capable]|- No-Execute Page Protection NX [Capable]|- OS-Enabled Ext. State Management OSXSAVE [Capable]|- Physical Address Extension PAE [Capable]|- Page Attribute Table PAT [Capable]|- Pending Break Enable PBE [Missing]|- Process Context Identifiers PCID [Missing]|- Perfmon and Debug Capability PDCM [Missing]|- Page Global Enable PGE [Capable]|- Page Size Extension PSE [Capable]|- 36-bit Page Size Extension PSE36 [Capable]|- Processor Serial Number PSN [Missing]|- Resource Director Technology/PQE RDT-A [Capable]|- Resource Director Technology/PQM RDT-M [Capable]|- Read Processor Register at User level RDPRU [Capable]|- Restricted Transactional Memory RTM [Missing]|- Safer Mode Extensions SMX [Missing]|- Self-Snoop SS [Missing]|- Supervisor-Mode Access Prevention SMAP [Capable]|- Supervisor-Mode Execution Prevention SMEP [Capable]|- Time Stamp Counter TSC [Invariant]|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]|- TSX Force Abort MSR Register TSX-ABORT [Missing]|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]|- User-Mode Instruction Prevention UMIP [Capable]|- Virtual Mode Extension VME [Capable]|- Virtual Machine Extensions VMX [Missing]|- Write Back & Do Not Invalidate Cache WBNOINVD [Capable]|- Extended xAPIC Support x2APIC [ xAPIC]|- AVIC controller for x2APIC x2AVIC [Missing]|- XSAVE/XSTOR States XSAVE [Capable]|- xTPR Update Control xTPR [Missing]Mitigation mechanisms|- Indirect Branch Restricted Speculation IBRS [ Unable] |- IBRS Always-On preferred by processor [ Unable] |- IBRS preferred over software solution [Capable] |- IBRS provides same speculation limits [Capable]|- Indirect Branch Prediction Barrier IBPB [Capable]|- Single Thread Indirect Branch Predictor STIBP [Capable]|- Speculative Store Bypass Disable SSBD [Capable] |- SSBD use VIRT_SPEC_CTRL register [ Unable] |- SSBD not needed on this processor [ Unable]|- No Branch Type Confusion BTC_NO [ Unable]|- BTC on Non-Branch instruction BTC-NOBR [ Enable]|- Arch - No Fast Predictive Store Forwarding PSFD [ Unable]Security Features|- Secure Init and Jump with Attestation SKINIT [Capable]|- Secure Encrypted Virtualization SEV [Capable]|- SEV - Encrypted State SEV-ES [Capable]|- SEV - Secure Nested Paging SEV-SNP [Missing]|- Guest Mode Execute Trap GMET [Capable]|- Supervisor Shadow Stack SSS [Missing]|- VM Permission Levels VMPL [Missing]|- VMPL Supervisor Shadow Stack VMPL-SSS [Missing]|- Secure Memory Encryption SME [Capable]|- Transparent SME TSME [Disable]|- Secure Multi-Key Memory Encryption SME-MK [Missing]|- DRAM Data Scrambling Scrambler [ Enable]Technologies|- Instruction Cache Unit |- L1 IP Prefetcher L1 HW IP < ON>|- Data Cache Unit |- L1 Prefetcher L1 HW < ON> |- L2 Prefetcher L2 HW < ON>|- System Management Mode SMM-Lock [ ON]|- Simultaneous Multithreading SMT [OFF]|- PowerNow! CnQ [ ON]|- Core C-States CCx [ ON]|- Core Performance Boost CPB <OFF>|- Watchdog Timer WDT < ON>|- Virtualization SVM [OFF] |- I/O MMU AMD-V [ ON] |- Version [ 0.1] |- Hypervisor [OFF] |- Vendor ID [ N/A]Performance Monitoring|- Version PM [ 1]|- Counters: General Fixed| { 6, 6, 4 } x 48 bits 3 x 64 bits|- Enhanced Halt State C1E <OFF>|- C2 UnDemotion C2U <OFF>|- C3 UnDemotion C3U < ON>|- Core C6 State CC6 <OFF>|- Package C6 State PC6 < ON>|- Legacy Frequency ID control FID [OFF]|- Legacy Voltage ID control VID [OFF]|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]|- Core C-States |- C-States Base Address BAR [ 0x413 ]|- ACPI Processor C-States _CST [ 2]|- MONITOR/MWAIT |- State index: #0 #1 #2 #3 #4 #5 #6 #7 |- Sub C-State: 1 1 0 0 0 0 0 0|- Core Cycles [Capable]|- Instructions Retired [Capable]|- Reference Cycles [Capable]|- Last Level Cache References [Capable]|- Global Time Stamp Counter [Missing]|- Data Fabric Performance Counter [Capable]|- Core Performance Counter [Capable]|- Processor Performance Control _PCT [ Enable]|- Performance Supported States _PSS [ 3]|- Performance Present Capabilities _PPC [ 0]|- Continuous Performance Control _CPC [ Enable]Power, Current & Thermal|- Temperature Offset:Junction TjMax [ 49: 95 C]|- CPPC Energy Preference EPP [Missing]|- Digital Thermal Sensor DTS [Capable]|- Power Limit Notification PLN [Missing]|- Package Thermal Management PTM [Missing]|- Thermal Monitor 1 TTP [ Enable]|- Thermal Monitor 2 HTC [ Enable]|- Thermal Design Power TDP [ 65 W] |- Minimum Power Min [ 65 W] |- Maximum Power Max [ 65 W]|- Thermal Design Power Package < Enable> |- Power Limit PL1 < 40 W> |- Time Window TW1 < 0 ns> |- Power Limit PL2 < 540 W> |- Time Window TW2 < 0 ns>|- Thermal Design Power Core [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns]|- Thermal Design Power Uncore [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns]|- Thermal Design Power DRAM [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns]|- Thermal Design Power Platform [Disable] |- Power Limit PL1 [ 0 W] |- Time Window TW1 [ 0 ns] |- Power Limit PL2 [ 0 W] |- Time Window TW2 [ 0 ns]|- Package Power Tracking PPT [ 88 W]|- Electrical Design Current EDC [ 88 A]|- Thermal Design Current TDC [ 60 A]|- Core Thermal Point|- Package Thermal Point |- Thermal Monitor Trip Limit [ 115 C] |- HTC Temperature Limit Limit [ 127 C] |- HTC Temperature Hysteresis Threshold [ 2 C]|- Units |- Power watt [ 0.125000000] |- Energy joule [ 0.000015259] |- Window second [ 0.000976562]ewout@enthoo ~ %
Apparently PMC appears not to be programmed the same on Zen architecture families.
Reason I will keep this feature as a build option. There's not enough explanations in specifications.
No idea how to manage acpi_idle
I prevent drivers from loading and make CoreFreq registers itself as the CPU-Idle handler. When done, I set kernel to put Core(s) in I/O wait.
In kernel window, you will next change default C2 to C6 (technically: I/O read at base address + C6 index)
Registration can be requested from the Settings window.
Just make sure mainstream drivers are blacklisted or unloaded before corefreqk.ko
More in my Wiki
Continuation of a bug discovered while debugging #422.
When trying to launch the daemon (all pieces compiled with
ARCH_PMC=UMC
via locally modified PKGBUILD) on a 3500X running on a X570 platform with various UEFI tweaks, it fails with the following message:3500X info
(works fine when not compiled with
ARCH_PMC=UMC
)Processor
Frequencies
IPC
TSC
Idle states
Vcore, Power & Thermal
Memory Controller
(Without
ARCH_PMC=UMC
)Features
Technologies
Capabilities
ISA
Processor Information
CPPC
System Information
BIOS
X570 I AORUS PRO WIFI (UEFI version F37a, AMD AGESA V2 1.2.0.8)
Kernel
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