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corefreqk.c
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/*
* CoreFreq
* Copyright (C) 2015-2021 CYRIL INGENIERIE
* Licenses: GPL2
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/cpu.h>
#include <linux/pci.h>
#ifdef CONFIG_DMI
#include <linux/dmi.h>
#endif /* CONFIG_DMI */
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/cdev.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/percpu.h>
#include <linux/utsname.h>
#ifdef CONFIG_CPU_IDLE
#include <linux/cpuidle.h>
#endif /* CONFIG_CPU_IDLE */
#ifdef CONFIG_CPU_FREQ
#include <linux/cpufreq.h>
#endif /* CONFIG_CPU_FREQ */
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
#include <linux/sched/signal.h>
#endif /* KERNEL_VERSION(4, 11, 0) */
#include <linux/clocksource.h>
#include <asm/msr.h>
#include <asm/nmi.h>
#ifdef CONFIG_XEN
#include <xen/xen.h>
#endif /* CONFIG_XEN */
#include <asm/mwait.h>
#include "bitasm.h"
#include "amdmsr.h"
#include "intelmsr.h"
#include "coretypes.h"
#include "corefreq-api.h"
#include "corefreqk.h"
#ifdef CONFIG_AMD_NB
#include <asm/amd_nb.h>
#endif
MODULE_AUTHOR ("CYRIL INGENIERIE <labs[at]cyring[dot]fr>");
MODULE_DESCRIPTION ("CoreFreq Processor Driver");
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)
MODULE_SUPPORTED_DEVICE ("Intel,AMD,HYGON");
#endif
MODULE_LICENSE ("GPL");
MODULE_VERSION (COREFREQ_VERSION);
static signed int ArchID = -1;
module_param(ArchID, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(ArchID, "Force an architecture (ID)");
static signed int AutoClock = 0b11;
module_param(AutoClock, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(AutoClock, "Estimate Clock Frequency 0:Spec; 1:Once; 2:Auto");
static unsigned int SleepInterval = 0;
module_param(SleepInterval, uint, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(SleepInterval, "Timer interval (ms)");
static unsigned int TickInterval = 0;
module_param(TickInterval, uint, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(TickInterval, "System requested interval (ms)");
static signed int Experimental = 0;
module_param(Experimental, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Experimental, "Enable features under development");
static signed int CPU_Count = -1;
module_param(CPU_Count, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(CPU_Count, "-1:Kernel(default); 0:Hardware; >0: User value");
static signed short Target_Ratio_Unlock = -1;
module_param(Target_Ratio_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Target_Ratio_Unlock, "1:Target Ratio Unlock; 0:Lock");
static signed short Clock_Ratio_Unlock = -1;
module_param(Clock_Ratio_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Clock_Ratio_Unlock, "1:MinRatio; 2:MaxRatio; 3:Both Unlock");
static signed short Turbo_Ratio_Unlock = -1;
module_param(Turbo_Ratio_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Turbo_Ratio_Unlock, "1:Turbo Ratio Unlock; 0:Lock");
static signed short Uncore_Ratio_Unlock = -1;
module_param(Uncore_Ratio_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Uncore_Ratio_Unlock, "1:Uncore Ratio Unlock; 0:Lock");
static signed int ServiceProcessor = -1; /* -1=ANY ; 0=BSP */
module_param(ServiceProcessor, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(ServiceProcessor, "Select a CPU to run services with");
static SERVICE_PROC DefaultSMT = {.Proc = -1};
static unsigned short RDPMC_Enable = 0;
module_param(RDPMC_Enable, ushort, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(RDPMC_Enable, "Enable RDPMC bit in CR4 register");
static unsigned short NMI_Disable = 1;
module_param(NMI_Disable, ushort, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(NMI_Disable, "Disable the NMI Handler");
static int Override_SubCstate_Depth = 0;
static unsigned short Override_SubCstate[CPUIDLE_STATE_MAX] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
module_param_array( Override_SubCstate,ushort, &Override_SubCstate_Depth, \
S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Override_SubCstate, "Override Sub C-States");
static signed short PkgCStateLimit = -1;
module_param(PkgCStateLimit, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(PkgCStateLimit, "Package C-State Limit");
static signed short IOMWAIT_Enable = -1;
module_param(IOMWAIT_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(IOMWAIT_Enable, "I/O MWAIT Redirection Enable");
static signed short CStateIORedir = -1;
module_param(CStateIORedir, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(CStateIORedir, "Power Mgmt IO Redirection C-State");
static signed short Config_TDP_Level = -1;
module_param(Config_TDP_Level, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Config_TDP_Level, "Config TDP Control Level");
static unsigned int Custom_TDP_Count = 0;
static signed short Custom_TDP_Offset[PWR_LIMIT_SIZE * PWR_DOMAIN(SIZE)] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
module_param_array(Custom_TDP_Offset, short, &Custom_TDP_Count , \
S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Custom_TDP_Offset, "TDP Limit Offset (watt)");
static unsigned int TDP_Limiting_Count = 0;
static signed short Activate_TDP_Limit[PWR_LIMIT_SIZE * PWR_DOMAIN(SIZE)] = {
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
module_param_array(Activate_TDP_Limit, short, &TDP_Limiting_Count, \
S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Activate_TDP_Limit, "Activate TDP Limiting");
static unsigned int TDP_Clamping_Count = 0;
static signed short Activate_TDP_Clamp[PWR_LIMIT_SIZE * PWR_DOMAIN(SIZE)] = {
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
module_param_array(Activate_TDP_Clamp, short, &TDP_Clamping_Count, \
S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Activate_TDP_Clamp, "Activate TDP Clamping");
static unsigned short Custom_TDC_Offset = 0;
module_param(Custom_TDC_Offset, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Custom_TDC_Offset, "TDC Limit Offset (amp)");
static signed short Activate_TDC_Limit = -1;
module_param(Activate_TDC_Limit, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Activate_TDC_Limit, "Activate TDC Limiting");
static signed short L1_HW_PREFETCH_Disable = -1;
module_param(L1_HW_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(L1_HW_PREFETCH_Disable, "Disable L1 HW Prefetcher");
static signed short L1_HW_IP_PREFETCH_Disable = -1;
module_param(L1_HW_IP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(L1_HW_IP_PREFETCH_Disable, "Disable L1 HW IP Prefetcher");
static signed short L2_HW_PREFETCH_Disable = -1;
module_param(L2_HW_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(L2_HW_PREFETCH_Disable, "Disable L2 HW Prefetcher");
static signed short L2_HW_CL_PREFETCH_Disable = -1;
module_param(L2_HW_CL_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(L2_HW_CL_PREFETCH_Disable, "Disable L2 HW CL Prefetcher");
static signed short SpeedStep_Enable = -1;
module_param(SpeedStep_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(SpeedStep_Enable, "Enable SpeedStep");
static signed short C1E_Enable = -1;
module_param(C1E_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(C1E_Enable, "Enable SpeedStep C1E");
static signed short TurboBoost_Enable = -1;
module_param(TurboBoost_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(TurboBoost_Enable, "Enable Turbo Boost");
static signed short C3A_Enable = -1;
module_param(C3A_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(C3A_Enable, "Enable C3 Auto Demotion");
static signed short C1A_Enable = -1;
module_param(C1A_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(C1A_Enable, "Enable C3 Auto Demotion");
static signed short C3U_Enable = -1;
module_param(C3U_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(C3U_Enable, "Enable C3 UnDemotion");
static signed short C1U_Enable = -1;
module_param(C1U_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(C1U_Enable, "Enable C1 UnDemotion");
static signed short CC6_Enable = -1;
module_param(CC6_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(CC6_Enable, "Enable Core C6 State");
static signed short PC6_Enable = -1;
module_param(PC6_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(PC6_Enable, "Enable Package C6 State");
static signed short ODCM_Enable = -1;
module_param(ODCM_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(ODCM_Enable, "Enable On-Demand Clock Modulation");
static signed short ODCM_DutyCycle = -1;
module_param(ODCM_DutyCycle, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(ODCM_DutyCycle, "ODCM DutyCycle [0-7] | [0-14]");
static signed short PowerMGMT_Unlock = -1;
module_param(PowerMGMT_Unlock, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(PowerMGMT_Unlock, "Unlock Power Management");
static signed short PowerPolicy = -1;
module_param(PowerPolicy, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(PowerPolicy, "Power Policy Preference [0-15]");
static signed short Turbo_Activation_Ratio = -1;
module_param(Turbo_Activation_Ratio, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Turbo_Activation_Ratio, "Turbo Activation Ratio");
static signed int PState_FID = -1;
module_param(PState_FID, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(PState_FID, "P-State Frequency Id");
static signed int PState_VID = -1;
module_param(PState_VID, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(PState_VID, "P-State Voltage Id");
static signed short HWP_Enable = -1;
module_param(HWP_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(HWP_Enable, "Hardware-Controlled Performance States");
static signed short HWP_EPP = -1;
module_param(HWP_EPP, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(HWP_EPP, "Energy Performance Preference");
static signed short HDC_Enable = -1;
module_param(HDC_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(HDC_Enable, "Hardware Duty Cycling");
static signed short EEO_Disable = -1;
module_param(EEO_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(EEO_Disable, "Disable Energy Efficiency Optimization");
static signed short R2H_Disable = -1;
module_param(R2H_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(R2H_Disable, "Disable Race to Halt");
static unsigned int Clear_Events = 0;
module_param(Clear_Events, uint, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Clear_Events, "Clear Thermal and Power Events");
static int ThermalScope = -1;
module_param(ThermalScope, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(ThermalScope, "[0:None; 1:SMT; 2:Core; 3:Package]");
static int VoltageScope = -1;
module_param(VoltageScope, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(VoltageScope, "[0:None; 1:SMT; 2:Core; 3:Package]");
static int PowerScope = -1;
module_param(PowerScope, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(PowerScope, "[0:None; 1:SMT; 2:Core; 3:Package]");
static signed short Register_CPU_Idle = -1;
module_param(Register_CPU_Idle, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Register_CPU_Idle, "Register the Kernel cpuidle driver");
static signed short Register_CPU_Freq = -1;
module_param(Register_CPU_Freq, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Register_CPU_Freq, "Register the Kernel cpufreq driver");
static signed short Register_Governor = -1;
module_param(Register_Governor, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Register_Governor, "Register the Kernel governor");
static signed short Register_ClockSource = -1;
module_param(Register_ClockSource, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Register_ClockSource, "Register Clock Source driver");
static signed short Idle_Route = -1;
module_param(Idle_Route, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Idle_Route, "[0:Default; 1:I/O; 2:HALT; 3:MWAIT]");
static signed short Mech_IBRS = -1;
module_param(Mech_IBRS, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Mech_IBRS, "Mitigation Mechanism IBRS");
static signed short Mech_STIBP = -1;
module_param(Mech_STIBP, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Mech_STIBP, "Mitigation Mechanism STIBP");
static signed short Mech_SSBD = -1;
module_param(Mech_SSBD, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Mech_SSBD, "Mitigation Mechanism SSBD");
static signed short Mech_IBPB = -1;
module_param(Mech_IBPB, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Mech_IBPB, "Mitigation Mechanism IBPB");
static signed short Mech_L1D_FLUSH = -1;
module_param(Mech_L1D_FLUSH, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Mech_L1D_FLUSH, "Mitigation Mechanism Cache L1D Flush");
static signed short Mech_PSFD = -1;
module_param(Mech_PSFD, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(Mech_PSFD, "Mitigation Mechanism PSFD");
static signed short WDT_Enable = -1;
module_param(WDT_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(WDT_Enable, "Watchdog Hardware Timer");
static struct {
signed int Major;
struct cdev *kcdev;
dev_t nmdev, mkdev;
struct class *clsdev;
#ifdef CONFIG_CPU_IDLE
struct cpuidle_device __percpu *IdleDevice;
struct cpuidle_driver IdleDriver;
#endif /* CONFIG_CPU_IDLE */
#ifdef CONFIG_CPU_FREQ
struct cpufreq_driver FreqDriver;
struct cpufreq_governor FreqGovernor;
#endif /* CONFIG_CPU_FREQ */
} CoreFreqK = {
#ifdef CONFIG_CPU_IDLE
.IdleDriver = {
.name = "corefreqk-idle",
.owner = THIS_MODULE
},
#endif /* CONFIG_CPU_IDLE */
#ifdef CONFIG_CPU_FREQ
.FreqDriver = {
.name = "corefreqk-perf",
.flags = CPUFREQ_CONST_LOOPS,
.exit = CoreFreqK_Policy_Exit,
/*MANDATORY*/ .init = CoreFreqK_Policy_Init,
/*MANDATORY*/ .verify = CoreFreqK_Policy_Verify,
/*MANDATORY*/ .setpolicy = CoreFreqK_SetPolicy,
.bios_limit= CoreFreqK_Bios_Limit,
.set_boost = CoreFreqK_SetBoost
},
.FreqGovernor = {
.name = "corefreq-policy",
.owner = THIS_MODULE,
.show_setspeed = CoreFreqK_Show_SetSpeed,
.store_setspeed = CoreFreqK_Store_SetSpeed
}
#endif /* CONFIG_CPU_FREQ */
};
static KPUBLIC *KPublic = NULL;
static KPRIVATE *KPrivate = NULL;
static ktime_t RearmTheTimer;
#define AT( _loc_ ) [ _loc_ ]
#define OF( _ptr_ , ...) -> _ptr_ __VA_ARGS__
#define RO( _ptr_ , ...) OF( _ptr_##_RO , __VA_ARGS__ )
#define RW( _ptr_ , ...) OF( _ptr_##_RW , __VA_ARGS__ )
#define ADDR( _head_ , _mbr_ ) ( _head_ _mbr_ )
#define PUBLIC(...) ADDR( KPublic , __VA_ARGS__ )
#define PRIVATE(...) ADDR( KPrivate, __VA_ARGS__ )
#define RESET_ARRAY(_array, _cnt, _val, ... ) \
({ \
unsigned int rst; \
for (rst = 0; rst < _cnt; rst++) { \
_array[rst] __VA_ARGS__ = _val; \
} \
})
static long CoreFreqK_Thermal_Scope(int scope)
{
if ((scope >= FORMULA_SCOPE_NONE) && (scope <= FORMULA_SCOPE_PKG))
{
PUBLIC(RO(Proc))->thermalFormula = \
(KIND_OF_FORMULA(PUBLIC(RO(Proc))->thermalFormula) << 8)|scope;
return (RC_SUCCESS);
} else {
return (-EINVAL);
}
}
static long CoreFreqK_Voltage_Scope(int scope)
{
if ((scope >= FORMULA_SCOPE_NONE) && (scope <= FORMULA_SCOPE_PKG))
{
PUBLIC(RO(Proc))->voltageFormula = \
(KIND_OF_FORMULA(PUBLIC(RO(Proc))->voltageFormula) << 8)|scope;
return (RC_SUCCESS);
} else {
return (-EINVAL);
}
}
static long CoreFreqK_Power_Scope(int scope)
{
if ((scope >= FORMULA_SCOPE_NONE) && (scope <= FORMULA_SCOPE_PKG))
{
PUBLIC(RO(Proc))->powerFormula = \
(KIND_OF_FORMULA(PUBLIC(RO(Proc))->powerFormula) << 8)|scope;
return (RC_SUCCESS);
} else {
return (-EINVAL);
}
}
unsigned int FixMissingRatioAndFrequency(unsigned int r32, CLOCK *pClock)
{
unsigned long long r64 = r32;
if (PUBLIC(RO(Proc))->Features.Factory.Freq != 0)
{
if ((r32 == 0) && (pClock->Q > 0))
{ /* Fix missing ratio. */
r64=DIV_ROUND_CLOSEST(PUBLIC(RO(Proc))->Features.Factory.Freq, pClock->Q);
PUBLIC(RO(Core,AT(PUBLIC(RO(Proc))->Service.Core)))->Boost[BOOST(MAX)]=\
(unsigned int) r64;
}
}
else if (r32 > 0)
{ /* Fix the Factory frequency (unit: MHz) */
r64 = pClock->Hz * r32;
r64 = r64 / 1000000LLU;
PUBLIC(RO(Proc))->Features.Factory.Freq = (unsigned int) r64;
}
PUBLIC(RO(Proc))->Features.Factory.Clock.Q = pClock->Q;
PUBLIC(RO(Proc))->Features.Factory.Clock.R = pClock->R;
PUBLIC(RO(Proc))->Features.Factory.Clock.Hz = pClock->Hz;
if (PUBLIC(RO(Proc))->Features.Factory.Clock.Hz > 0)
{
r64 = PUBLIC(RO(Proc))->Features.Factory.Freq * 1000000LLU;
r64 = DIV_ROUND_CLOSEST(r64, PUBLIC(RO(Proc))->Features.Factory.Clock.Hz);
PUBLIC(RO(Proc))->Features.Factory.Ratio = (unsigned int) r64;
}
return ((unsigned int) r64);
}
unsigned long long CoreFreqK_Read_CS_From_Invariant_TSC(struct clocksource *cs)
{
unsigned long long TSC __attribute__ ((aligned (8)));
UNUSED(cs);
RDTSCP64(TSC);
return (TSC);
}
unsigned long long CoreFreqK_Read_CS_From_Variant_TSC(struct clocksource *cs)
{
unsigned long long TSC __attribute__ ((aligned (8)));
UNUSED(cs);
RDTSC64(TSC);
return (TSC);
}
static struct clocksource CoreFreqK_CS = {
.name = "corefreq",
.rating = 250,
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static long CoreFreqK_UnRegister_ClockSource(void)
{
long rc = -EINVAL;
if (PUBLIC(RO(Proc))->Registration.Driver.CS & REGISTRATION_ENABLE)
{
int rx = clocksource_unregister(&CoreFreqK_CS);
switch ( rx ) {
case 0:
PUBLIC(RO(Proc))->Registration.Driver.CS = REGISTRATION_DISABLE;
rc = RC_SUCCESS;
break;
default:
rc = (long) rx;
break;
}
}
return (rc);
}
static long CoreFreqK_Register_ClockSource(unsigned int cpu)
{
long rc = -EINVAL;
if (Register_ClockSource == 1)
{
unsigned long long Freq_Hz;
unsigned int Freq_KHz;
if ((PUBLIC(RO(Proc))->Features.AdvPower.EDX.Inv_TSC == 1)
|| (PUBLIC(RO(Proc))->Features.ExtInfo.EDX.RDTSCP == 1))
{
CoreFreqK_CS.read = CoreFreqK_Read_CS_From_Invariant_TSC;
}
else
{
CoreFreqK_CS.read = CoreFreqK_Read_CS_From_Variant_TSC;
}
Freq_Hz = PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MAX)]
* PUBLIC(RO(Core, AT(cpu)))->Clock.Hz;
Freq_KHz = Freq_Hz / 1000U;
if (Freq_KHz != 0)
{
int rx = clocksource_register_khz(&CoreFreqK_CS, Freq_KHz);
switch (rx) {
default:
fallthrough;
case -EBUSY:
PUBLIC(RO(Proc))->Registration.Driver.CS = REGISTRATION_DISABLE;
rc = (long) rx;
break;
case 0:
PUBLIC(RO(Proc))->Registration.Driver.CS = REGISTRATION_ENABLE;
rc = RC_SUCCESS;
pr_debug("%s: Freq_KHz[%u] Kernel CPU_KHZ[%u] TSC_KHZ[%u]\n" \
"LPJ[%lu] mask[%llx] mult[%u] shift[%u]\n",
CoreFreqK_CS.name, Freq_KHz, cpu_khz, tsc_khz, loops_per_jiffy,
CoreFreqK_CS.mask, CoreFreqK_CS.mult, CoreFreqK_CS.shift);
break;
}
}
} else {
PUBLIC(RO(Proc))->Registration.Driver.CS = REGISTRATION_DISABLE;
}
return (rc);
}
void VendorFromCPUID( char *pVendorID, unsigned int *pLargestFunc,
unsigned int *pCRC, enum HYPERVISOR *pHypervisor,
unsigned long leaf, unsigned long subLeaf )
{
struct {
char *vendorID;
size_t vendorLen;
enum CRC_MANUFACTURER mfrCRC;
enum HYPERVISOR hypervisor;
} mfrTbl[] = {
{VENDOR_INTEL ,__builtin_strlen(VENDOR_INTEL) ,CRC_INTEL , BARE_METAL},
{VENDOR_AMD ,__builtin_strlen(VENDOR_AMD) ,CRC_AMD , BARE_METAL},
{VENDOR_HYGON ,__builtin_strlen(VENDOR_HYGON) ,CRC_HYGON , BARE_METAL},
{VENDOR_KVM ,__builtin_strlen(VENDOR_KVM) ,CRC_KVM , HYPERV_KVM},
{VENDOR_VBOX ,__builtin_strlen(VENDOR_VBOX) ,CRC_VBOX , HYPERV_VBOX},
{VENDOR_KBOX ,__builtin_strlen(VENDOR_KBOX) ,CRC_KBOX , HYPERV_KBOX},
{VENDOR_VMWARE ,__builtin_strlen(VENDOR_VMWARE),CRC_VMWARE,HYPERV_VMWARE},
{VENDOR_HYPERV ,__builtin_strlen(VENDOR_HYPERV),CRC_HYPERV,HYPERV_HYPERV}
};
unsigned int eax = 0x0, ebx = 0x0, ecx = 0x0, edx = 0x0; /*DWORD Only!*/
__asm__ volatile
(
"movq %4, %%rax \n\t"
"movq %5, %%rcx \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (eax),
"=r" (ebx),
"=r" (ecx),
"=r" (edx)
: "ir" (leaf),
"ir" (subLeaf)
: "%rax", "%rbx", "%rcx", "%rdx"
);
pVendorID[ 0] = ebx;
pVendorID[ 1] = (ebx >> 8);
pVendorID[ 2] = (ebx >> 16);
pVendorID[ 3] = (ebx >> 24);
pVendorID[ 4] = edx;
pVendorID[ 5] = (edx >> 8);
pVendorID[ 6] = (edx >> 16);
pVendorID[ 7] = (edx >> 24);
pVendorID[ 8] = ecx;
pVendorID[ 9] = (ecx >> 8);
pVendorID[10] = (ecx >> 16);
pVendorID[11] = (ecx >> 24);
pVendorID[12] = '\0';
(*pLargestFunc) = eax;
for (eax = 0; eax < sizeof(mfrTbl) / sizeof(mfrTbl[0]); eax++) {
if (!strncmp(pVendorID, mfrTbl[eax].vendorID, mfrTbl[eax].vendorLen))
{
(*pCRC) = mfrTbl[eax].mfrCRC;
(*pHypervisor) = mfrTbl[eax].hypervisor;
return;
}
}
}
signed int SearchArchitectureID(void)
{
signed int id;
for (id = ARCHITECTURES - 1; id > 0; id--)
{ /* Search for an architecture signature. */
if ( (PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily \
== Arch[id].Signature.ExtFamily)
&& (PUBLIC(RO(Proc))->Features.Std.EAX.Family \
== Arch[id].Signature.Family)
&& ( ( (PUBLIC(RO(Proc))->Features.Std.EAX.ExtModel \
== Arch[id].Signature.ExtModel)
&& (PUBLIC(RO(Proc))->Features.Std.EAX.Model \
== Arch[id].Signature.Model) )
|| (!Arch[id].Signature.ExtModel \
&& !Arch[id].Signature.Model) ) )
{
break;
}
}
return (id);
}
void BrandCleanup(char *pBrand, char inOrder[])
{
unsigned long ix, jx;
for (jx = 0; jx < BRAND_LENGTH; jx++) {
if (inOrder[jx] != 0x20) {
break;
}
}
for (ix = 0; jx < BRAND_LENGTH; jx++) {
if (!(inOrder[jx] == 0x20 && inOrder[jx + 1] == 0x20)) {
pBrand[ix++] = inOrder[jx];
}
}
}
void BrandFromCPUID(char *buffer)
{
BRAND Brand;
unsigned long ix;
unsigned int jx , px = 0;
for (ix = 0; ix < 3; ix++)
{ __asm__ volatile
(
"movq %4, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (Brand.AX),
"=r" (Brand.BX),
"=r" (Brand.CX),
"=r" (Brand.DX)
: "r" (0x80000002LU + ix)
: "%rax", "%rbx", "%rcx", "%rdx"
);
for (jx = 0; jx < 4; jx++, px++) {
buffer[px ] = Brand.AX.Chr[jx];
buffer[px + 4] = Brand.BX.Chr[jx];
buffer[px + 8] = Brand.CX.Chr[jx];
buffer[px + 12] = Brand.DX.Chr[jx];
}
px += BRAND_PART;
}
}
unsigned int Intel_Brand(char *pBrand, char buffer[])
{
unsigned int ix, frequency = 0, multiplier = 0;
BrandFromCPUID(buffer);
for (ix = 0; ix < (BRAND_LENGTH - 2); ix++)
{
if ((buffer[ix + 1] == 'H') && (buffer[ix + 2] == 'z')) {
switch (buffer[ix]) {
case 'M':
multiplier = 1;
break;
case 'G':
multiplier = 1000;
break;
case 'T':
multiplier = 1000000;
break;
}
break;
}
}
if (multiplier > 0)
{
if (buffer[ix - 3] == '.') {
frequency = (int) (buffer[ix - 4] - '0') * multiplier;
frequency += (int) (buffer[ix - 2] - '0') * (multiplier / 10);
frequency += (int) (buffer[ix - 1] - '0') * (multiplier / 100);
} else {
frequency = (int) (buffer[ix - 4] - '0') * 1000;
frequency += (int) (buffer[ix - 3] - '0') * 100;
frequency += (int) (buffer[ix - 2] - '0') * 10;
frequency += (int) (buffer[ix - 1] - '0');
frequency *= frequency;
}
}
BrandCleanup(pBrand, buffer);
return (frequency);
}
/* Retreive the Processor(BSP) features. */
static void Query_Features(void *pArg)
{ /* Must have x86 CPUID 0x0, 0x1, and Intel CPUID 0x4 */
INIT_ARG *iArg = (INIT_ARG *) pArg;
unsigned int eax = 0x0, ebx = 0x0, ecx = 0x0, edx = 0x0; /*DWORD Only!*/
enum HYPERVISOR hypervisor = HYPERV_NONE;
VendorFromCPUID(iArg->Features->Info.Vendor.ID,
&iArg->Features->Info.LargestStdFunc,
&iArg->Features->Info.Vendor.CRC,
&hypervisor,
0x0LU, 0x0LU);
if (hypervisor != BARE_METAL) {
iArg->rc = -ENXIO;
return;
}
__asm__ volatile
(
"movq $0x1, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (iArg->Features->Std.EAX),
"=r" (iArg->Features->Std.EBX),
"=r" (iArg->Features->Std.ECX),
"=r" (iArg->Features->Std.EDX)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
if (iArg->Features->Info.LargestStdFunc >= 0x5)
{
__asm__ volatile
(
"movq $0x5, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (iArg->Features->MWait.EAX),
"=r" (iArg->Features->MWait.EBX),
"=r" (iArg->Features->MWait.ECX),
"=r" (iArg->Features->MWait.EDX)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
switch (Override_SubCstate_Depth) {
case 8:
iArg->Features->MWait.EDX.SubCstate_MWAIT7 = Override_SubCstate[7];
fallthrough;
case 7:
iArg->Features->MWait.EDX.SubCstate_MWAIT6 = Override_SubCstate[6];
fallthrough;
case 6:
iArg->Features->MWait.EDX.SubCstate_MWAIT5 = Override_SubCstate[5];
fallthrough;
case 5:
iArg->Features->MWait.EDX.SubCstate_MWAIT4 = Override_SubCstate[4];
fallthrough;
case 4:
iArg->Features->MWait.EDX.SubCstate_MWAIT3 = Override_SubCstate[3];
fallthrough;
case 3:
iArg->Features->MWait.EDX.SubCstate_MWAIT2 = Override_SubCstate[2];
fallthrough;
case 2:
iArg->Features->MWait.EDX.SubCstate_MWAIT1 = Override_SubCstate[1];
fallthrough;
case 1:
iArg->Features->MWait.EDX.SubCstate_MWAIT0 = Override_SubCstate[0];
break;
};
}
if (iArg->Features->Info.LargestStdFunc >= 0x6)
{
__asm__ volatile
(
"movq $0x6, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (iArg->Features->Power.EAX),
"=r" (iArg->Features->Power.EBX),
"=r" (iArg->Features->Power.ECX),
"=r" (iArg->Features->Power.EDX)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
}
if (iArg->Features->Info.LargestStdFunc >= 0x7)
{
__asm__ volatile
(
"movq $0x7, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (iArg->Features->ExtFeature.EAX),
"=r" (iArg->Features->ExtFeature.EBX),
"=r" (iArg->Features->ExtFeature.ECX),
"=r" (iArg->Features->ExtFeature.EDX)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
if (iArg->Features->ExtFeature.EAX.MaxSubLeaf >= 1)
{
__asm__ volatile
(
"movq $0x7, %%rax \n\t"
"movq $0x1, %%rcx \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (iArg->Features->ExtFeature_Leaf1.EAX),
"=r" (iArg->Features->ExtFeature_Leaf1.EBX),
"=r" (iArg->Features->ExtFeature_Leaf1.ECX),
"=r" (iArg->Features->ExtFeature_Leaf1.EDX)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
}
}
/* Must have 0x80000000,0x80000001,0x80000002,0x80000003,0x80000004 */
__asm__ volatile
(
"movq $0x80000000, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (iArg->Features->Info.LargestExtFunc),
"=r" (ebx),
"=r" (ecx),
"=r" (edx)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
__asm__ volatile
(
"movq $0x80000001, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (eax),
"=r" (ebx),
"=r" (iArg->Features->ExtInfo.ECX),
"=r" (iArg->Features->ExtInfo.EDX)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
if (iArg->Features->Info.LargestExtFunc >= 0x80000007)
{
__asm__ volatile
(
"movq $0x80000007, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (iArg->Features->AdvPower.EAX),
"=r" (iArg->Features->AdvPower.EBX),
"=r" (iArg->Features->AdvPower.ECX),
"=r" (iArg->Features->AdvPower.EDX)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
}
if (iArg->Features->Info.LargestExtFunc >= 0x80000008)
{
__asm__ volatile
(
"movq $0x80000008, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (iArg->Features->leaf80000008.EAX),
"=r" (iArg->Features->leaf80000008.EBX),
"=r" (iArg->Features->leaf80000008.ECX),
"=r" (iArg->Features->leaf80000008.EDX)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
}
/* Reset the performance features bits (present is zero) */
iArg->Features->PerfMon.EBX.CoreCycles = 1;
iArg->Features->PerfMon.EBX.InstrRetired = 1;
iArg->Features->PerfMon.EBX.RefCycles = 1;
iArg->Features->PerfMon.EBX.LLC_Ref = 1;
iArg->Features->PerfMon.EBX.LLC_Misses = 1;
iArg->Features->PerfMon.EBX.BranchRetired = 1;
iArg->Features->PerfMon.EBX.BranchMispred = 1;
iArg->Features->PerfMon.EBX.TopdownSlots = 1;
/* Per Vendor features */
if (iArg->Features->Info.Vendor.CRC == CRC_INTEL)
{
__asm__ volatile
(
"movq $0x4, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"
"xorq %%rcx, %%rcx \n\t"
"xorq %%rdx, %%rdx \n\t"
"cpuid \n\t"
"mov %%eax, %0 \n\t"
"mov %%ebx, %1 \n\t"
"mov %%ecx, %2 \n\t"
"mov %%edx, %3"
: "=r" (eax),
"=r" (ebx),
"=r" (ecx),
"=r" (edx)
:
: "%rax", "%rbx", "%rcx", "%rdx"
);
iArg->SMT_Count = (eax >> 26) & 0x3f;
iArg->SMT_Count++;
if (iArg->Features->Info.LargestStdFunc >= 0xa)
{
__asm__ volatile
(
"movq $0xa, %%rax \n\t"
"xorq %%rbx, %%rbx \n\t"