From 04e170e86b17d563b02d89963f4352f30ed562fc Mon Sep 17 00:00:00 2001
From: Amelia Dobis <ad4048@princeton.edu>
Date: Wed, 1 May 2024 13:56:08 -0700
Subject: [PATCH] [LTL] Added overloadings for AssertProperty (#4037)

(cherry picked from commit 5cf2b4020ab77302d5a7541d4a277c21bdc2fddb)
---
 src/main/scala/chisel3/ltl/LTL.scala | 57 ++++++++++++++++++++++++++--
 1 file changed, 53 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/chisel3/ltl/LTL.scala b/src/main/scala/chisel3/ltl/LTL.scala
index 595afbe3239..3c4922c77a9 100644
--- a/src/main/scala/chisel3/ltl/LTL.scala
+++ b/src/main/scala/chisel3/ltl/LTL.scala
@@ -340,14 +340,14 @@ sealed abstract class AssertPropertyLike {
 
   /** Assert, assume, or cover that a property holds.
     *
-    * - The `prop` parameter can be a `Property`, `Sequence`, or simple `Bool`.
-    * - The optional `clock` specifies a clock with respect to which all cycle
+    * @param prop: parameter can be a `Property`, `Sequence`, or simple `Bool`.
+    * @param clock [optional]: specifies a clock with respect to which all cycle
     *   delays in the property are expressed. This is a shorthand for
     *   `prop.clock(clock)`.
-    * - The optional `disable` specifies a condition under which the evaluation
+    * @param disable [optional]: specifies a condition under which the evaluation
     *   of the property is disabled. This is a shorthand for
     *   `prop.disable(disable)`.
-    * - The optional `label` is used to assign a name to the assert, assume, or
+    * @param label [optional]: is used to assign a name to the assert, assume, or
     *   cover construct in the output language. In SystemVerilog, this is
     *   emitted as `label: assert(...)`.
     */
@@ -363,6 +363,55 @@ sealed abstract class AssertPropertyLike {
     verif.property := clocked.inner
   }
 
+  /** Assert, assume, or cover that a boolean predicate holds.
+    * @param cond: a boolean predicate that should be checked.
+    * This will generate a boolean property that is clocked using the implicit clock
+    * and disabled in the case where the design has not yet been reset.
+    */
+  def apply(
+    cond: Bool
+  ): Unit = {
+    apply(Sequence.BoolSequence(cond))
+  }
+
+  /** Assert, assume, or cover that a boolean predicate holds.
+    * @param cond: a boolean predicate that should be checked.
+    * @param label: is used to assign a name to the assert, assume, or
+    *   cover construct in the output language. In SystemVerilog, this is
+    *   emitted as `label: assert(...)`.
+    * This will generate a boolean property that is clocked using the implicit clock
+    * and disabled in the case where the design has not yet been reset.
+    */
+  def apply(
+    cond:  Bool,
+    label: String
+  ): Unit = {
+    apply(Sequence.BoolSequence(cond), label = Some(label))
+  }
+
+  /** Assert, assume, or cover that a boolean predicate holds.
+    * @param cond: a boolean predicate that should be checked.
+    * @param clock: specifies a clock with respect to which all cycle
+    *   delays in the property are expressed. This is a shorthand for
+    *   `prop.clock(clock)`.
+    * @param disable: specifies a condition under which the evaluation
+    *   of the property is disabled. This is a shorthand for
+    *   `prop.disable(disable)`.
+    * @param label: is used to assign a name to the assert, assume, or
+    *   cover construct in the output language. In SystemVerilog, this is
+    *   emitted as `label: assert(...)`.
+    * This will generate a boolean property that is clocked using the implicit clock
+    * and disabled in the case where the design has not yet been reset.
+    */
+  def apply(
+    cond:    Bool,
+    clock:   Clock,
+    disable: Disable,
+    label:   String
+  ): Unit = {
+    apply(Sequence.BoolSequence(cond), Some(clock), Some(disable), Some(label))
+  }
+
   def createIntrinsic(label: Option[String]): Instance[VerifAssertLikeIntrinsic]
 }