From b4fc251ba15840b31665257a7430f2ea2284c929 Mon Sep 17 00:00:00 2001 From: Raffaele Meloni Date: Tue, 26 Mar 2024 19:16:22 +0100 Subject: [PATCH 1/2] Make Workspace parametric: allow to run a simulation in Chiselsim with different firtool options i.e. -g (#3932) --- .../scala/chisel3/simulator/Simulator.scala | 3 +- .../scala/chisel3/simulator/package.scala | 6 ++- .../chiselTests/simulator/SimulatorSpec.scala | 47 +++++++++++++++++++ 3 files changed, 53 insertions(+), 3 deletions(-) diff --git a/src/main/scala/chisel3/simulator/Simulator.scala b/src/main/scala/chisel3/simulator/Simulator.scala index 62689f061b5..14539fe3b5a 100644 --- a/src/main/scala/chisel3/simulator/Simulator.scala +++ b/src/main/scala/chisel3/simulator/Simulator.scala @@ -92,6 +92,7 @@ trait Simulator { def workingDirectoryPrefix = "workdir" def customSimulationWorkingDirectory: Option[String] = None def verbose: Boolean = false + def firtoolArgs: Seq[String] = Seq() private[simulator] def processBackends(processor: Simulator.BackendProcessor): Unit private[simulator] def _simulate[T <: RawModule, U]( @@ -100,7 +101,7 @@ trait Simulator { ): Seq[Simulator.BackendInvocationDigest[U]] = { val workspace = new Workspace(path = workspacePath, workingDirectoryPrefix = workingDirectoryPrefix) workspace.reset() - val elaboratedModule = workspace.elaborateGeneratedModule({ () => module }) + val elaboratedModule = workspace.elaborateGeneratedModule({ () => module }, firtoolArgs) workspace.generateAdditionalSources() val compiler = new Simulator.WorkspaceCompiler( elaboratedModule, diff --git a/src/main/scala/chisel3/simulator/package.scala b/src/main/scala/chisel3/simulator/package.scala index 354a5b56573..877523882e3 100644 --- a/src/main/scala/chisel3/simulator/package.scala +++ b/src/main/scala/chisel3/simulator/package.scala @@ -92,10 +92,12 @@ package object simulator { implicit class ChiselWorkspace(workspace: Workspace) { def elaborateGeneratedModule[T <: RawModule]( - generateModule: () => T + generateModule: () => T, + firtoolArgs: Seq[String] = Seq() ): ElaboratedModule[T] = { // Use CIRCT to generate SystemVerilog sources, and potentially additional artifacts var someDut: Option[T] = None + val firtoolOptions = firtoolArgs.map(circt.stage.FirtoolOption) val outputAnnotations = (new circt.stage.ChiselStage).execute( Array("--target", "systemverilog", "--split-verilog"), Seq( @@ -106,7 +108,7 @@ package object simulator { }, circt.stage.FirtoolOption("-disable-annotation-unknown"), firrtl.options.TargetDirAnnotation(workspace.supportArtifactsPath) - ) + ) ++ firtoolOptions ) // Move the files indicated by a filelist. No-op if the file has already diff --git a/src/test/scala/chiselTests/simulator/SimulatorSpec.scala b/src/test/scala/chiselTests/simulator/SimulatorSpec.scala index aa4025cee04..6d562ae9e47 100644 --- a/src/test/scala/chiselTests/simulator/SimulatorSpec.scala +++ b/src/test/scala/chiselTests/simulator/SimulatorSpec.scala @@ -111,5 +111,52 @@ class SimulatorSpec extends AnyFunSpec with Matchers { } .result } + + it("runs a design with debug mode (-g) and --strip-debug-info") { + import circt.stage.ChiselStage + + class Bar extends Module { + val a = IO(Input(Bool())) + val b = IO(Input(Bool())) + val out = IO(Output(Bool())) + + out := a & b + } + + // Check now the debug info is stripped + val expectedSV = ChiselStage.emitSystemVerilog(new Bar, firtoolOpts = Array("--strip-debug-info", "-g")) + + new VerilatorSimulator("test_run_dir/simulator/bar_debug_mode") { + override val firtoolArgs = Seq("--strip-debug-info", "-g") + } + .simulate(new Bar) { module => + import PeekPokeAPI._ + val bar = module.wrapped + + bar.a.poke(false.B) + bar.b.poke(false.B) + bar.out.expect(false.B) + bar.clock.step() + + bar.a.poke(true.B) + bar.b.poke(false.B) + bar.out.expect(false.B) + bar.clock.step() + + bar.a.poke(true.B) + bar.b.poke(true.B) + bar.out.expect(true.B) + bar.clock.step() + } + .result + + // Check the expected SV and the generated SV are the same + val source = io.Source.fromFile("test_run_dir/simulator/bar_debug_mode/primary-sources/Bar.sv") + val actualSV = source.mkString + assert(actualSV === expectedSV) + source.close() + + } + } } From 199b6ec1d0a179d3928937f3886f96f9e0f24d11 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 27 Mar 2024 15:15:54 -0700 Subject: [PATCH 2/2] Run scalafmt --- src/main/scala/chisel3/simulator/package.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/chisel3/simulator/package.scala b/src/main/scala/chisel3/simulator/package.scala index 877523882e3..30787ab144d 100644 --- a/src/main/scala/chisel3/simulator/package.scala +++ b/src/main/scala/chisel3/simulator/package.scala @@ -92,8 +92,8 @@ package object simulator { implicit class ChiselWorkspace(workspace: Workspace) { def elaborateGeneratedModule[T <: RawModule]( - generateModule: () => T, - firtoolArgs: Seq[String] = Seq() + generateModule: () => T, + firtoolArgs: Seq[String] = Seq() ): ElaboratedModule[T] = { // Use CIRCT to generate SystemVerilog sources, and potentially additional artifacts var someDut: Option[T] = None