From a47e1d3745cf1d8c36994308bd0b36726a46f17a Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Thu, 26 Jan 2023 14:58:20 -0600 Subject: [PATCH 01/20] checkpoint --- src/main/scala/chisel3/util/circt/IsX.scala | 51 +++++++++++++++++++ .../chisel3/util/circt/PlusArgsTest.scala | 50 ++++++++++++++++++ .../chisel3/util/circt/PlusArgsValue.scala | 50 ++++++++++++++++++ .../scala/chisel3/util/circt/SizeOf.scala | 10 ++-- 4 files changed, 155 insertions(+), 6 deletions(-) create mode 100644 src/main/scala/chisel3/util/circt/IsX.scala create mode 100644 src/main/scala/chisel3/util/circt/PlusArgsTest.scala create mode 100644 src/main/scala/chisel3/util/circt/PlusArgsValue.scala diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala new file mode 100644 index 00000000000..caeb90d4f49 --- /dev/null +++ b/src/main/scala/chisel3/util/circt/IsX.scala @@ -0,0 +1,51 @@ +package chisel3.util.circt + +// SPDX-License-Identifier: Apache-2.0 + +package chisel3.util.circt + +import chisel3._ +import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} + +import circt.Intrinsic + +// We have to unique designedName per type, be we can't due to name conflicts +// on bundles. Thus we use a globally unique id. +private object IsXGlobalIDGen { + private var id: Int = 0 + def getID() = { + this.synchronized { + val oldID = id + id = id + 1 + oldID + } + } +} + +/** Create a module with a parameterized type which returns whether the input + * is a verilog 'x'. + */ +private class IsXIntrinsic[T <: Data](gen: T) extends ExtModule { + val i = IO(Input(gen)) + val found = IO(Output(UInt(1.W))) + annotate(new ChiselAnnotation { + override def toFirrtl = + Intrinsic(toTarget, "circt.isX") + }) + override val desiredName = "IsX_" + SizeOfGlobalIDGen.getID() +} + +object IsX { + + /** Creates an intrinsic which returns whether the input is a verilog 'x'. + * + * @example {{{ + * b := isX(a) + * }}} + */ + def apply[T <: Data](gen: T): Data = { + val inst = Module(new IsXIntrinsic(chiselTypeOf(gen))) + inst.i := gen + inst.found + } +} diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala new file mode 100644 index 00000000000..0b00cbcc297 --- /dev/null +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -0,0 +1,50 @@ +package chisel3.util.circt + +// SPDX-License-Identifier: Apache-2.0 + +package chisel3.util.circt + +import chisel3._ +import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} + +import circt.Intrinsic + +// We have to unique designedName per type, be we can't due to name conflicts +// on bundles. Thus we use a globally unique id. +private object PlusArgsTestGlobalIDGen { + private var id: Int = 0 + def getID() = { + this.synchronized { + val oldID = id + id = id + 1 + oldID + } + } +} + +/** Create a module with a parameterized type which returns whether the input + * is a verilog 'x'. + */ +private class PlusArgsTestIntrinsic[T <: Data](gen: T) extends ExtModule { + val found = IO(Output(UInt(1.W))) + annotate(new ChiselAnnotation { + override def toFirrtl = + Intrinsic(toTarget, "circt.plusargs.test") + }) + override val desiredName = "PlusArgsTest_" + PlusArgsValueGlobalIDGen.getID() +} + +object PlusArgsTest { + + /** Creates an intrinsic which returns whether the input is a verilog 'x'. + * + * @example {{{ + * b := isX(a) + * }}} + */ + def apply[T <: Data](gen: T): Data = { + val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen))) + inst.i := gen + inst.size + } +} diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala new file mode 100644 index 00000000000..cbb9c1f17e1 --- /dev/null +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -0,0 +1,50 @@ +package chisel3.util.circt + +// SPDX-License-Identifier: Apache-2.0 + +package chisel3.util.circt + +import chisel3._ +import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} + +import circt.Intrinsic + +// We have to unique designedName per type, be we can't due to name conflicts +// on bundles. Thus we use a globally unique id. +private object PlusArgsValueGlobalIDGen { + private var id: Int = 0 + def getID() = { + this.synchronized { + val oldID = id + id = id + 1 + oldID + } + } +} + +/** Create a module which generates a verilog $plusargs$value. This returns a + * single value as indicated by the format string. + */ +private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends ExtModule { + val found= IO(Output(UInt<1>)) + val result = IO(Output(gen)) + annotate(new ChiselAnnotation { + override def toFirrtl = + Intrinsic(toTarget, "circt.plusargs.value") + }) + override val desiredName = "PlusArgsValue_" + PlusArgsValueGlobalIDGen.getID() +} + +object PlusArgsValue { + + /** Creates an intrinsic which returns whether the input is a verilog 'x'. + * + * @example {{{ + * b := isX(a) + * }}} + */ + def apply[T <: Data](gen: T, str: String): Data = { + val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen), str)) + inst.found, inst.result + } +} \ No newline at end of file diff --git a/src/main/scala/chisel3/util/circt/SizeOf.scala b/src/main/scala/chisel3/util/circt/SizeOf.scala index bc7807058e0..c9ab319c4a1 100644 --- a/src/main/scala/chisel3/util/circt/SizeOf.scala +++ b/src/main/scala/chisel3/util/circt/SizeOf.scala @@ -2,8 +2,6 @@ package chisel3.util.circt -import scala.util.hashing.MurmurHash3 - import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} @@ -27,7 +25,7 @@ private object SizeOfGlobalIDGen { * results of type inference. */ private class SizeOfIntrinsic[T <: Data](gen: T) extends ExtModule { - val i = IO(Input(gen)); + val i = IO(Input(gen)) val size = IO(Output(UInt(32.W))) annotate(new ChiselAnnotation { override def toFirrtl = @@ -48,8 +46,8 @@ object SizeOf { * }}} */ def apply[T <: Data](gen: T): Data = { - val sizeOfInst = Module(new SizeOfIntrinsic(chiselTypeOf(gen))) - sizeOfInst.i := gen - sizeOfInst.size + val inst = Module(new SizeOfIntrinsic(chiselTypeOf(gen))) + inst.i := gen + inst.size } } From 89ceba0d048ec2e47042087985b736f587ed9279 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Fri, 27 Jan 2023 09:55:30 -0600 Subject: [PATCH 02/20] checkpoint --- src/main/scala/chisel3/util/circt/IsX.scala | 2 - .../chisel3/util/circt/PlusArgsTest.scala | 11 ++-- .../chisel3/util/circt/PlusArgsValue.scala | 12 ++-- src/test/scala/chiselTests/util/IsXSpec.scala | 58 +++++++++++++++++++ .../scala/chiselTests/util/SizeOfSpec.scala | 4 +- 5 files changed, 70 insertions(+), 17 deletions(-) create mode 100644 src/test/scala/chiselTests/util/IsXSpec.scala diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala index caeb90d4f49..eba834c16fc 100644 --- a/src/main/scala/chisel3/util/circt/IsX.scala +++ b/src/main/scala/chisel3/util/circt/IsX.scala @@ -1,5 +1,3 @@ -package chisel3.util.circt - // SPDX-License-Identifier: Apache-2.0 package chisel3.util.circt diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 0b00cbcc297..029e1ca6966 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -1,5 +1,3 @@ -package chisel3.util.circt - // SPDX-License-Identifier: Apache-2.0 package chisel3.util.circt @@ -25,7 +23,7 @@ private object PlusArgsTestGlobalIDGen { /** Create a module with a parameterized type which returns whether the input * is a verilog 'x'. */ -private class PlusArgsTestIntrinsic[T <: Data](gen: T) extends ExtModule { +private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) extends ExtModule(Map("FORMAT" -> str)) { val found = IO(Output(UInt(1.W))) annotate(new ChiselAnnotation { override def toFirrtl = @@ -42,9 +40,8 @@ object PlusArgsTest { * b := isX(a) * }}} */ - def apply[T <: Data](gen: T): Data = { - val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen))) - inst.i := gen - inst.size + def apply[T <: Data](gen: T, str: String): Data = { + val inst = Module(new PlusArgsTestIntrinsic(chiselTypeOf(gen), str)) + inst.found } } diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index cbb9c1f17e1..2dbb6d16ce4 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -1,5 +1,3 @@ -package chisel3.util.circt - // SPDX-License-Identifier: Apache-2.0 package chisel3.util.circt @@ -25,9 +23,11 @@ private object PlusArgsValueGlobalIDGen { /** Create a module which generates a verilog $plusargs$value. This returns a * single value as indicated by the format string. */ -private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends ExtModule { - val found= IO(Output(UInt<1>)) - val result = IO(Output(gen)) +private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends ExtModule(Map("FORMAT" -> str)) { + val io = IO(new Bundle { + val found= Output(UInt(1.W)) + val result = Output(gen) + }) annotate(new ChiselAnnotation { override def toFirrtl = Intrinsic(toTarget, "circt.plusargs.value") @@ -45,6 +45,6 @@ object PlusArgsValue { */ def apply[T <: Data](gen: T, str: String): Data = { val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen), str)) - inst.found, inst.result + inst.io } } \ No newline at end of file diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala new file mode 100644 index 00000000000..ae17b79a946 --- /dev/null +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -0,0 +1,58 @@ +package chiselTests.util + +package chiselTests.util + +import chisel3._ +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import chisel3.testers.BasicTester +import chisel3.util.circt.IsX + +import org.scalatest.flatspec.AnyFlatSpec +import org.scalatest.matchers.should.Matchers + +import scala.io.Source + +private class MyBundle extends Bundle { + val a = UInt() + val b = SInt() +} + +private class IsXTop extends Module { + val io = IO(new Bundle { + val w = Input(UInt(65.W)) + val x = Input(new MyBundle) + val outw = UInt(1.W) + val outx = UInt(1.W) + }) + io.outw := IsX(io.w) + io.outx := IsX(io.x) +} + +/** A test for intrinsics. Since chisel is producing intrinsics as tagged + * extmodules (for now), we explicitly test the chirrtl and annotations rather + * than the processed firrtl or verilog. It is worth noting that annotations + * are implemented (for now) in a way which makes the output valid for all + * firrtl compilers, hence we write a localized, not end-to-end test + */ +class IsXSpec extends AnyFlatSpec with Matchers { + it should "Should work for types" in { + val fir = ChiselStage.emitChirrtl(new SizeOfTop) + val a1 = """extmodule SizeOf_0""".r + (fir should include).regex(a1) + val b1 = """defname = SizeOf_0""".r + (fir should include).regex(b1) + val a2 = """extmodule SizeOf_1""".r + (fir should include).regex(a2) + val b2 = """defname = SizeOf_1""".r + (fir should include).regex(b2) + + // The second elaboration uses a unique name since the Builder is reused (?) + val c = """Intrinsic\(~SizeOfTop\|SizeOf.*,circt.sizeof\)""" + ((new chisel3.stage.ChiselStage) + .execute( + args = Array("--no-run-firrtl"), + annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new SizeOfTop)) + ) + .mkString("\n") should include).regex(c) + } +} diff --git a/src/test/scala/chiselTests/util/SizeOfSpec.scala b/src/test/scala/chiselTests/util/SizeOfSpec.scala index 6a6ef8d00e6..3ca77702106 100644 --- a/src/test/scala/chiselTests/util/SizeOfSpec.scala +++ b/src/test/scala/chiselTests/util/SizeOfSpec.scala @@ -10,12 +10,12 @@ import org.scalatest.matchers.should.Matchers import scala.io.Source -class MyBundle extends Bundle { +private class MyBundle extends Bundle { val a = UInt() val b = SInt() } -class SizeOfTop extends Module { +private class SizeOfTop extends Module { val io = IO(new Bundle { val w = Input(UInt(65.W)) val x = Input(new MyBundle) From 6dbd0f14adf92f322e08c0ea8c4389892da13c48 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Fri, 27 Jan 2023 10:05:05 -0600 Subject: [PATCH 03/20] checkpoint --- src/test/scala/chiselTests/util/CatSpec.scala | 2 +- src/test/scala/chiselTests/util/PipeSpec.scala | 2 +- src/test/scala/chiselTests/util/PriorityMuxSpec.scala | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala index 9d0fcbb04a0..327bcea020a 100644 --- a/src/test/scala/chiselTests/util/CatSpec.scala +++ b/src/test/scala/chiselTests/util/CatSpec.scala @@ -5,7 +5,7 @@ package chiselTests.util import chisel3._ import chisel3.experimental.noPrefix import chisel3.util.Cat -import chiselTests.ChiselFlatSpec +import _root_.chiselTests.ChiselFlatSpec import circt.stage.ChiselStage object CatSpec { diff --git a/src/test/scala/chiselTests/util/PipeSpec.scala b/src/test/scala/chiselTests/util/PipeSpec.scala index 5343b757e3f..39955c2955a 100644 --- a/src/test/scala/chiselTests/util/PipeSpec.scala +++ b/src/test/scala/chiselTests/util/PipeSpec.scala @@ -4,7 +4,7 @@ package chiselTests.util import chisel3._ import chisel3.util.{Pipe, Valid} -import chiselTests.ChiselFlatSpec +import _root_.chiselTests.ChiselFlatSpec import circt.stage.ChiselStage.emitCHIRRTL class PipeSpec extends ChiselFlatSpec { diff --git a/src/test/scala/chiselTests/util/PriorityMuxSpec.scala b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala index 814ac9b0410..27cb3ff88e7 100644 --- a/src/test/scala/chiselTests/util/PriorityMuxSpec.scala +++ b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala @@ -5,7 +5,7 @@ package chiselTests.util import chisel3._ import chisel3.testers.BasicTester import chisel3.util.{Counter, PriorityMux} -import chiselTests.ChiselFlatSpec +import _root_.chiselTests.ChiselFlatSpec import circt.stage.ChiselStage.emitCHIRRTL class PriorityMuxTester extends BasicTester { From f58938283a96de164acb4092a11a1db97f74e918 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Fri, 27 Jan 2023 11:22:34 -0600 Subject: [PATCH 04/20] sync --- src/main/scala/chisel3/util/circt/IsX.scala | 2 +- .../chisel3/util/circt/PlusArgsTest.scala | 5 ++ .../chisel3/util/circt/PlusArgsValue.scala | 21 +++++--- src/test/scala/chiselTests/util/CatSpec.scala | 2 +- src/test/scala/chiselTests/util/IsXSpec.scala | 20 ++++--- .../scala/chiselTests/util/PipeSpec.scala | 2 +- .../chiselTests/util/PlusArgsTestSpec.scala | 50 +++++++++++++++++ .../chiselTests/util/PlusArgsValueSpec.scala | 53 +++++++++++++++++++ .../chiselTests/util/PriorityMuxSpec.scala | 2 +- .../scala/chiselTests/util/SizeOfSpec.scala | 4 +- 10 files changed, 137 insertions(+), 24 deletions(-) create mode 100644 src/test/scala/chiselTests/util/PlusArgsTestSpec.scala create mode 100644 src/test/scala/chiselTests/util/PlusArgsValueSpec.scala diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala index eba834c16fc..c95cd66e19b 100644 --- a/src/main/scala/chisel3/util/circt/IsX.scala +++ b/src/main/scala/chisel3/util/circt/IsX.scala @@ -30,7 +30,7 @@ private class IsXIntrinsic[T <: Data](gen: T) extends ExtModule { override def toFirrtl = Intrinsic(toTarget, "circt.isX") }) - override val desiredName = "IsX_" + SizeOfGlobalIDGen.getID() + override val desiredName = "IsX_" + IsXGlobalIDGen.getID() } object IsX { diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 029e1ca6966..938b490ae82 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -41,7 +41,12 @@ object PlusArgsTest { * }}} */ def apply[T <: Data](gen: T, str: String): Data = { + if (gen.isSynthesizable) { val inst = Module(new PlusArgsTestIntrinsic(chiselTypeOf(gen), str)) inst.found + } else { + val inst = Module(new PlusArgsTestIntrinsic(gen, str)) + inst.found + } } } diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index 2dbb6d16ce4..9f3ff58498b 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -3,7 +3,7 @@ package chisel3.util.circt import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} +import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule, FlatIO} import circt.Intrinsic @@ -24,10 +24,11 @@ private object PlusArgsValueGlobalIDGen { * single value as indicated by the format string. */ private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends ExtModule(Map("FORMAT" -> str)) { - val io = IO(new Bundle { - val found= Output(UInt(1.W)) + val io = FlatIO(new Bundle { + val found= Output(UInt(1.W)) val result = Output(gen) - }) + } + ) annotate(new ChiselAnnotation { override def toFirrtl = Intrinsic(toTarget, "circt.plusargs.value") @@ -43,8 +44,14 @@ object PlusArgsValue { * b := isX(a) * }}} */ - def apply[T <: Data](gen: T, str: String): Data = { - val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen), str)) - inst.io + def apply[T <: Data](gen: T, str: String) = { + if (gen.isSynthesizable) { + val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen), str)) + inst.io + } else { + val inst = Module(new PlusArgsValueIntrinsic(gen, str)) + inst.io + } } + } \ No newline at end of file diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala index 327bcea020a..9d0fcbb04a0 100644 --- a/src/test/scala/chiselTests/util/CatSpec.scala +++ b/src/test/scala/chiselTests/util/CatSpec.scala @@ -5,7 +5,7 @@ package chiselTests.util import chisel3._ import chisel3.experimental.noPrefix import chisel3.util.Cat -import _root_.chiselTests.ChiselFlatSpec +import chiselTests.ChiselFlatSpec import circt.stage.ChiselStage object CatSpec { diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index ae17b79a946..c1ff6f22bd5 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -1,7 +1,5 @@ package chiselTests.util -package chiselTests.util - import chisel3._ import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} import chisel3.testers.BasicTester @@ -12,7 +10,7 @@ import org.scalatest.matchers.should.Matchers import scala.io.Source -private class MyBundle extends Bundle { +private class IsXBundle extends Bundle { val a = UInt() val b = SInt() } @@ -20,7 +18,7 @@ private class MyBundle extends Bundle { private class IsXTop extends Module { val io = IO(new Bundle { val w = Input(UInt(65.W)) - val x = Input(new MyBundle) + val x = Input(new IsXBundle) val outw = UInt(1.W) val outx = UInt(1.W) }) @@ -36,22 +34,22 @@ private class IsXTop extends Module { */ class IsXSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { - val fir = ChiselStage.emitChirrtl(new SizeOfTop) - val a1 = """extmodule SizeOf_0""".r + val fir = ChiselStage.emitChirrtl(new IsXTop) + val a1 = """extmodule IsX_0""".r (fir should include).regex(a1) - val b1 = """defname = SizeOf_0""".r + val b1 = """defname = IsX_0""".r (fir should include).regex(b1) - val a2 = """extmodule SizeOf_1""".r + val a2 = """extmodule IsX_1""".r (fir should include).regex(a2) - val b2 = """defname = SizeOf_1""".r + val b2 = """defname = IsX_1""".r (fir should include).regex(b2) // The second elaboration uses a unique name since the Builder is reused (?) - val c = """Intrinsic\(~SizeOfTop\|SizeOf.*,circt.sizeof\)""" + val c = """Intrinsic\(~IsXTop\|IsX.*,circt.isX\)""" ((new chisel3.stage.ChiselStage) .execute( args = Array("--no-run-firrtl"), - annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new SizeOfTop)) + annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new IsXTop)) ) .mkString("\n") should include).regex(c) } diff --git a/src/test/scala/chiselTests/util/PipeSpec.scala b/src/test/scala/chiselTests/util/PipeSpec.scala index 39955c2955a..5343b757e3f 100644 --- a/src/test/scala/chiselTests/util/PipeSpec.scala +++ b/src/test/scala/chiselTests/util/PipeSpec.scala @@ -4,7 +4,7 @@ package chiselTests.util import chisel3._ import chisel3.util.{Pipe, Valid} -import _root_.chiselTests.ChiselFlatSpec +import chiselTests.ChiselFlatSpec import circt.stage.ChiselStage.emitCHIRRTL class PipeSpec extends ChiselFlatSpec { diff --git a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala new file mode 100644 index 00000000000..2a259fd2223 --- /dev/null +++ b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala @@ -0,0 +1,50 @@ +package chiselTests.util + +import chisel3._ +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import chisel3.testers.BasicTester +import chisel3.util.circt.PlusArgsTest + +import org.scalatest.flatspec.AnyFlatSpec +import org.scalatest.matchers.should.Matchers + +import scala.io.Source + +private class PlusArgsTestTop extends Module { + val io = IO(new Bundle { + val w = Output(UInt(1.W)) + val x = Output(UInt(1.W)) + val z = Input(UInt(32.W)) + }) + io.w := PlusArgsTest(UInt(32.W), "FOO") + io.x := PlusArgsTest(io.z, "BAR") +} + +/** A test for intrinsics. Since chisel is producing intrinsics as tagged + * extmodules (for now), we explicitly test the chirrtl and annotations rather + * than the processed firrtl or verilog. It is worth noting that annotations + * are implemented (for now) in a way which makes the output valid for all + * firrtl compilers, hence we write a localized, not end-to-end test + */ +class PlusArgsTestSpec extends AnyFlatSpec with Matchers { + it should "Should work for types" in { + val fir = ChiselStage.emitChirrtl(new PlusArgsTestTop) + val a1 = """extmodule PlusArgsTest_0""".r + (fir should include).regex(a1) + val b1 = """defname = PlusArgsTest_0""".r + (fir should include).regex(b1) + val a2 = """extmodule PlusArgsTest_1""".r + (fir should include).regex(a2) + val b2 = """defname = PlusArgsTest_1""".r + (fir should include).regex(b2) + + // The second elaboration uses a unique name since the Builder is reused (?) + val c = """Intrinsic\(~PlusArgsTestTop\|PlusArgsTest.*,circt.plusargs.test\)""" + ((new chisel3.stage.ChiselStage) + .execute( + args = Array("--no-run-firrtl"), + annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new PlusArgsTestTop)) + ) + .mkString("\n") should include).regex(c) + } +} diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala new file mode 100644 index 00000000000..f3a79cb387e --- /dev/null +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -0,0 +1,53 @@ +package chiselTests.util + +import chisel3._ +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import chisel3.testers.BasicTester +import chisel3.util.circt.PlusArgsValue + +import org.scalatest.flatspec.AnyFlatSpec +import org.scalatest.matchers.should.Matchers + +import scala.io.Source + +private class PlusArgsValueTop extends Module { + val io = IO(new Bundle { + val wf = Output(UInt(1.W)) + val wv = Output(UInt(32.W)) + val xf = Output(UInt(1.W)) + val xv = Output(UInt(32.W)) + }) + val tmpw = PlusArgsValue(UInt(32.W), "FOO=%d") + val tmpx = PlusArgsValue(io.xv, "BAR=%d") + io.xf := tmpx.found + io.xv := tmpx.result +} + +/** A test for intrinsics. Since chisel is producing intrinsics as tagged + * extmodules (for now), we explicitly test the chirrtl and annotations rather + * than the processed firrtl or verilog. It is worth noting that annotations + * are implemented (for now) in a way which makes the output valid for all + * firrtl compilers, hence we write a localized, not end-to-end test + */ +class PlusArgsValueSpec extends AnyFlatSpec with Matchers { + it should "Should work for types" in { + val fir = ChiselStage.emitChirrtl(new PlusArgsValueTop) + val a1 = """extmodule PlusArgsValue_0""".r + (fir should include).regex(a1) + val b1 = """defname = PlusArgsValue_0""".r + (fir should include).regex(b1) + val a2 = """extmodule PlusArgsValue_1""".r + (fir should include).regex(a2) + val b2 = """defname = PlusArgsValue_1""".r + (fir should include).regex(b2) + + // The second elaboration uses a unique name since the Builder is reused (?) + val c = """Intrinsic\(~PlusArgsValueTop\|PlusArgsValue.*,circt.plusargs.value\)""" + ((new chisel3.stage.ChiselStage) + .execute( + args = Array("--no-run-firrtl"), + annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new PlusArgsValueTop)) + ) + .mkString("\n") should include).regex(c) + } +} diff --git a/src/test/scala/chiselTests/util/PriorityMuxSpec.scala b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala index 27cb3ff88e7..814ac9b0410 100644 --- a/src/test/scala/chiselTests/util/PriorityMuxSpec.scala +++ b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala @@ -5,7 +5,7 @@ package chiselTests.util import chisel3._ import chisel3.testers.BasicTester import chisel3.util.{Counter, PriorityMux} -import _root_.chiselTests.ChiselFlatSpec +import chiselTests.ChiselFlatSpec import circt.stage.ChiselStage.emitCHIRRTL class PriorityMuxTester extends BasicTester { diff --git a/src/test/scala/chiselTests/util/SizeOfSpec.scala b/src/test/scala/chiselTests/util/SizeOfSpec.scala index 3ca77702106..dc1c03bba82 100644 --- a/src/test/scala/chiselTests/util/SizeOfSpec.scala +++ b/src/test/scala/chiselTests/util/SizeOfSpec.scala @@ -10,7 +10,7 @@ import org.scalatest.matchers.should.Matchers import scala.io.Source -private class MyBundle extends Bundle { +private class SizeOfBundle extends Bundle { val a = UInt() val b = SInt() } @@ -18,7 +18,7 @@ private class MyBundle extends Bundle { private class SizeOfTop extends Module { val io = IO(new Bundle { val w = Input(UInt(65.W)) - val x = Input(new MyBundle) + val x = Input(new SizeOfBundle) val outw = UInt(32.W) val outx = UInt(32.W) }) From 0287aef04206891ec52c9a9b0b171c5944d2cd01 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Fri, 27 Jan 2023 11:26:57 -0600 Subject: [PATCH 05/20] checkpoint --- .../chisel3/util/circt/PlusArgsTest.scala | 17 +++++++------ .../chisel3/util/circt/PlusArgsValue.scala | 25 ++++++++++--------- 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 938b490ae82..45b7443ad51 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -20,8 +20,9 @@ private object PlusArgsTestGlobalIDGen { } } -/** Create a module with a parameterized type which returns whether the input - * is a verilog 'x'. +/** Create a module with a parameterized type which calls the verilog function + * $test$plusargs to test for the existance of the string str in the + * simulator command line. */ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) extends ExtModule(Map("FORMAT" -> str)) { val found = IO(Output(UInt(1.W))) @@ -34,19 +35,19 @@ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) extends ExtM object PlusArgsTest { - /** Creates an intrinsic which returns whether the input is a verilog 'x'. + /** Creates an intrinsic which calls $test$plusargs. * * @example {{{ - * b := isX(a) + * b := PlusArgsTest(UInt<32.W>, "FOO") * }}} */ def apply[T <: Data](gen: T, str: String): Data = { if (gen.isSynthesizable) { - val inst = Module(new PlusArgsTestIntrinsic(chiselTypeOf(gen), str)) - inst.found + val inst = Module(new PlusArgsTestIntrinsic(chiselTypeOf(gen), str)) + inst.found } else { - val inst = Module(new PlusArgsTestIntrinsic(gen, str)) - inst.found + val inst = Module(new PlusArgsTestIntrinsic(gen, str)) + inst.found } } } diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index 9f3ff58498b..f3572dac96c 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -21,14 +21,14 @@ private object PlusArgsValueGlobalIDGen { } /** Create a module which generates a verilog $plusargs$value. This returns a - * single value as indicated by the format string. + * value as indicated by the format string and a flag for whether the value + * was found. */ private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends ExtModule(Map("FORMAT" -> str)) { val io = FlatIO(new Bundle { - val found= Output(UInt(1.W)) + val found = Output(UInt(1.W)) val result = Output(gen) - } - ) + }) annotate(new ChiselAnnotation { override def toFirrtl = Intrinsic(toTarget, "circt.plusargs.value") @@ -38,20 +38,21 @@ private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends Ext object PlusArgsValue { - /** Creates an intrinsic which returns whether the input is a verilog 'x'. + /** Creates an intrinsic which calls $test$plusargs. * * @example {{{ - * b := isX(a) + * b := PlusArgsValue(UInt<32.W>, "FOO=%d") + * b.found + * b.value * }}} */ def apply[T <: Data](gen: T, str: String) = { if (gen.isSynthesizable) { - val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen), str)) - inst.io + val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen), str)) + inst.io } else { - val inst = Module(new PlusArgsValueIntrinsic(gen, str)) - inst.io + val inst = Module(new PlusArgsValueIntrinsic(gen, str)) + inst.io } } - -} \ No newline at end of file +} From 483e6e0839f9bca8868d14f72e4d9b7bd460732b Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Fri, 27 Jan 2023 12:05:56 -0600 Subject: [PATCH 06/20] id --- src/main/scala/chisel3/util/circt/PlusArgsTest.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 45b7443ad51..503522d8ead 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -30,7 +30,7 @@ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) extends ExtM override def toFirrtl = Intrinsic(toTarget, "circt.plusargs.test") }) - override val desiredName = "PlusArgsTest_" + PlusArgsValueGlobalIDGen.getID() + override val desiredName = "PlusArgsTest_" + PlusArgsTestGlobalIDGen.getID() } object PlusArgsTest { From 32b02d82fc2bc9936df8c7e600e0bad54f76d018 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Mon, 30 Jan 2023 13:01:29 -0600 Subject: [PATCH 07/20] license headers --- src/test/scala/chiselTests/util/IsXSpec.scala | 2 ++ src/test/scala/chiselTests/util/PlusArgsTestSpec.scala | 2 ++ src/test/scala/chiselTests/util/PlusArgsValueSpec.scala | 2 ++ src/test/scala/chiselTests/util/SizeOfSpec.scala | 2 ++ 4 files changed, 8 insertions(+) diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index c1ff6f22bd5..eb3af6bb4c3 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: Apache-2.0 + package chiselTests.util import chisel3._ diff --git a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala index 2a259fd2223..c85358b7649 100644 --- a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: Apache-2.0 + package chiselTests.util import chisel3._ diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index f3a79cb387e..0341b11a99f 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: Apache-2.0 + package chiselTests.util import chisel3._ diff --git a/src/test/scala/chiselTests/util/SizeOfSpec.scala b/src/test/scala/chiselTests/util/SizeOfSpec.scala index dc1c03bba82..9fb1b8c1e5a 100644 --- a/src/test/scala/chiselTests/util/SizeOfSpec.scala +++ b/src/test/scala/chiselTests/util/SizeOfSpec.scala @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: Apache-2.0 + package chiselTests.util import chisel3._ From ae668da2729f544d4b627b2d10b30e11787dc716 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Mon, 30 Jan 2023 14:18:41 -0600 Subject: [PATCH 08/20] Use existing id generator. make tests more specific. --- src/main/scala/chisel3/util/circt/IsX.scala | 16 ++-------------- .../scala/chisel3/util/circt/PlusArgsTest.scala | 16 ++-------------- .../scala/chisel3/util/circt/PlusArgsValue.scala | 16 ++-------------- src/main/scala/chisel3/util/circt/SizeOf.scala | 16 ++-------------- src/test/scala/chiselTests/util/IsXSpec.scala | 11 ++++------- .../chiselTests/util/PlusArgsTestSpec.scala | 8 +------- .../chiselTests/util/PlusArgsValueSpec.scala | 8 +------- src/test/scala/chiselTests/util/SizeOfSpec.scala | 8 +------- 8 files changed, 15 insertions(+), 84 deletions(-) diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala index c95cd66e19b..32dd565575d 100644 --- a/src/main/scala/chisel3/util/circt/IsX.scala +++ b/src/main/scala/chisel3/util/circt/IsX.scala @@ -4,22 +4,10 @@ package chisel3.util.circt import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} +import chisel3.internal.Builder import circt.Intrinsic -// We have to unique designedName per type, be we can't due to name conflicts -// on bundles. Thus we use a globally unique id. -private object IsXGlobalIDGen { - private var id: Int = 0 - def getID() = { - this.synchronized { - val oldID = id - id = id + 1 - oldID - } - } -} - /** Create a module with a parameterized type which returns whether the input * is a verilog 'x'. */ @@ -30,7 +18,7 @@ private class IsXIntrinsic[T <: Data](gen: T) extends ExtModule { override def toFirrtl = Intrinsic(toTarget, "circt.isX") }) - override val desiredName = "IsX_" + IsXGlobalIDGen.getID() + override val desiredName = "IsX_" + Builder.idGen.next } object IsX { diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 503522d8ead..b02c4f6c2b1 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -4,22 +4,10 @@ package chisel3.util.circt import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} +import chisel3.internal.Builder import circt.Intrinsic -// We have to unique designedName per type, be we can't due to name conflicts -// on bundles. Thus we use a globally unique id. -private object PlusArgsTestGlobalIDGen { - private var id: Int = 0 - def getID() = { - this.synchronized { - val oldID = id - id = id + 1 - oldID - } - } -} - /** Create a module with a parameterized type which calls the verilog function * $test$plusargs to test for the existance of the string str in the * simulator command line. @@ -30,7 +18,7 @@ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) extends ExtM override def toFirrtl = Intrinsic(toTarget, "circt.plusargs.test") }) - override val desiredName = "PlusArgsTest_" + PlusArgsTestGlobalIDGen.getID() + override val desiredName = "PlusArgsTest_" + Builder.idGen.next } object PlusArgsTest { diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index f3572dac96c..331f30b1fc9 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -4,22 +4,10 @@ package chisel3.util.circt import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule, FlatIO} +import chisel3.internal.Builder import circt.Intrinsic -// We have to unique designedName per type, be we can't due to name conflicts -// on bundles. Thus we use a globally unique id. -private object PlusArgsValueGlobalIDGen { - private var id: Int = 0 - def getID() = { - this.synchronized { - val oldID = id - id = id + 1 - oldID - } - } -} - /** Create a module which generates a verilog $plusargs$value. This returns a * value as indicated by the format string and a flag for whether the value * was found. @@ -33,7 +21,7 @@ private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends Ext override def toFirrtl = Intrinsic(toTarget, "circt.plusargs.value") }) - override val desiredName = "PlusArgsValue_" + PlusArgsValueGlobalIDGen.getID() + override val desiredName = "PlusArgsValue_" + Builder.idGen.next } object PlusArgsValue { diff --git a/src/main/scala/chisel3/util/circt/SizeOf.scala b/src/main/scala/chisel3/util/circt/SizeOf.scala index c9ab319c4a1..550288e3682 100644 --- a/src/main/scala/chisel3/util/circt/SizeOf.scala +++ b/src/main/scala/chisel3/util/circt/SizeOf.scala @@ -4,22 +4,10 @@ package chisel3.util.circt import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} +import chisel3.internal.Builder import circt.Intrinsic -// We have to unique designedName per type, be we can't due to name conflicts -// on bundles. Thus we use a globally unique id. -private object SizeOfGlobalIDGen { - private var id: Int = 0 - def getID() = { - this.synchronized { - val oldID = id - id = id + 1 - oldID - } - } -} - /** Create a module with a parameterized type which returns the size of the type * as a compile-time constant. This lets you write code which depends on the * results of type inference. @@ -31,7 +19,7 @@ private class SizeOfIntrinsic[T <: Data](gen: T) extends ExtModule { override def toFirrtl = Intrinsic(toTarget, "circt.sizeof") }) - override val desiredName = "SizeOf_" + SizeOfGlobalIDGen.getID() + override val desiredName = "SizeOf_" + Builder.idGen.next } object SizeOf { diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index eb3af6bb4c3..074c1292468 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -21,11 +21,14 @@ private class IsXTop extends Module { val io = IO(new Bundle { val w = Input(UInt(65.W)) val x = Input(new IsXBundle) + val y = Input(UInt(65.W)) val outw = UInt(1.W) val outx = UInt(1.W) + val outy = UInt(1.W) }) io.outw := IsX(io.w) io.outx := IsX(io.x) + io.outy := IsX(io.y) } /** A test for intrinsics. Since chisel is producing intrinsics as tagged @@ -37,14 +40,8 @@ private class IsXTop extends Module { class IsXSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitChirrtl(new IsXTop) - val a1 = """extmodule IsX_0""".r + val a1 = """(?s)extmodule IsX_(\d+).*defname = IsX_\1.*extmodule IsX_(\d+).*defname = IsX_\2.*extmodule IsX_(\d+).*defname = IsX_\3""".r (fir should include).regex(a1) - val b1 = """defname = IsX_0""".r - (fir should include).regex(b1) - val a2 = """extmodule IsX_1""".r - (fir should include).regex(a2) - val b2 = """defname = IsX_1""".r - (fir should include).regex(b2) // The second elaboration uses a unique name since the Builder is reused (?) val c = """Intrinsic\(~IsXTop\|IsX.*,circt.isX\)""" diff --git a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala index c85358b7649..17f4034f570 100644 --- a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala @@ -31,14 +31,8 @@ private class PlusArgsTestTop extends Module { class PlusArgsTestSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitChirrtl(new PlusArgsTestTop) - val a1 = """extmodule PlusArgsTest_0""".r + val a1 = """(?s)extmodule PlusArgsTest_(\d+).*defname = PlusArgsTest_\1.*extmodule PlusArgsTest_(\d+).*defname = PlusArgsTest_\2""".r (fir should include).regex(a1) - val b1 = """defname = PlusArgsTest_0""".r - (fir should include).regex(b1) - val a2 = """extmodule PlusArgsTest_1""".r - (fir should include).regex(a2) - val b2 = """defname = PlusArgsTest_1""".r - (fir should include).regex(b2) // The second elaboration uses a unique name since the Builder is reused (?) val c = """Intrinsic\(~PlusArgsTestTop\|PlusArgsTest.*,circt.plusargs.test\)""" diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index 0341b11a99f..890992091fb 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -34,14 +34,8 @@ private class PlusArgsValueTop extends Module { class PlusArgsValueSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitChirrtl(new PlusArgsValueTop) - val a1 = """extmodule PlusArgsValue_0""".r + val a1 = """(?s)extmodule PlusArgsValue_(\d+).*defname = PlusArgsValue_\1.*extmodule PlusArgsValue_(\d+).*defname = PlusArgsValue_\2""".r (fir should include).regex(a1) - val b1 = """defname = PlusArgsValue_0""".r - (fir should include).regex(b1) - val a2 = """extmodule PlusArgsValue_1""".r - (fir should include).regex(a2) - val b2 = """defname = PlusArgsValue_1""".r - (fir should include).regex(b2) // The second elaboration uses a unique name since the Builder is reused (?) val c = """Intrinsic\(~PlusArgsValueTop\|PlusArgsValue.*,circt.plusargs.value\)""" diff --git a/src/test/scala/chiselTests/util/SizeOfSpec.scala b/src/test/scala/chiselTests/util/SizeOfSpec.scala index 9fb1b8c1e5a..ceaa5578bdf 100644 --- a/src/test/scala/chiselTests/util/SizeOfSpec.scala +++ b/src/test/scala/chiselTests/util/SizeOfSpec.scala @@ -37,14 +37,8 @@ private class SizeOfTop extends Module { class SizeOfSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitChirrtl(new SizeOfTop) - val a1 = """extmodule SizeOf_0""".r + val a1 = """(?s)extmodule SizeOf_(\d+).*defname = SizeOf_\1.*extmodule SizeOf_(\d+).*defname = SizeOf_\2""".r (fir should include).regex(a1) - val b1 = """defname = SizeOf_0""".r - (fir should include).regex(b1) - val a2 = """extmodule SizeOf_1""".r - (fir should include).regex(a2) - val b2 = """defname = SizeOf_1""".r - (fir should include).regex(b2) // The second elaboration uses a unique name since the Builder is reused (?) val c = """Intrinsic\(~SizeOfTop\|SizeOf.*,circt.sizeof\)""" From bd84146a302980becb91e7fd21cebe4ecae3b405 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Mon, 30 Jan 2023 15:36:47 -0600 Subject: [PATCH 09/20] formatting --- src/test/scala/chiselTests/util/IsXSpec.scala | 3 ++- src/test/scala/chiselTests/util/PlusArgsTestSpec.scala | 3 ++- src/test/scala/chiselTests/util/PlusArgsValueSpec.scala | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index 074c1292468..b04c4168e7c 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -40,7 +40,8 @@ private class IsXTop extends Module { class IsXSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitChirrtl(new IsXTop) - val a1 = """(?s)extmodule IsX_(\d+).*defname = IsX_\1.*extmodule IsX_(\d+).*defname = IsX_\2.*extmodule IsX_(\d+).*defname = IsX_\3""".r + val a1 = + """(?s)extmodule IsX_(\d+).*defname = IsX_\1.*extmodule IsX_(\d+).*defname = IsX_\2.*extmodule IsX_(\d+).*defname = IsX_\3""".r (fir should include).regex(a1) // The second elaboration uses a unique name since the Builder is reused (?) diff --git a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala index 17f4034f570..246b63f95ed 100644 --- a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala @@ -31,7 +31,8 @@ private class PlusArgsTestTop extends Module { class PlusArgsTestSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitChirrtl(new PlusArgsTestTop) - val a1 = """(?s)extmodule PlusArgsTest_(\d+).*defname = PlusArgsTest_\1.*extmodule PlusArgsTest_(\d+).*defname = PlusArgsTest_\2""".r + val a1 = + """(?s)extmodule PlusArgsTest_(\d+).*defname = PlusArgsTest_\1.*extmodule PlusArgsTest_(\d+).*defname = PlusArgsTest_\2""".r (fir should include).regex(a1) // The second elaboration uses a unique name since the Builder is reused (?) diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index 890992091fb..ebe0e2494d3 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -34,7 +34,8 @@ private class PlusArgsValueTop extends Module { class PlusArgsValueSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitChirrtl(new PlusArgsValueTop) - val a1 = """(?s)extmodule PlusArgsValue_(\d+).*defname = PlusArgsValue_\1.*extmodule PlusArgsValue_(\d+).*defname = PlusArgsValue_\2""".r + val a1 = + """(?s)extmodule PlusArgsValue_(\d+).*defname = PlusArgsValue_\1.*extmodule PlusArgsValue_(\d+).*defname = PlusArgsValue_\2""".r (fir should include).regex(a1) // The second elaboration uses a unique name since the Builder is reused (?) From b9cfd3fd5f1cfa5ce8d6d277c0353c13b60e1390 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Tue, 4 Apr 2023 15:01:53 -0500 Subject: [PATCH 10/20] move to IntModule --- src/main/scala/chisel3/util/circt/IsX.scala | 9 ++---- .../chisel3/util/circt/PlusArgsTest.scala | 10 ++---- .../chisel3/util/circt/PlusArgsValue.scala | 10 ++---- .../scala/chisel3/util/circt/SizeOf.scala | 22 ++----------- src/test/scala/chiselTests/util/IsXSpec.scala | 31 +++++++------------ .../chiselTests/util/PlusArgsTestSpec.scala | 30 ++++++------------ .../chiselTests/util/PlusArgsValueSpec.scala | 25 +++++++-------- .../scala/chiselTests/util/SizeOfSpec.scala | 28 ++--------------- 8 files changed, 46 insertions(+), 119 deletions(-) diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala index 32dd565575d..8c81ee9affa 100644 --- a/src/main/scala/chisel3/util/circt/IsX.scala +++ b/src/main/scala/chisel3/util/circt/IsX.scala @@ -3,7 +3,7 @@ package chisel3.util.circt import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} +import chisel3.experimental.IntrinsicModule import chisel3.internal.Builder import circt.Intrinsic @@ -11,14 +11,9 @@ import circt.Intrinsic /** Create a module with a parameterized type which returns whether the input * is a verilog 'x'. */ -private class IsXIntrinsic[T <: Data](gen: T) extends ExtModule { +private class IsXIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt.isX") { val i = IO(Input(gen)) val found = IO(Output(UInt(1.W))) - annotate(new ChiselAnnotation { - override def toFirrtl = - Intrinsic(toTarget, "circt.isX") - }) - override val desiredName = "IsX_" + Builder.idGen.next } object IsX { diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index b02c4f6c2b1..9525a4ff88c 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -3,7 +3,7 @@ package chisel3.util.circt import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} +import chisel3.experimental.IntrinsicModule import chisel3.internal.Builder import circt.Intrinsic @@ -12,13 +12,9 @@ import circt.Intrinsic * $test$plusargs to test for the existance of the string str in the * simulator command line. */ -private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) extends ExtModule(Map("FORMAT" -> str)) { +private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) + extends IntrinsicModule("circt.plusargs.test", Map("FORMAT" -> str)) { val found = IO(Output(UInt(1.W))) - annotate(new ChiselAnnotation { - override def toFirrtl = - Intrinsic(toTarget, "circt.plusargs.test") - }) - override val desiredName = "PlusArgsTest_" + Builder.idGen.next } object PlusArgsTest { diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index 331f30b1fc9..3a220cfd376 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -3,7 +3,7 @@ package chisel3.util.circt import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule, FlatIO} +import chisel3.experimental.{FlatIO, IntrinsicModule} import chisel3.internal.Builder import circt.Intrinsic @@ -12,16 +12,12 @@ import circt.Intrinsic * value as indicated by the format string and a flag for whether the value * was found. */ -private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends ExtModule(Map("FORMAT" -> str)) { +private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) + extends IntrinsicModule("circt.plusargs.value", Map("FORMAT" -> str)) { val io = FlatIO(new Bundle { val found = Output(UInt(1.W)) val result = Output(gen) }) - annotate(new ChiselAnnotation { - override def toFirrtl = - Intrinsic(toTarget, "circt.plusargs.value") - }) - override val desiredName = "PlusArgsValue_" + Builder.idGen.next } object PlusArgsValue { diff --git a/src/main/scala/chisel3/util/circt/SizeOf.scala b/src/main/scala/chisel3/util/circt/SizeOf.scala index 7cb60e27022..2ca362c0194 100644 --- a/src/main/scala/chisel3/util/circt/SizeOf.scala +++ b/src/main/scala/chisel3/util/circt/SizeOf.scala @@ -3,34 +3,16 @@ package chisel3.util.circt import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, ExtModule} +import chisel3.experimental.IntrinsicModule import chisel3.internal.{Builder, BuilderContextCache} -import circt.Intrinsic - -// We have to unique designedName per type, be we can't due to name conflicts -// on bundles. Thus we use a globally unique id. -private object SizeOfGlobalIDGen { - private case object CacheKey extends BuilderContextCache.Key[Int] - def getID() = { - val oldID = Builder.contextCache.getOrElse(CacheKey, 0) - Builder.contextCache.put(CacheKey, oldID + 1) - oldID - } -} - /** Create a module with a parameterized type which returns the size of the type * as a compile-time constant. This lets you write code which depends on the * results of type inference. */ -private class SizeOfIntrinsic[T <: Data](gen: T) extends ExtModule { +private class SizeOfIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt.sizeof") { val i = IO(Input(gen)) val size = IO(Output(UInt(32.W))) - annotate(new ChiselAnnotation { - override def toFirrtl = - Intrinsic(toTarget, "circt.sizeof") - }) - override val desiredName = "SizeOf_" + Builder.idGen.next } object SizeOf { diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index b04c4168e7c..fb6d34c1fa1 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -3,9 +3,10 @@ package chiselTests.util import chisel3._ -import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import chisel3.stage.ChiselGeneratorAnnotation import chisel3.testers.BasicTester import chisel3.util.circt.IsX +import circt.stage.ChiselStage import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers @@ -31,26 +32,18 @@ private class IsXTop extends Module { io.outy := IsX(io.y) } -/** A test for intrinsics. Since chisel is producing intrinsics as tagged - * extmodules (for now), we explicitly test the chirrtl and annotations rather - * than the processed firrtl or verilog. It is worth noting that annotations - * are implemented (for now) in a way which makes the output valid for all - * firrtl compilers, hence we write a localized, not end-to-end test - */ class IsXSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { - val fir = ChiselStage.emitChirrtl(new IsXTop) - val a1 = - """(?s)extmodule IsX_(\d+).*defname = IsX_\1.*extmodule IsX_(\d+).*defname = IsX_\2.*extmodule IsX_(\d+).*defname = IsX_\3""".r - (fir should include).regex(a1) - - // The second elaboration uses a unique name since the Builder is reused (?) - val c = """Intrinsic\(~IsXTop\|IsX.*,circt.isX\)""" - ((new chisel3.stage.ChiselStage) - .execute( - args = Array("--no-run-firrtl"), - annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new IsXTop)) + val fir = ChiselStage.emitCHIRRTL(new IsXTop) + println(fir) + ( + (fir.split('\n').map(x => x.trim) should contain).allOf( + "intmodule IsXIntrinsic :", + "input i : UInt<65>", + "output found : UInt<1>", + "intrinsic = circt.isX", + "input i : { a : UInt, b : SInt}", ) - .mkString("\n") should include).regex(c) + ) } } diff --git a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala index 246b63f95ed..f08c1c1d3b7 100644 --- a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala @@ -3,9 +3,9 @@ package chiselTests.util import chisel3._ -import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} import chisel3.testers.BasicTester import chisel3.util.circt.PlusArgsTest +import circt.stage.ChiselStage import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers @@ -22,26 +22,16 @@ private class PlusArgsTestTop extends Module { io.x := PlusArgsTest(io.z, "BAR") } -/** A test for intrinsics. Since chisel is producing intrinsics as tagged - * extmodules (for now), we explicitly test the chirrtl and annotations rather - * than the processed firrtl or verilog. It is worth noting that annotations - * are implemented (for now) in a way which makes the output valid for all - * firrtl compilers, hence we write a localized, not end-to-end test - */ class PlusArgsTestSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { - val fir = ChiselStage.emitChirrtl(new PlusArgsTestTop) - val a1 = - """(?s)extmodule PlusArgsTest_(\d+).*defname = PlusArgsTest_\1.*extmodule PlusArgsTest_(\d+).*defname = PlusArgsTest_\2""".r - (fir should include).regex(a1) - - // The second elaboration uses a unique name since the Builder is reused (?) - val c = """Intrinsic\(~PlusArgsTestTop\|PlusArgsTest.*,circt.plusargs.test\)""" - ((new chisel3.stage.ChiselStage) - .execute( - args = Array("--no-run-firrtl"), - annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new PlusArgsTestTop)) - ) - .mkString("\n") should include).regex(c) + val fir = ChiselStage.emitCHIRRTL(new PlusArgsTestTop) + println(fir) + (fir.split('\n').map(x => x.trim) should contain).allOf( + "intmodule PlusArgsTestIntrinsic :", + "output found : UInt<1>", + "intrinsic = circt.plusargs.test", + "parameter FORMAT = \"FOO\"", + "parameter FORMAT = \"BAR\"" + ) } } diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index ebe0e2494d3..c054c60df00 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -3,9 +3,9 @@ package chiselTests.util import chisel3._ -import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} import chisel3.testers.BasicTester import chisel3.util.circt.PlusArgsValue +import circt.stage.ChiselStage import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers @@ -33,18 +33,15 @@ private class PlusArgsValueTop extends Module { */ class PlusArgsValueSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { - val fir = ChiselStage.emitChirrtl(new PlusArgsValueTop) - val a1 = - """(?s)extmodule PlusArgsValue_(\d+).*defname = PlusArgsValue_\1.*extmodule PlusArgsValue_(\d+).*defname = PlusArgsValue_\2""".r - (fir should include).regex(a1) - - // The second elaboration uses a unique name since the Builder is reused (?) - val c = """Intrinsic\(~PlusArgsValueTop\|PlusArgsValue.*,circt.plusargs.value\)""" - ((new chisel3.stage.ChiselStage) - .execute( - args = Array("--no-run-firrtl"), - annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new PlusArgsValueTop)) - ) - .mkString("\n") should include).regex(c) + val fir = ChiselStage.emitCHIRRTL(new PlusArgsValueTop) + println(fir) + (fir.split('\n').map(x => x.trim) should contain).inOrder( + "intmodule PlusArgsValueIntrinsic :", + "output found : UInt<1>", + "output result : UInt<32>", + "intrinsic = circt.plusargs.value", + "parameter FORMAT = \"FOO=%d\"", + "parameter FORMAT = \"BAR=%d\"" + ) } } diff --git a/src/test/scala/chiselTests/util/SizeOfSpec.scala b/src/test/scala/chiselTests/util/SizeOfSpec.scala index 37e79f1e4f9..04df988ec06 100644 --- a/src/test/scala/chiselTests/util/SizeOfSpec.scala +++ b/src/test/scala/chiselTests/util/SizeOfSpec.scala @@ -3,14 +3,10 @@ package chiselTests.util import chisel3._ -import chisel3.stage.ChiselGeneratorAnnotation import chisel3.testers.BasicTester import chisel3.util.circt.SizeOf - import circt.stage.ChiselStage -import firrtl.stage.FirrtlCircuitAnnotation - import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers @@ -32,29 +28,11 @@ private class SizeOfTop extends Module { io.outx := SizeOf(io.x) } -/** A test for intrinsics. Since chisel is producing intrinsics as tagged - * extmodules (for now), we explicitly test the chirrtl and annotations rather - * than the processed firrtl or verilog. It is worth noting that annotations - * are implemented (for now) in a way which makes the output valid for all - * firrtl compilers, hence we write a localized, not end-to-end test - */ class SizeOfSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitCHIRRTL(new SizeOfTop) - val a1 = """extmodule SizeOf_0""".r - (fir should include).regex(a1) - - // The second elaboration uses a unique name since the Builder is reused (?) - val c = """Intrinsic\(~SizeOfTop\|SizeOf.*,circt.sizeof\)""" - ((new ChiselStage) - .execute( - args = Array("--target", "chirrtl"), - annotations = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new SizeOfTop)) - ) - .flatMap { - case FirrtlCircuitAnnotation(circuit) => circuit.annotations - case _ => None - } - .mkString("\n") should include).regex(c) + println(fir) + (fir.split('\n').map(x => x.trim) should contain) + .allOf("intmodule SizeOfIntrinsic :", "input i : UInt<65>", "output size : UInt<32>", "intrinsic = circt.sizeof") } } From f9272add9ce132dd653317b2b4c1c41aae11ee16 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Tue, 4 Apr 2023 15:02:33 -0500 Subject: [PATCH 11/20] Update src/main/scala/chisel3/util/circt/IsX.scala Co-authored-by: Megan Wachs --- src/main/scala/chisel3/util/circt/IsX.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala index 8c81ee9affa..2ecc76f4295 100644 --- a/src/main/scala/chisel3/util/circt/IsX.scala +++ b/src/main/scala/chisel3/util/circt/IsX.scala @@ -21,7 +21,7 @@ object IsX { /** Creates an intrinsic which returns whether the input is a verilog 'x'. * * @example {{{ - * b := isX(a) + * b := IsX(a) * }}} */ def apply[T <: Data](gen: T): Data = { From 9e3c79c648cebd158e9112a9f9de6694e2aa4cc1 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Tue, 4 Apr 2023 15:02:41 -0500 Subject: [PATCH 12/20] Update src/main/scala/chisel3/util/circt/PlusArgsTest.scala Co-authored-by: Megan Wachs --- src/main/scala/chisel3/util/circt/PlusArgsTest.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 9525a4ff88c..b88b50798eb 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -9,7 +9,7 @@ import chisel3.internal.Builder import circt.Intrinsic /** Create a module with a parameterized type which calls the verilog function - * $test$plusargs to test for the existance of the string str in the + * $test$plusargs to test for the existence of the string str in the * simulator command line. */ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) From d2e7ca24b6c78feba3066981cb65af2566aae471 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Tue, 4 Apr 2023 15:04:16 -0500 Subject: [PATCH 13/20] Update src/main/scala/chisel3/util/circt/PlusArgsValue.scala Co-authored-by: Megan Wachs --- src/main/scala/chisel3/util/circt/PlusArgsValue.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index 3a220cfd376..174332f0356 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -25,7 +25,7 @@ object PlusArgsValue { /** Creates an intrinsic which calls $test$plusargs. * * @example {{{ - * b := PlusArgsValue(UInt<32.W>, "FOO=%d") + * b := PlusArgsValue(UInt(32.W), "FOO=%d") * b.found * b.value * }}} From ebff9eda413207b19bb428cdaecee08f4ff49a5b Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Tue, 4 Apr 2023 15:16:00 -0500 Subject: [PATCH 14/20] sync --- src/main/scala/chisel3/util/circt/PlusArgsTest.scala | 2 +- src/main/scala/chisel3/util/circt/PlusArgsValue.scala | 2 +- src/test/scala/chiselTests/util/IsXSpec.scala | 2 +- src/test/scala/chiselTests/util/PlusArgsValueSpec.scala | 6 ------ 4 files changed, 3 insertions(+), 9 deletions(-) diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 9525a4ff88c..aada2b29645 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -9,7 +9,7 @@ import chisel3.internal.Builder import circt.Intrinsic /** Create a module with a parameterized type which calls the verilog function - * $test$plusargs to test for the existance of the string str in the + * \$test\$plusargs to test for the existence of the string str in the * simulator command line. */ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index 3a220cfd376..5444f672ce5 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -8,7 +8,7 @@ import chisel3.internal.Builder import circt.Intrinsic -/** Create a module which generates a verilog $plusargs$value. This returns a +/** Create a module which generates a verilog \$plusargs\$value. This returns a * value as indicated by the format string and a flag for whether the value * was found. */ diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index fb6d34c1fa1..39bf2fb8dbd 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -42,7 +42,7 @@ class IsXSpec extends AnyFlatSpec with Matchers { "input i : UInt<65>", "output found : UInt<1>", "intrinsic = circt.isX", - "input i : { a : UInt, b : SInt}", + "input i : { a : UInt, b : SInt}" ) ) } diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index c054c60df00..8043181dd1f 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -25,12 +25,6 @@ private class PlusArgsValueTop extends Module { io.xv := tmpx.result } -/** A test for intrinsics. Since chisel is producing intrinsics as tagged - * extmodules (for now), we explicitly test the chirrtl and annotations rather - * than the processed firrtl or verilog. It is worth noting that annotations - * are implemented (for now) in a way which makes the output valid for all - * firrtl compilers, hence we write a localized, not end-to-end test - */ class PlusArgsValueSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitCHIRRTL(new PlusArgsValueTop) From 7f205ebfa66948300a3b0931dcfc00abbd911f85 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Tue, 4 Apr 2023 15:23:26 -0500 Subject: [PATCH 15/20] mdoc --- src/main/scala/chisel3/util/circt/PlusArgsTest.scala | 2 +- src/main/scala/chisel3/util/circt/PlusArgsValue.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index aada2b29645..113b1f07a9b 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -19,7 +19,7 @@ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) object PlusArgsTest { - /** Creates an intrinsic which calls $test$plusargs. + /** Creates an intrinsic which calls \$test\$plusargs. * * @example {{{ * b := PlusArgsTest(UInt<32.W>, "FOO") diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index 14ef35f29f7..97d620f8e91 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -22,7 +22,7 @@ private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) object PlusArgsValue { - /** Creates an intrinsic which calls $test$plusargs. + /** Creates an intrinsic which calls \$test\$plusargs. * * @example {{{ * b := PlusArgsValue(UInt(32.W), "FOO=%d") From 8ffe833a32e167a292d4856ce3dd1ff9e99dbb2c Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Wed, 5 Apr 2023 09:58:48 -0500 Subject: [PATCH 16/20] tweaks --- src/main/scala/chisel3/util/circt/PlusArgsTest.scala | 12 +++++------- .../scala/chisel3/util/circt/PlusArgsValue.scala | 12 +++++------- src/test/scala/chiselTests/util/IsXSpec.scala | 2 +- .../scala/chiselTests/util/PlusArgsTestSpec.scala | 2 +- .../scala/chiselTests/util/PlusArgsValueSpec.scala | 2 +- src/test/scala/chiselTests/util/SizeOfSpec.scala | 2 +- 6 files changed, 14 insertions(+), 18 deletions(-) diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 113b1f07a9b..67b41763472 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -14,7 +14,7 @@ import circt.Intrinsic */ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) extends IntrinsicModule("circt.plusargs.test", Map("FORMAT" -> str)) { - val found = IO(Output(UInt(1.W))) + val found = IO(Output(Bool())) } object PlusArgsTest { @@ -26,12 +26,10 @@ object PlusArgsTest { * }}} */ def apply[T <: Data](gen: T, str: String): Data = { - if (gen.isSynthesizable) { - val inst = Module(new PlusArgsTestIntrinsic(chiselTypeOf(gen), str)) - inst.found + Module(if (gen.isSynthesizable) { + new PlusArgsTestIntrinsic(chiselTypeOf(gen), str) } else { - val inst = Module(new PlusArgsTestIntrinsic(gen, str)) - inst.found - } + new PlusArgsTestIntrinsic(gen, str) + }).found } } diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index 97d620f8e91..ed190fbf0b8 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -15,7 +15,7 @@ import circt.Intrinsic private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) extends IntrinsicModule("circt.plusargs.value", Map("FORMAT" -> str)) { val io = FlatIO(new Bundle { - val found = Output(UInt(1.W)) + val found = Output(Bool()) val result = Output(gen) }) } @@ -31,12 +31,10 @@ object PlusArgsValue { * }}} */ def apply[T <: Data](gen: T, str: String) = { - if (gen.isSynthesizable) { - val inst = Module(new PlusArgsValueIntrinsic(chiselTypeOf(gen), str)) - inst.io + Module(if (gen.isSynthesizable) { + new PlusArgsValueIntrinsic(chiselTypeOf(gen), str) } else { - val inst = Module(new PlusArgsValueIntrinsic(gen, str)) - inst.io - } + new PlusArgsValueIntrinsic(gen, str) + }).io } } diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index 39bf2fb8dbd..64835a86e57 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -37,7 +37,7 @@ class IsXSpec extends AnyFlatSpec with Matchers { val fir = ChiselStage.emitCHIRRTL(new IsXTop) println(fir) ( - (fir.split('\n').map(x => x.trim) should contain).allOf( + (fir.split('\n').map(_.trim) should contain).allOf( "intmodule IsXIntrinsic :", "input i : UInt<65>", "output found : UInt<1>", diff --git a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala index f08c1c1d3b7..6c66a1f5f6e 100644 --- a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala @@ -26,7 +26,7 @@ class PlusArgsTestSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitCHIRRTL(new PlusArgsTestTop) println(fir) - (fir.split('\n').map(x => x.trim) should contain).allOf( + (fir.split('\n').map(_.trim) should contain).allOf( "intmodule PlusArgsTestIntrinsic :", "output found : UInt<1>", "intrinsic = circt.plusargs.test", diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index 8043181dd1f..4390d319416 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -29,7 +29,7 @@ class PlusArgsValueSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitCHIRRTL(new PlusArgsValueTop) println(fir) - (fir.split('\n').map(x => x.trim) should contain).inOrder( + (fir.split('\n').map(_.trim) should contain).inOrder( "intmodule PlusArgsValueIntrinsic :", "output found : UInt<1>", "output result : UInt<32>", diff --git a/src/test/scala/chiselTests/util/SizeOfSpec.scala b/src/test/scala/chiselTests/util/SizeOfSpec.scala index 04df988ec06..e67da5af855 100644 --- a/src/test/scala/chiselTests/util/SizeOfSpec.scala +++ b/src/test/scala/chiselTests/util/SizeOfSpec.scala @@ -32,7 +32,7 @@ class SizeOfSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitCHIRRTL(new SizeOfTop) println(fir) - (fir.split('\n').map(x => x.trim) should contain) + (fir.split('\n').map(_.trim) should contain) .allOf("intmodule SizeOfIntrinsic :", "input i : UInt<65>", "output size : UInt<32>", "intrinsic = circt.sizeof") } } From f22549a7503a20c50bd656835e1b9d0388a87f62 Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Wed, 5 Apr 2023 10:19:39 -0500 Subject: [PATCH 17/20] use valid identifiers, as required by intmodule --- src/main/scala/chisel3/util/circt/IsX.scala | 2 +- .../chisel3/util/circt/PlusArgsTest.scala | 2 +- .../chisel3/util/circt/PlusArgsValue.scala | 2 +- .../scala/chisel3/util/circt/SizeOf.scala | 2 +- src/test/scala/chiselTests/util/IsXSpec.scala | 2 +- .../chiselTests/util/PlusArgsTestSpec.scala | 2 +- .../chiselTests/util/PlusArgsValueSpec.scala | 20 +++++++++---------- .../scala/chiselTests/util/SizeOfSpec.scala | 2 +- 8 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala index 2ecc76f4295..a529f3f25e9 100644 --- a/src/main/scala/chisel3/util/circt/IsX.scala +++ b/src/main/scala/chisel3/util/circt/IsX.scala @@ -11,7 +11,7 @@ import circt.Intrinsic /** Create a module with a parameterized type which returns whether the input * is a verilog 'x'. */ -private class IsXIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt.isX") { +private class IsXIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt_isX") { val i = IO(Input(gen)) val found = IO(Output(UInt(1.W))) } diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index 67b41763472..e5d7213a67d 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -13,7 +13,7 @@ import circt.Intrinsic * simulator command line. */ private class PlusArgsTestIntrinsic[T <: Data](gen: T, str: String) - extends IntrinsicModule("circt.plusargs.test", Map("FORMAT" -> str)) { + extends IntrinsicModule("circt_plusargs_test", Map("FORMAT" -> str)) { val found = IO(Output(Bool())) } diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index ed190fbf0b8..f9000ad250d 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -13,7 +13,7 @@ import circt.Intrinsic * was found. */ private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) - extends IntrinsicModule("circt.plusargs.value", Map("FORMAT" -> str)) { + extends IntrinsicModule("circt_plusargs_value", Map("FORMAT" -> str)) { val io = FlatIO(new Bundle { val found = Output(Bool()) val result = Output(gen) diff --git a/src/main/scala/chisel3/util/circt/SizeOf.scala b/src/main/scala/chisel3/util/circt/SizeOf.scala index 2ca362c0194..7667e28b76f 100644 --- a/src/main/scala/chisel3/util/circt/SizeOf.scala +++ b/src/main/scala/chisel3/util/circt/SizeOf.scala @@ -10,7 +10,7 @@ import chisel3.internal.{Builder, BuilderContextCache} * as a compile-time constant. This lets you write code which depends on the * results of type inference. */ -private class SizeOfIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt.sizeof") { +private class SizeOfIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt_sizeof") { val i = IO(Input(gen)) val size = IO(Output(UInt(32.W))) } diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index 64835a86e57..7440eb62d81 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -41,7 +41,7 @@ class IsXSpec extends AnyFlatSpec with Matchers { "intmodule IsXIntrinsic :", "input i : UInt<65>", "output found : UInt<1>", - "intrinsic = circt.isX", + "intrinsic = circt_isX", "input i : { a : UInt, b : SInt}" ) ) diff --git a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala index 6c66a1f5f6e..523fb028a21 100644 --- a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala @@ -29,7 +29,7 @@ class PlusArgsTestSpec extends AnyFlatSpec with Matchers { (fir.split('\n').map(_.trim) should contain).allOf( "intmodule PlusArgsTestIntrinsic :", "output found : UInt<1>", - "intrinsic = circt.plusargs.test", + "intrinsic = circt_plusargs_test", "parameter FORMAT = \"FOO\"", "parameter FORMAT = \"BAR\"" ) diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index 4390d319416..2257a197765 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -13,16 +13,16 @@ import org.scalatest.matchers.should.Matchers import scala.io.Source private class PlusArgsValueTop extends Module { - val io = IO(new Bundle { - val wf = Output(UInt(1.W)) - val wv = Output(UInt(32.W)) - val xf = Output(UInt(1.W)) - val xv = Output(UInt(32.W)) - }) + val wf = IO(Output(UInt(1.W))) + val wv = IO(Output(UInt(32.W))) + val xf = IO(Output(UInt(1.W))) + val xv = IO(Output(UInt(32.W))) val tmpw = PlusArgsValue(UInt(32.W), "FOO=%d") - val tmpx = PlusArgsValue(io.xv, "BAR=%d") - io.xf := tmpx.found - io.xv := tmpx.result + val tmpx = PlusArgsValue(xv, "BAR=%d") + wf := tmpw.found + wv := tmpw.result + xf := tmpx.found + xv := tmpx.result } class PlusArgsValueSpec extends AnyFlatSpec with Matchers { @@ -33,7 +33,7 @@ class PlusArgsValueSpec extends AnyFlatSpec with Matchers { "intmodule PlusArgsValueIntrinsic :", "output found : UInt<1>", "output result : UInt<32>", - "intrinsic = circt.plusargs.value", + "intrinsic = circt_plusargs_value", "parameter FORMAT = \"FOO=%d\"", "parameter FORMAT = \"BAR=%d\"" ) diff --git a/src/test/scala/chiselTests/util/SizeOfSpec.scala b/src/test/scala/chiselTests/util/SizeOfSpec.scala index e67da5af855..e14e7e445a4 100644 --- a/src/test/scala/chiselTests/util/SizeOfSpec.scala +++ b/src/test/scala/chiselTests/util/SizeOfSpec.scala @@ -33,6 +33,6 @@ class SizeOfSpec extends AnyFlatSpec with Matchers { val fir = ChiselStage.emitCHIRRTL(new SizeOfTop) println(fir) (fir.split('\n').map(_.trim) should contain) - .allOf("intmodule SizeOfIntrinsic :", "input i : UInt<65>", "output size : UInt<32>", "intrinsic = circt.sizeof") + .allOf("intmodule SizeOfIntrinsic :", "input i : UInt<65>", "output size : UInt<32>", "intrinsic = circt_sizeof") } } From 16eb559d57e6ca6430e59ee1b1937931be12f25b Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Wed, 5 Apr 2023 10:50:01 -0500 Subject: [PATCH 18/20] tweak --- src/test/scala/chiselTests/util/IsXSpec.scala | 20 +++++++++---------- .../chiselTests/util/PlusArgsTestSpec.scala | 12 +++++------ .../scala/chiselTests/util/SizeOfSpec.scala | 14 ++++++------- 3 files changed, 20 insertions(+), 26 deletions(-) diff --git a/src/test/scala/chiselTests/util/IsXSpec.scala b/src/test/scala/chiselTests/util/IsXSpec.scala index 7440eb62d81..fb963d4c067 100644 --- a/src/test/scala/chiselTests/util/IsXSpec.scala +++ b/src/test/scala/chiselTests/util/IsXSpec.scala @@ -19,17 +19,15 @@ private class IsXBundle extends Bundle { } private class IsXTop extends Module { - val io = IO(new Bundle { - val w = Input(UInt(65.W)) - val x = Input(new IsXBundle) - val y = Input(UInt(65.W)) - val outw = UInt(1.W) - val outx = UInt(1.W) - val outy = UInt(1.W) - }) - io.outw := IsX(io.w) - io.outx := IsX(io.x) - io.outy := IsX(io.y) + val w = IO(Input(UInt(65.W))) + val x = IO(Input(new IsXBundle)) + val y = IO(Input(UInt(65.W))) + val outw = IO(Output(UInt(1.W))) + val outx = IO(Output(UInt(1.W))) + val outy = IO(Output(UInt(1.W))) + outw := IsX(w) + outx := IsX(x) + outy := IsX(y) } class IsXSpec extends AnyFlatSpec with Matchers { diff --git a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala index 523fb028a21..40936d9d8af 100644 --- a/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsTestSpec.scala @@ -13,13 +13,11 @@ import org.scalatest.matchers.should.Matchers import scala.io.Source private class PlusArgsTestTop extends Module { - val io = IO(new Bundle { - val w = Output(UInt(1.W)) - val x = Output(UInt(1.W)) - val z = Input(UInt(32.W)) - }) - io.w := PlusArgsTest(UInt(32.W), "FOO") - io.x := PlusArgsTest(io.z, "BAR") + val w = IO(Output(UInt(1.W))) + val x = IO(Output(UInt(1.W))) + val z = IO(Input(UInt(32.W))) + w := PlusArgsTest(UInt(32.W), "FOO") + x := PlusArgsTest(z, "BAR") } class PlusArgsTestSpec extends AnyFlatSpec with Matchers { diff --git a/src/test/scala/chiselTests/util/SizeOfSpec.scala b/src/test/scala/chiselTests/util/SizeOfSpec.scala index e14e7e445a4..a185a7340d3 100644 --- a/src/test/scala/chiselTests/util/SizeOfSpec.scala +++ b/src/test/scala/chiselTests/util/SizeOfSpec.scala @@ -18,14 +18,12 @@ private class SizeOfBundle extends Bundle { } private class SizeOfTop extends Module { - val io = IO(new Bundle { - val w = Input(UInt(65.W)) - val x = Input(new SizeOfBundle) - val outw = UInt(32.W) - val outx = UInt(32.W) - }) - io.outw := SizeOf(io.w) - io.outx := SizeOf(io.x) + val w = IO(Input(UInt(65.W))) + val x = IO(Input(new SizeOfBundle)) + val outw = IO(Output(UInt(32.W))) + val outx = IO(Output(UInt(32.W))) + outw := SizeOf(w) + outx := SizeOf(x) } class SizeOfSpec extends AnyFlatSpec with Matchers { From 94e8c04c3d8306dc0ad4dfed9d0a844225f48f4d Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Thu, 6 Apr 2023 18:54:43 -0500 Subject: [PATCH 19/20] Defaulting version too. Not really an intrnisic anymore, but as good a place to put the function as any other --- src/main/scala/chisel3/util/circt/IsX.scala | 4 ++-- .../chisel3/util/circt/PlusArgsTest.scala | 2 +- .../chisel3/util/circt/PlusArgsValue.scala | 18 ++++++++++++++++-- .../chiselTests/util/PlusArgsValueSpec.scala | 5 ++++- 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/src/main/scala/chisel3/util/circt/IsX.scala b/src/main/scala/chisel3/util/circt/IsX.scala index a529f3f25e9..4d1ccd9db89 100644 --- a/src/main/scala/chisel3/util/circt/IsX.scala +++ b/src/main/scala/chisel3/util/circt/IsX.scala @@ -13,7 +13,7 @@ import circt.Intrinsic */ private class IsXIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt_isX") { val i = IO(Input(gen)) - val found = IO(Output(UInt(1.W))) + val found = IO(Output(Bool())) } object IsX { @@ -24,7 +24,7 @@ object IsX { * b := IsX(a) * }}} */ - def apply[T <: Data](gen: T): Data = { + def apply[T <: Data](gen: T): Bool = { val inst = Module(new IsXIntrinsic(chiselTypeOf(gen))) inst.i := gen inst.found diff --git a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala index e5d7213a67d..895975df79b 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsTest.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsTest.scala @@ -25,7 +25,7 @@ object PlusArgsTest { * b := PlusArgsTest(UInt<32.W>, "FOO") * }}} */ - def apply[T <: Data](gen: T, str: String): Data = { + def apply[T <: Data](gen: T, str: String): Bool = { Module(if (gen.isSynthesizable) { new PlusArgsTestIntrinsic(chiselTypeOf(gen), str) } else { diff --git a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala index f9000ad250d..23412b2a259 100644 --- a/src/main/scala/chisel3/util/circt/PlusArgsValue.scala +++ b/src/main/scala/chisel3/util/circt/PlusArgsValue.scala @@ -2,13 +2,15 @@ package chisel3.util.circt +import scala.language.reflectiveCalls + import chisel3._ import chisel3.experimental.{FlatIO, IntrinsicModule} import chisel3.internal.Builder import circt.Intrinsic -/** Create a module which generates a verilog \$plusargs\$value. This returns a +/** Create a module which generates a verilog \$value\$plusargs. This returns a * value as indicated by the format string and a flag for whether the value * was found. */ @@ -22,7 +24,7 @@ private class PlusArgsValueIntrinsic[T <: Data](gen: T, str: String) object PlusArgsValue { - /** Creates an intrinsic which calls \$test\$plusargs. + /** Creates an intrinsic which calls \$value\$plusargs. * * @example {{{ * b := PlusArgsValue(UInt(32.W), "FOO=%d") @@ -37,4 +39,16 @@ object PlusArgsValue { new PlusArgsValueIntrinsic(gen, str) }).io } + + /** Creates an intrinsic which calls \$value\$plusargs and returns a default + * value if the specified pattern is not found. + * + * @example {{{ + * v := PlusArgsValue(UInt(32.W), "FOO=%d", 42.U) + * }}} + */ + def apply[T <: Data](gen: T, str: String, default: T): T = { + val result = apply(gen, str) + Mux(result.found, result.result, default) + } } diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index 2257a197765..35ef00e3c45 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -17,8 +17,10 @@ private class PlusArgsValueTop extends Module { val wv = IO(Output(UInt(32.W))) val xf = IO(Output(UInt(1.W))) val xv = IO(Output(UInt(32.W))) + val zv = IO(Output(UInt(32.W))) val tmpw = PlusArgsValue(UInt(32.W), "FOO=%d") val tmpx = PlusArgsValue(xv, "BAR=%d") + zv := PlusArgsValue(xv, "BAR=%d", 42.U) wf := tmpw.found wv := tmpw.result xf := tmpx.found @@ -35,7 +37,8 @@ class PlusArgsValueSpec extends AnyFlatSpec with Matchers { "output result : UInt<32>", "intrinsic = circt_plusargs_value", "parameter FORMAT = \"FOO=%d\"", - "parameter FORMAT = \"BAR=%d\"" + "parameter FORMAT = \"BAR=%d\"", + "node _zv_T = mux(PlusArgsValueIntrinsic_2.found, PlusArgsValueIntrinsic_2.result, UInt<6>(\"h2a\")) @[src/main/scala/chisel3/util/circt/PlusArgsValue.scala 52:8]" ) } } From dbbf6c0c45b11df23a7b37a66131e6f57cf0c03d Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Sat, 8 Apr 2023 13:15:05 -0500 Subject: [PATCH 20/20] tweak --- src/test/scala/chiselTests/util/PlusArgsValueSpec.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala index 35ef00e3c45..11b22619710 100644 --- a/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala +++ b/src/test/scala/chiselTests/util/PlusArgsValueSpec.scala @@ -31,14 +31,14 @@ class PlusArgsValueSpec extends AnyFlatSpec with Matchers { it should "Should work for types" in { val fir = ChiselStage.emitCHIRRTL(new PlusArgsValueTop) println(fir) - (fir.split('\n').map(_.trim) should contain).inOrder( + (fir.split('\n').map(_.trim.takeWhile(_ != '@')) should contain).inOrder( "intmodule PlusArgsValueIntrinsic :", "output found : UInt<1>", "output result : UInt<32>", "intrinsic = circt_plusargs_value", "parameter FORMAT = \"FOO=%d\"", "parameter FORMAT = \"BAR=%d\"", - "node _zv_T = mux(PlusArgsValueIntrinsic_2.found, PlusArgsValueIntrinsic_2.result, UInt<6>(\"h2a\")) @[src/main/scala/chisel3/util/circt/PlusArgsValue.scala 52:8]" + "node _zv_T = mux(PlusArgsValueIntrinsic_2.found, PlusArgsValueIntrinsic_2.result, UInt<6>(\"h2a\")) " ) } }