From 614438c4496714a30c58a5a5ea6b83afb89a97e8 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 3 Feb 2021 19:55:36 -0500 Subject: [PATCH 1/4] Remove chisel3.stage.phases.DriverCompatibility Signed-off-by: Schuyler Eldridge --- .../stage/phases/DriverCompatibility.scala | 152 +----------------- .../phases/DriverCompatibilitySpec.scala | 71 -------- 2 files changed, 2 insertions(+), 221 deletions(-) delete mode 100644 src/test/scala/chisel3/stage/phases/DriverCompatibilitySpec.scala diff --git a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala index 659914ae63d..f07d6c4a818 100644 --- a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala +++ b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala @@ -16,153 +16,5 @@ import chisel3.stage.{ChiselStage, NoRunFirrtlCompilerAnnotation, ChiselOutputFi * Primarily, this object includes [[firrtl.options.Phase Phase]]s that generate [[firrtl.annotations.Annotation]]s * derived from the deprecated [[firrtl.stage.phases.DriverCompatibility.TopNameAnnotation]]. */ -object DriverCompatibility { - - /** Adds a [[ChiselOutputFileAnnotation]] derived from a [[TopNameAnnotation]] if no [[ChiselOutputFileAnnotation]] - * already exists. If no [[TopNameAnnotation]] exists, then no [[firrtl.stage.OutputFileAnnotation]] is added. ''This is not a - * replacement for [[chisel3.stage.phases.AddImplicitOutputFile AddImplicitOutputFile]] as this only adds an output - * file based on a discovered top name and not on a discovered elaborated circuit.'' Consequently, this will provide - * the correct behavior before a circuit has been elaborated. - * @note the output suffix is unspecified and will be set by the underlying [[firrtl.EmittedComponent]] - */ - private [chisel3] class AddImplicitOutputFile extends Phase { - - override def prerequisites = Seq.empty - override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.ChiselStage]) - override def invalidates(a: Phase) = false - - def transform(annotations: AnnotationSeq): AnnotationSeq = { - val hasOutputFile = annotations - .collectFirst{ case a: ChiselOutputFileAnnotation => a } - .isDefined - lazy val top = annotations.collectFirst{ case TopNameAnnotation(a) => a } - - if (!hasOutputFile && top.isDefined) { - ChiselOutputFileAnnotation(top.get) +: annotations - } else { - annotations - } - } - } - - /** If a [[firrtl.options.OutputAnnotationFileAnnotation]] does not exist, this adds one derived from a - * [[TopNameAnnotation]]. ''This is not a replacement for [[chisel3.stage.phases.AddImplicitOutputAnnotationFile]] as - * this only adds an output annotation file based on a discovered top name.'' Consequently, this will provide the - * correct behavior before a circuit has been elaborated. - * @note the output suffix is unspecified and will be set by [[firrtl.options.phases.WriteOutputAnnotations]] - */ - private[chisel3] class AddImplicitOutputAnnotationFile extends Phase { - - override def prerequisites = Seq.empty - override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Seq(Dependency[chisel3.stage.ChiselStage]) - override def invalidates(a: Phase) = false - - def transform(annotations: AnnotationSeq): AnnotationSeq = - annotations - .collectFirst{ case _: OutputAnnotationFileAnnotation => annotations } - .getOrElse{ - val top = annotations.collectFirst{ case TopNameAnnotation(a) => a } - if (top.isDefined) { - OutputAnnotationFileAnnotation(top.get) +: annotations - } else { - annotations - } - } - } - - private[chisel3] case object RunFirrtlCompilerAnnotation extends NoTargetAnnotation - - /** Disables the execution of [[firrtl.stage.FirrtlStage]]. This can be used to call [[chisel3.stage.ChiselStage]] and - * guarantee that the FIRRTL compiler will not run. This is necessary for certain [[chisel3.Driver]] compatibility - * situations where you need to do something between Chisel compilation and FIRRTL compilations, e.g., update a - * mutable data structure. - */ - private[chisel3] class DisableFirrtlStage extends Phase { - - override def prerequisites = Seq.empty - override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Seq(Dependency[ChiselStage]) - override def invalidates(a: Phase) = false - - def transform(annotations: AnnotationSeq): AnnotationSeq = annotations - .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations } - .getOrElse { Seq(RunFirrtlCompilerAnnotation, NoRunFirrtlCompilerAnnotation) ++ annotations } - } - - private[chisel3] class ReEnableFirrtlStage extends Phase { - - override def prerequisites = Seq(Dependency[DisableFirrtlStage], Dependency[ChiselStage]) - override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Seq.empty - override def invalidates(a: Phase) = false - - def transform(annotations: AnnotationSeq): AnnotationSeq = annotations - .collectFirst { case RunFirrtlCompilerAnnotation => - val a: AnnotationSeq = annotations.filter { - case NoRunFirrtlCompilerAnnotation | RunFirrtlCompilerAnnotation => false - case _ => true - } - a - } - .getOrElse{ annotations } - - } - - private[chisel3] case class OptionsManagerAnnotation( - manager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions) - extends NoTargetAnnotation with Unserializable - - /** Mutate an input [[firrtl.ExecutionOptionsManager]] based on information encoded in an [[firrtl.AnnotationSeq]]. - * This is intended to be run between [[chisel3.stage.ChiselStage ChiselStage]] and [[firrtl.stage.FirrtlStage]] if - * you want to have backwards compatibility with an [[firrtl.ExecutionOptionsManager]]. - */ - private[chisel3] class MutateOptionsManager extends Phase { - - override def prerequisites = Seq(Dependency[chisel3.stage.ChiselStage]) - override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Seq(Dependency[ReEnableFirrtlStage]) - override def invalidates(a: Phase) = false - - def transform(annotations: AnnotationSeq): AnnotationSeq = { - - val optionsManager = annotations - .collectFirst{ case OptionsManagerAnnotation(a) => a } - .getOrElse{ throw new OptionsException( - "An OptionsManagerException must exist for Chisel Driver compatibility mode") } - - val firrtlCircuit = annotations.collectFirst{ case FirrtlCircuitAnnotation(a) => a } - optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy( - firrtlCircuit = firrtlCircuit, - annotations = optionsManager.firrtlOptions.annotations ++ annotations, - customTransforms = optionsManager.firrtlOptions.customTransforms ++ - annotations.collect{ case RunFirrtlTransformAnnotation(a) => a } ) - - annotations - - } - - } - - /** A [[Phase]] that lets us run - * @todo a better solution than the current state hack below may be needed - */ - private [chisel3] class FirrtlPreprocessing extends Phase { - - override def prerequisites = Seq(Dependency[ChiselStage], Dependency[MutateOptionsManager], Dependency[ReEnableFirrtlStage]) - override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Seq(Dependency[MaybeFirrtlStage]) - override def invalidates(a: Phase) = false - - private val phases = - Seq( new firrtl.stage.phases.DriverCompatibility.AddImplicitOutputFile, - new firrtl.stage.phases.DriverCompatibility.AddImplicitEmitter ) - - override def transform(annotations: AnnotationSeq): AnnotationSeq = - phases - .foldLeft(annotations)( (a, p) => p.transform(a) ) - - } - -} +@deprecated("This object contains no public members. This will be removed in FIRRTL 1.5.", "FIRRTL 1.5") +object DriverCompatibility diff --git a/src/test/scala/chisel3/stage/phases/DriverCompatibilitySpec.scala b/src/test/scala/chisel3/stage/phases/DriverCompatibilitySpec.scala deleted file mode 100644 index b80d5298ace..00000000000 --- a/src/test/scala/chisel3/stage/phases/DriverCompatibilitySpec.scala +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package chisel3.stage.phases - - -import chisel3.stage.{NoRunFirrtlCompilerAnnotation, ChiselOutputFileAnnotation} - -import firrtl.options.{OutputAnnotationFileAnnotation, StageOptions} -import firrtl.options.Viewer.view -import firrtl.stage.phases.DriverCompatibility.TopNameAnnotation -import org.scalatest.flatspec.AnyFlatSpec -import org.scalatest.matchers.should.Matchers - -class DriverCompatibilitySpec extends AnyFlatSpec with Matchers { - - behavior of classOf[DriverCompatibility.AddImplicitOutputFile].toString - - it should "do nothing if a ChiselOutputFileAnnotation is present" in { - val annotations = Seq( - ChiselOutputFileAnnotation("Foo"), - TopNameAnnotation("Bar") ) - (new DriverCompatibility.AddImplicitOutputFile).transform(annotations).toSeq should be (annotations) - } - - it should "add a ChiselOutputFileAnnotation derived from a TopNameAnnotation" in { - val annotations = Seq( TopNameAnnotation("Bar") ) - val expected = ChiselOutputFileAnnotation("Bar") +: annotations - (new DriverCompatibility.AddImplicitOutputFile).transform(annotations).toSeq should be (expected) - } - - behavior of classOf[DriverCompatibility.AddImplicitOutputAnnotationFile].toString - - it should "do nothing if an OutputAnnotationFileAnnotation is present" in { - val annotations = Seq( - OutputAnnotationFileAnnotation("Foo"), - TopNameAnnotation("Bar") ) - (new DriverCompatibility.AddImplicitOutputAnnotationFile).transform(annotations).toSeq should be (annotations) - } - - it should "add an OutputAnnotationFileAnnotation derived from a TopNameAnnotation" in { - val annotations = Seq( TopNameAnnotation("Bar") ) - val expected = OutputAnnotationFileAnnotation("Bar") +: annotations - (new DriverCompatibility.AddImplicitOutputAnnotationFile).transform(annotations).toSeq should be (expected) - } - - behavior of classOf[DriverCompatibility.DisableFirrtlStage].toString - - it should "add a NoRunFirrtlCompilerAnnotation if one does not exist" in { - val annos = Seq(NoRunFirrtlCompilerAnnotation) - val expected = DriverCompatibility.RunFirrtlCompilerAnnotation +: annos - (new DriverCompatibility.DisableFirrtlStage).transform(Seq.empty).toSeq should be (expected) - } - - it should "NOT add a NoRunFirrtlCompilerAnnotation if one already exists" in { - val annos = Seq(NoRunFirrtlCompilerAnnotation) - (new DriverCompatibility.DisableFirrtlStage).transform(annos).toSeq should be (annos) - } - - behavior of classOf[DriverCompatibility.ReEnableFirrtlStage].toString - - it should "NOT strip a NoRunFirrtlCompilerAnnotation if NO RunFirrtlCompilerAnnotation is present" in { - val annos = Seq(NoRunFirrtlCompilerAnnotation, DriverCompatibility.RunFirrtlCompilerAnnotation) - (new DriverCompatibility.ReEnableFirrtlStage).transform(annos).toSeq should be (Seq.empty) - } - - it should "strip a NoRunFirrtlCompilerAnnotation if a RunFirrtlCompilerAnnotation is present" in { - val annos = Seq(NoRunFirrtlCompilerAnnotation) - (new DriverCompatibility.ReEnableFirrtlStage).transform(annos).toSeq should be (annos) - } - -} From 6778028d907cb665d2a8028f707259514a1818c9 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 3 Feb 2021 20:57:54 -0500 Subject: [PATCH 2/4] fixup! Remove chisel3.stage.phases.DriverCompatibility Signed-off-by: Schuyler Eldridge --- src/main/scala/chisel3/stage/phases/DriverCompatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala index f07d6c4a818..4245d6e4f0b 100644 --- a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala +++ b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala @@ -16,5 +16,5 @@ import chisel3.stage.{ChiselStage, NoRunFirrtlCompilerAnnotation, ChiselOutputFi * Primarily, this object includes [[firrtl.options.Phase Phase]]s that generate [[firrtl.annotations.Annotation]]s * derived from the deprecated [[firrtl.stage.phases.DriverCompatibility.TopNameAnnotation]]. */ -@deprecated("This object contains no public members. This will be removed in FIRRTL 1.5.", "FIRRTL 1.5") +@deprecated("This object contains no public members. This will be removed in Chisel 3.6.", "FIRRTL 3.4.3") object DriverCompatibility From ef3d74cbb9545bce55f47706e5a2a617c50fce18 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 3 Feb 2021 21:05:46 -0500 Subject: [PATCH 3/4] fixup! Remove chisel3.stage.phases.DriverCompatibility --- src/main/scala/chisel3/stage/phases/DriverCompatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala index 4245d6e4f0b..34d7bb9589c 100644 --- a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala +++ b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala @@ -16,5 +16,5 @@ import chisel3.stage.{ChiselStage, NoRunFirrtlCompilerAnnotation, ChiselOutputFi * Primarily, this object includes [[firrtl.options.Phase Phase]]s that generate [[firrtl.annotations.Annotation]]s * derived from the deprecated [[firrtl.stage.phases.DriverCompatibility.TopNameAnnotation]]. */ -@deprecated("This object contains no public members. This will be removed in Chisel 3.6.", "FIRRTL 3.4.3") +@deprecated("This object contains no public members. This will be removed in Chisel 3.6.", "FIRRTL 3.5") object DriverCompatibility From f06c1b8b5c2c92003671e3ab42dea764a88e2ac3 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 3 Feb 2021 20:34:50 -0800 Subject: [PATCH 4/4] Update src/main/scala/chisel3/stage/phases/DriverCompatibility.scala --- src/main/scala/chisel3/stage/phases/DriverCompatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala index 34d7bb9589c..9305c5c95af 100644 --- a/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala +++ b/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala @@ -16,5 +16,5 @@ import chisel3.stage.{ChiselStage, NoRunFirrtlCompilerAnnotation, ChiselOutputFi * Primarily, this object includes [[firrtl.options.Phase Phase]]s that generate [[firrtl.annotations.Annotation]]s * derived from the deprecated [[firrtl.stage.phases.DriverCompatibility.TopNameAnnotation]]. */ -@deprecated("This object contains no public members. This will be removed in Chisel 3.6.", "FIRRTL 3.5") +@deprecated("This object contains no public members. This will be removed in Chisel 3.6.", "Chisel 3.5") object DriverCompatibility