From f7f1495d899e0d6847e69ec3026822d286a00405 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Date: Sat, 21 Mar 2020 16:04:34 -0400
Subject: [PATCH] Set StageError cause in ChiselStage

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 src/main/scala/chisel3/stage/ChiselStage.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 99484425474..eb90c1b6e2b 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -44,7 +44,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
         .augmentString(stackTrace)
         .lines
         .foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex
-      throw new StageError()
+      throw new StageError(cause=ce)
   }
 
 }