diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala
index a687c4cdcef..ec15e23abc0 100644
--- a/src/main/scala/chisel3/util/MixedVec.scala
+++ b/src/main/scala/chisel3/util/MixedVec.scala
@@ -24,6 +24,13 @@ object MixedVecInit {
     }
     hetVecWire
   }
+
+  /**
+    * Construct a new wire with the given bound values.
+    * This is analogous to [[chisel3.core.VecInit]].
+    * @return MixedVec with given values assigned
+    */
+  def apply[T <: Data](val0: T, vals: T*): MixedVec[T] = apply(val0 +: vals.toSeq)
 }
 
 object MixedVec {
@@ -34,6 +41,19 @@ object MixedVec {
     */
   def apply[T <: Data](eltsIn: Seq[T]): MixedVec[T] = new MixedVec(eltsIn)
 
+  /**
+    * Create a MixedVec from that holds the given types.
+    * The types passed to this constructor must be Chisel types.
+    * @return MixedVec with the given types.
+    */
+  def apply[T <: Data](val0: T, vals: T*): MixedVec[T] = new MixedVec(val0 +: vals.toSeq)
+
+  /**
+    * Create a new MixedVec from an unbound MixedVec type.
+    * @return MixedVec with the given types.
+    */
+  def apply[T <: Data](mixedVec: MixedVec[T]): MixedVec[T] = new MixedVec(mixedVec.elts)
+
   /**
     * Create a MixedVec from the type of the given Vec.
     * For example, given a Vec(2, UInt(8.W)), this creates MixedVec(Seq.fill(2){UInt(8.W)}).
diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala
index 271467aacbe..0e4cc3e7db9 100644
--- a/src/test/scala/chiselTests/MixedVecSpec.scala
+++ b/src/test/scala/chiselTests/MixedVecSpec.scala
@@ -159,6 +159,25 @@ class MixedVecSpec extends ChiselPropSpec {
   implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
   implicit val noShrinkInt = Shrink[Int](_ => Stream.empty)
 
+  property("MixedVec varargs API should work") {
+    assertTesterPasses {
+      new BasicTester {
+        val wire = Wire(MixedVec(UInt(1.W), UInt(8.W)))
+        wire(0) := 1.U
+        wire(1) := 101.U
+
+        chisel3.assert(wire(0) === 1.U)
+        chisel3.assert(wire(1) + 1.U === 102.U)
+
+        val wireInit = MixedVecInit(1.U, 101.U)
+        chisel3.assert(wireInit(0) === 1.U)
+        chisel3.assert(wireInit(1) + 1.U === 102.U)
+
+        stop()
+      }
+    }
+  }
+
   property("MixedVecs should be assignable") {
     forAll(safeUIntN(8)) { case (w: Int, v: List[Int]) =>
       assertTesterPasses {