diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index abb15f9cc99e..514d958c6361 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -257,12 +257,7 @@
       (is_signed bool)
       (in_type Type)
       (out_type Type))
-    (SelectIf
-      (if_spectre_guard bool)
-      (rd VecWritableReg)
-      (test Reg)
-      (x ValueRegs)
-      (y ValueRegs))
+
     (RawData (data VecU8))
 
     ;; An unwind pseudo-instruction.
@@ -872,6 +867,12 @@
 (rule (rv_sltu rs1 rs2)
   (alu_rrr (AluOPRRR.SltU) rs1 rs2))
 
+;; Helper for emitting the `snez` instruction.
+;; This instruction is a mnemonic for `sltu rd, zero, rs`.
+(decl rv_snez (Reg) Reg)
+(rule (rv_snez rs1)
+  (rv_sltu (zero_reg) rs1))
+
 ;; Helper for emiting the `sltiu` ("Set Less Than Immediate Unsigned") instruction.
 ;; rd ← rs1 < imm
 (decl rv_sltiu (Reg Imm12) Reg)
@@ -1371,15 +1372,35 @@
 (rule (select_addi (fits_in_64 ty)) (AluOPRRI.Addi))
 
 
-(decl bnot_128 (ValueRegs) ValueRegs)
-(rule
-  (bnot_128 val)
-  (let
-    (;; low part.
-      (low Reg (rv_not (value_regs_get val 0)))
-      ;; high part.
-      (high Reg (rv_not (value_regs_get val 1))))
-    (value_regs low high)))
+(decl gen_bnot (Type ValueRegs) ValueRegs)
+(rule 1 (gen_bnot $I128 x)
+  (let ((lo Reg (rv_not (value_regs_get x 0)))
+        (hi Reg (rv_not (value_regs_get x 1))))
+    (value_regs lo hi)))
+
+(rule 0 (gen_bnot (fits_in_64 _) x)
+  (rv_not x))
+
+
+(decl gen_and (Type ValueRegs ValueRegs) ValueRegs)
+(rule 1 (gen_and $I128 x y)
+  (value_regs
+    (rv_and (value_regs_get x 0) (value_regs_get y 0))
+    (rv_and (value_regs_get x 1) (value_regs_get y 1))))
+
+(rule 0 (gen_and (fits_in_64 _) x y)
+  (rv_and (value_regs_get x 0) (value_regs_get y 0)))
+
+
+(decl gen_or (Type ValueRegs ValueRegs) ValueRegs)
+(rule 1 (gen_or $I128 x y)
+  (value_regs
+    (rv_or (value_regs_get x 0) (value_regs_get y 0))
+    (rv_or (value_regs_get x 1) (value_regs_get y 1))))
+
+(rule 0 (gen_or (fits_in_64 _) x y)
+  (rv_or (value_regs_get x 0) (value_regs_get y 0)))
+
 
 (decl lower_bit_reverse (Reg Type) Reg)
 
@@ -2511,9 +2532,8 @@
   0
   (lower_bmask (fits_in_64 _) (fits_in_64 in_ty) val)
   (let ((input Reg (normalize_cmp_value in_ty val (ExtendOp.Zero)))
-        (zero Reg (zero_reg))
-        (ones Reg (load_imm12 -1)))
-  (value_reg (gen_select_reg (IntCC.Equal) zero input zero ones))))
+        (non_zero Reg (rv_snez input)))
+    (value_reg (rv_neg non_zero))))
 
 ;; Bitwise-or the two registers that make up the 128-bit value, then recurse as
 ;; though it was a 64-bit value.
diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
index 0db271046b45..eb90867ae243 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -1864,48 +1864,6 @@ impl MachInstEmit for Inst {
                 }
                 sink.put_data(Inst::TRAP_OPCODE);
             }
-            &Inst::SelectIf {
-                if_spectre_guard: _if_spectre_guard, // _if_spectre_guard not use because it is used to not be removed by optimization pass and some other staff.
-                ref rd,
-                test,
-                ref x,
-                ref y,
-            } => {
-                let label_select_x = sink.get_label();
-                let label_select_y = sink.get_label();
-                let label_jump_over = sink.get_label();
-                let test = allocs.next(test);
-                let x = alloc_value_regs(x, &mut allocs);
-                let y = alloc_value_regs(y, &mut allocs);
-                let rd: Vec<_> = rd.iter().map(|r| allocs.next_writable(*r)).collect();
-                Inst::CondBr {
-                    taken: BranchTarget::Label(label_select_x),
-                    not_taken: BranchTarget::Label(label_select_y),
-                    kind: IntegerCompare {
-                        kind: IntCC::NotEqual,
-                        rs1: test,
-                        rs2: zero_reg(),
-                    },
-                }
-                .emit(&[], sink, emit_info, state);
-
-                // here select x.
-                sink.bind_label(label_select_x, &mut state.ctrl_plane);
-                gen_moves(&rd[..], x.regs())
-                    .into_iter()
-                    .for_each(|i| i.emit(&[], sink, emit_info, state));
-                // jump over
-                Inst::Jal {
-                    dest: BranchTarget::Label(label_jump_over),
-                }
-                .emit(&[], sink, emit_info, state);
-                // here select y.
-                sink.bind_label(label_select_y, &mut state.ctrl_plane);
-                gen_moves(&rd[..], y.regs())
-                    .into_iter()
-                    .for_each(|i| i.emit(&[], sink, emit_info, state));
-                sink.bind_label(label_jump_over, &mut state.ctrl_plane);
-            }
             &Inst::AtomicLoad { rd, ty, p } => {
                 let p = allocs.next(p);
                 let rd = allocs.next_writable(rd);
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
index e62be595f031..ea61641da3bb 100644
--- a/cranelift/codegen/src/isa/riscv64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -526,18 +526,6 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
             collector.reg_early_def(tmp);
             collector.reg_early_def(rd);
         }
-        &Inst::SelectIf {
-            ref rd,
-            test,
-            ref x,
-            ref y,
-            ..
-        } => {
-            collector.reg_use(test);
-            collector.reg_uses(x.regs());
-            collector.reg_uses(y.regs());
-            rd.iter().for_each(|r| collector.reg_early_def(*r));
-        }
         &Inst::RawData { .. } => {}
         &Inst::AtomicStore { src, p, .. } => {
             collector.reg_use(src);
@@ -1012,31 +1000,6 @@ impl Inst {
                     rd, rs, tmp, tmp2, step, ty
                 )
             }
-            &Inst::SelectIf {
-                if_spectre_guard,
-                ref rd,
-                test,
-                ref x,
-                ref y,
-            } => {
-                let test = format_reg(test, allocs);
-                let x = format_regs(x.regs(), allocs);
-                let y = format_regs(y.regs(), allocs);
-                let rd: Vec<_> = rd.iter().map(|r| r.to_reg()).collect();
-                let rd = format_regs(&rd[..], allocs);
-                format!(
-                    "selectif{} {},{},{}##test={}",
-                    if if_spectre_guard {
-                        "_spectre_guard"
-                    } else {
-                        ""
-                    },
-                    rd,
-                    x,
-                    y,
-                    test
-                )
-            }
             &Inst::Popcnt {
                 sum,
                 step,
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
index 3bc08aa704a4..6559b75bc81b 100644
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -230,8 +230,8 @@
     (rv_remu x y)))
 
 ;;;; Rules for `and` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(rule -1 (lower (has_type (fits_in_64 (ty_int ty)) (band x y)))
-  (rv_and x y))
+(rule -1 (lower (has_type (ty_int ty) (band x y)))
+  (gen_and ty x y))
 
 ;; Special cases for when one operand is an immediate that fits in 12 bits.
 (rule 2 (lower (has_type (fits_in_64 (ty_int ty)) (band x (imm12_from_value y))))
@@ -240,9 +240,6 @@
 (rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (band (imm12_from_value x) y)))
   (rv_andi y x))
 
-(rule (lower (has_type $I128 (band x y)))
-  (lower_b128_binary (AluOPRRR.And) x y))
-
 (rule (lower (has_type $F32 (band x y)))
   (lower_float_binary (AluOPRRR.And) x y $F32))
 
@@ -277,8 +274,8 @@
 
 
 ;;;; Rules for `or` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(rule -1 (lower (has_type (fits_in_64 (ty_int ty)) (bor x y)))
-  (rv_or x y))
+(rule -1 (lower (has_type (ty_int ty) (bor x y)))
+  (gen_or ty x y))
 
 ;; Special cases for when one operand is an immediate that fits in 12 bits.
 (rule 2 (lower (has_type (fits_in_64 (ty_int ty)) (bor x (imm12_from_value y))))
@@ -287,9 +284,6 @@
 (rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (bor (imm12_from_value x) y)))
   (rv_ori y x))
 
-(rule (lower (has_type $I128 (bor x y)))
-  (lower_b128_binary (AluOPRRR.Or) x y))
-
 (rule (lower (has_type $F32 (bor x y)))
   (lower_float_binary (AluOPRRR.Or) x y $F32))
 
@@ -345,11 +339,8 @@
 
 
 ;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(rule -1 (lower (has_type (fits_in_64 (ty_int ty)) (bnot x)))
-  (rv_xori x (imm_from_neg_bits -1)))
-
-(rule (lower (has_type $I128 (bnot x)))
-  (bnot_128 x))
+(rule -1 (lower (has_type (ty_int ty) (bnot x)))
+  (gen_bnot ty x))
 
 (rule
   (lower (has_type $F32 (bnot x)))
@@ -927,17 +918,23 @@
 
 
 ;;;;;  Rules for `select_spectre_guard`;;;;;;;;;
-(rule
-  (lower (has_type r_ty (select_spectre_guard (icmp cc ca @ (value_type cty) cb) a b)))
-  (let
-    ((dst VecWritableReg (alloc_vec_writable r_ty))
-      (r Reg (lower_icmp cc ca cb cty))
-      (_ Unit (emit (MInst.SelectIf $true (vec_writable_clone dst) r a b))))
-    (vec_writable_to_regs dst)))
 
-(rule -1
-  (lower (has_type ty (select_spectre_guard c @ (value_type cty) x y)))
-  (gen_select ty (truthy_to_reg cty (normalize_cmp_value cty c (ExtendOp.Zero))) x y))
+;; SelectSpectreGuard is equivalent to Select, but we should not use a branch based
+;; lowering for it. Instead we use a conditional move based lowering.
+;;
+;; We don't have cmov's in RISC-V either, but we can emulate those using bitwise
+;; operations, which is what we do below.
+(rule (lower (has_type ty (select_spectre_guard cmp @ (value_type cmp_ty) x @ (value_type arg_ty) y)))
+  (let (;; Build a mask that is 0 or -1 depending on the input comparision value.
+        ;; `lower_bmask` handles normalizing the input.
+        (mask ValueRegs (lower_bmask arg_ty cmp_ty cmp))
+        ;; Using the mask above we can select either `x` or `y` by
+        ;; performing a bitwise `and` on both sides and then merging them
+        ;; together. We know that only the bits of one of the sides will be selected.
+        ;; TODO: We can use `andn` here if we have `Zbb`
+        (lhs ValueRegs (gen_and arg_ty x mask))
+        (rhs ValueRegs (gen_and arg_ty y (gen_bnot arg_ty mask))))
+    (gen_or arg_ty lhs rhs)))
 
 ;;;;;  Rules for `bmask`;;;;;;;;;
 (rule
diff --git a/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif b/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
index e802e74d8c2c..54573373b0bf 100644
--- a/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif
@@ -11,19 +11,16 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   li a2,-1
-;   select_reg a1,zero,a2##condition=(zero eq a0)
+;   sltu a2,zero,a0
+;   sub a1,zero,a2
 ;   mv a0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   or a0, a0, a1
-;   addi a2, zero, -1
-;   beq zero, a0, 0xc
-;   ori a1, a2, 0
-;   j 8
-;   ori a1, zero, 0
+;   snez a2, a0
+;   neg a1, a2
 ;   ori a0, a1, 0
 ;   ret
 
@@ -36,18 +33,15 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   li a2,-1
-;   select_reg a0,zero,a2##condition=(zero eq a0)
+;   sltu a2,zero,a0
+;   sub a0,zero,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   or a0, a0, a1
-;   addi a2, zero, -1
-;   beq zero, a0, 0xc
-;   ori a0, a2, 0
-;   j 8
-;   ori a0, zero, 0
+;   snez a2, a0
+;   neg a0, a2
 ;   ret
 
 function %bmask_i128_i32(i128) -> i32 {
@@ -59,18 +53,15 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   li a2,-1
-;   select_reg a0,zero,a2##condition=(zero eq a0)
+;   sltu a2,zero,a0
+;   sub a0,zero,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   or a0, a0, a1
-;   addi a2, zero, -1
-;   beq zero, a0, 0xc
-;   ori a0, a2, 0
-;   j 8
-;   ori a0, zero, 0
+;   snez a2, a0
+;   neg a0, a2
 ;   ret
 
 function %bmask_i128_i16(i128) -> i16 {
@@ -82,18 +73,15 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   li a2,-1
-;   select_reg a0,zero,a2##condition=(zero eq a0)
+;   sltu a2,zero,a0
+;   sub a0,zero,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   or a0, a0, a1
-;   addi a2, zero, -1
-;   beq zero, a0, 0xc
-;   ori a0, a2, 0
-;   j 8
-;   ori a0, zero, 0
+;   snez a2, a0
+;   neg a0, a2
 ;   ret
 
 function %bmask_i128_i8(i128) -> i8 {
@@ -105,18 +93,15 @@ block0(v0: i128):
 ; VCode:
 ; block0:
 ;   or a0,a0,a1
-;   li a2,-1
-;   select_reg a0,zero,a2##condition=(zero eq a0)
+;   sltu a2,zero,a0
+;   sub a0,zero,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   or a0, a0, a1
-;   addi a2, zero, -1
-;   beq zero, a0, 0xc
-;   ori a0, a2, 0
-;   j 8
-;   ori a0, zero, 0
+;   snez a2, a0
+;   neg a0, a2
 ;   ret
 
 function %bmask_i64_i128(i64) -> i128 {
@@ -127,18 +112,15 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,-1
-;   select_reg a1,zero,t2##condition=(zero eq a0)
+;   sltu t2,zero,a0
+;   sub a1,zero,t2
 ;   mv a0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, -1
-;   beq zero, a0, 0xc
-;   ori a1, t2, 0
-;   j 8
-;   ori a1, zero, 0
+;   snez t2, a0
+;   neg a1, t2
 ;   ori a0, a1, 0
 ;   ret
 
@@ -152,8 +134,8 @@ block0(v0: i32):
 ; block0:
 ;   slli t2,a0,32
 ;   srli a1,t2,32
-;   li a3,-1
-;   select_reg a1,zero,a3##condition=(zero eq a1)
+;   sltu a3,zero,a1
+;   sub a1,zero,a3
 ;   mv a0,a1
 ;   ret
 ; 
@@ -161,11 +143,8 @@ block0(v0: i32):
 ; block0: ; offset 0x0
 ;   slli t2, a0, 0x20
 ;   srli a1, t2, 0x20
-;   addi a3, zero, -1
-;   beq zero, a1, 0xc
-;   ori a1, a3, 0
-;   j 8
-;   ori a1, zero, 0
+;   snez a3, a1
+;   neg a1, a3
 ;   ori a0, a1, 0
 ;   ret
 
@@ -179,8 +158,8 @@ block0(v0: i16):
 ; block0:
 ;   slli t2,a0,48
 ;   srli a1,t2,48
-;   li a3,-1
-;   select_reg a1,zero,a3##condition=(zero eq a1)
+;   sltu a3,zero,a1
+;   sub a1,zero,a3
 ;   mv a0,a1
 ;   ret
 ; 
@@ -188,11 +167,8 @@ block0(v0: i16):
 ; block0: ; offset 0x0
 ;   slli t2, a0, 0x30
 ;   srli a1, t2, 0x30
-;   addi a3, zero, -1
-;   beq zero, a1, 0xc
-;   ori a1, a3, 0
-;   j 8
-;   ori a1, zero, 0
+;   snez a3, a1
+;   neg a1, a3
 ;   ori a0, a1, 0
 ;   ret
 
@@ -205,18 +181,16 @@ block0(v0: i8):
 ; VCode:
 ; block0:
 ;   andi t2,a0,255
-;   li a1,-1
-;   select_reg a1,zero,a1##condition=(zero eq t2)
+;   sltu a1,zero,t2
+;   sub a1,zero,a1
 ;   mv a0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   andi t2, a0, 0xff
-;   addi a1, zero, -1
-;   beq zero, t2, 8
-;   j 8
-;   ori a1, zero, 0
+;   snez a1, t2
+;   neg a1, a1
 ;   ori a0, a1, 0
 ;   ret
 
diff --git a/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif b/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
new file mode 100644
index 000000000000..cceaedf594bf
--- /dev/null
+++ b/cranelift/filetests/filetests/isa/riscv64/select_spectre_guard.clif
@@ -0,0 +1,1089 @@
+test compile precise-output
+set unwind_info=false
+target riscv64
+
+function %f(i8, i8, i8) -> i8 {
+block0(v0: i8, v1: i8, v2: i8):
+  v3 = iconst.i8 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i8 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li t1,42
+;   andi t4,a0,255
+;   andi t1,t1,255
+;   eq a0,t4,t1##ty=i8
+;   andi a5,a0,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a1,t4
+;   not a0,t4
+;   and a2,a2,a0
+;   or a0,t1,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t1, zero, 0x2a
+;   andi t4, a0, 0xff
+;   andi t1, t1, 0xff
+;   bne t4, t1, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   andi a5, a0, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a1, t4
+;   not a0, t4
+;   and a2, a2, a0
+;   or a0, t1, a2
+;   ret
+
+function %f(i8, i16, i16) -> i16 {
+block0(v0: i8, v1: i16, v2: i16):
+  v3 = iconst.i8 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i16 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li t1,42
+;   andi t4,a0,255
+;   andi t1,t1,255
+;   eq a0,t4,t1##ty=i8
+;   andi a5,a0,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a1,t4
+;   not a0,t4
+;   and a2,a2,a0
+;   or a0,t1,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t1, zero, 0x2a
+;   andi t4, a0, 0xff
+;   andi t1, t1, 0xff
+;   bne t4, t1, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   andi a5, a0, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a1, t4
+;   not a0, t4
+;   and a2, a2, a0
+;   or a0, t1, a2
+;   ret
+
+function %f(i8, i32, i32) -> i32 {
+block0(v0: i8, v1: i32, v2: i32):
+  v3 = iconst.i8 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i32 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li t1,42
+;   andi t4,a0,255
+;   andi t1,t1,255
+;   eq a0,t4,t1##ty=i8
+;   andi a5,a0,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a1,t4
+;   not a0,t4
+;   and a2,a2,a0
+;   or a0,t1,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t1, zero, 0x2a
+;   andi t4, a0, 0xff
+;   andi t1, t1, 0xff
+;   bne t4, t1, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   andi a5, a0, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a1, t4
+;   not a0, t4
+;   and a2, a2, a0
+;   or a0, t1, a2
+;   ret
+
+function %f(i8, i64, i64) -> i64 {
+block0(v0: i8, v1: i64, v2: i64):
+  v3 = iconst.i8 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i64 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li t1,42
+;   andi t4,a0,255
+;   andi t1,t1,255
+;   eq a0,t4,t1##ty=i8
+;   andi a5,a0,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a1,t4
+;   not a0,t4
+;   and a2,a2,a0
+;   or a0,t1,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t1, zero, 0x2a
+;   andi t4, a0, 0xff
+;   andi t1, t1, 0xff
+;   bne t4, t1, 0xc
+;   addi a0, zero, 1
+;   j 8
+;   mv a0, zero
+;   andi a5, a0, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a1, t4
+;   not a0, t4
+;   and a2, a2, a0
+;   or a0, t1, a2
+;   ret
+
+function %f(i8, i128, i128) -> i128 {
+block0(v0: i8, v1: i128, v2: i128):
+  v3 = iconst.i8 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i128 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a5,42
+;   andi a6,a0,255
+;   andi a5,a5,255
+;   eq a6,a6,a5##ty=i8
+;   andi a7,a6,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   and a2,a2,t1
+;   not a5,t1
+;   not a6,t1
+;   and t3,a3,a5
+;   and t0,a4,a6
+;   or a0,a0,t3
+;   or a1,a2,t0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a5, zero, 0x2a
+;   andi a6, a0, 0xff
+;   andi a5, a5, 0xff
+;   bne a6, a5, 0xc
+;   addi a6, zero, 1
+;   j 8
+;   mv a6, zero
+;   andi a7, a6, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   and a2, a2, t1
+;   not a5, t1
+;   not a6, t1
+;   and t3, a3, a5
+;   and t0, a4, a6
+;   or a0, a0, t3
+;   or a1, a2, t0
+;   ret
+
+function %f(i16, i8, i8) -> i8 {
+block0(v0: i16, v1: i8, v2: i8):
+  v3 = iconst.i16 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i8 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a3,42
+;   slli t4,a0,48
+;   srli t1,t4,48
+;   slli a0,a3,48
+;   srli a3,a0,48
+;   eq a4,t1,a3##ty=i16
+;   andi a7,a4,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   not a3,t1
+;   and a4,a2,a3
+;   or a0,a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 0x2a
+;   slli t4, a0, 0x30
+;   srli t1, t4, 0x30
+;   slli a0, a3, 0x30
+;   srli a3, a0, 0x30
+;   bne t1, a3, 0xc
+;   addi a4, zero, 1
+;   j 8
+;   mv a4, zero
+;   andi a7, a4, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   not a3, t1
+;   and a4, a2, a3
+;   or a0, a0, a4
+;   ret
+
+function %f(i16, i16, i16) -> i16 {
+block0(v0: i16, v1: i16, v2: i16):
+  v3 = iconst.i16 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i16 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a3,42
+;   slli t4,a0,48
+;   srli t1,t4,48
+;   slli a0,a3,48
+;   srli a3,a0,48
+;   eq a4,t1,a3##ty=i16
+;   andi a7,a4,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   not a3,t1
+;   and a4,a2,a3
+;   or a0,a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 0x2a
+;   slli t4, a0, 0x30
+;   srli t1, t4, 0x30
+;   slli a0, a3, 0x30
+;   srli a3, a0, 0x30
+;   bne t1, a3, 0xc
+;   addi a4, zero, 1
+;   j 8
+;   mv a4, zero
+;   andi a7, a4, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   not a3, t1
+;   and a4, a2, a3
+;   or a0, a0, a4
+;   ret
+
+function %f(i16, i32, i32) -> i32 {
+block0(v0: i16, v1: i32, v2: i32):
+  v3 = iconst.i16 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i32 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a3,42
+;   slli t4,a0,48
+;   srli t1,t4,48
+;   slli a0,a3,48
+;   srli a3,a0,48
+;   eq a4,t1,a3##ty=i16
+;   andi a7,a4,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   not a3,t1
+;   and a4,a2,a3
+;   or a0,a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 0x2a
+;   slli t4, a0, 0x30
+;   srli t1, t4, 0x30
+;   slli a0, a3, 0x30
+;   srli a3, a0, 0x30
+;   bne t1, a3, 0xc
+;   addi a4, zero, 1
+;   j 8
+;   mv a4, zero
+;   andi a7, a4, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   not a3, t1
+;   and a4, a2, a3
+;   or a0, a0, a4
+;   ret
+
+function %f(i16, i64, i64) -> i64 {
+block0(v0: i16, v1: i64, v2: i64):
+  v3 = iconst.i16 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i64 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a3,42
+;   slli t4,a0,48
+;   srli t1,t4,48
+;   slli a0,a3,48
+;   srli a3,a0,48
+;   eq a4,t1,a3##ty=i16
+;   andi a7,a4,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   not a3,t1
+;   and a4,a2,a3
+;   or a0,a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 0x2a
+;   slli t4, a0, 0x30
+;   srli t1, t4, 0x30
+;   slli a0, a3, 0x30
+;   srli a3, a0, 0x30
+;   bne t1, a3, 0xc
+;   addi a4, zero, 1
+;   j 8
+;   mv a4, zero
+;   andi a7, a4, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   not a3, t1
+;   and a4, a2, a3
+;   or a0, a0, a4
+;   ret
+
+function %f(i16, i128, i128) -> i128 {
+block0(v0: i16, v1: i128, v2: i128):
+  v3 = iconst.i16 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i128 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a6,42
+;   slli a5,a0,48
+;   srli a5,a5,48
+;   slli a6,a6,48
+;   srli t3,a6,48
+;   eq t0,a5,t3##ty=i16
+;   andi t4,t0,255
+;   sltu t1,zero,t4
+;   sub a0,zero,t1
+;   and a6,a1,a0
+;   and a5,a2,a0
+;   not a7,a0
+;   not t3,a0
+;   and t0,a3,a7
+;   and t2,a4,t3
+;   or a0,a6,t0
+;   or a1,a5,t2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a6, zero, 0x2a
+;   slli a5, a0, 0x30
+;   srli a5, a5, 0x30
+;   slli a6, a6, 0x30
+;   srli t3, a6, 0x30
+;   bne a5, t3, 0xc
+;   addi t0, zero, 1
+;   j 8
+;   mv t0, zero
+;   andi t4, t0, 0xff
+;   snez t1, t4
+;   neg a0, t1
+;   and a6, a1, a0
+;   and a5, a2, a0
+;   not a7, a0
+;   not t3, a0
+;   and t0, a3, a7
+;   and t2, a4, t3
+;   or a0, a6, t0
+;   or a1, a5, t2
+;   ret
+
+function %f(i32, i8, i8) -> i8 {
+block0(v0: i32, v1: i8, v2: i8):
+  v3 = iconst.i32 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i8 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a3,42
+;   slli t4,a0,32
+;   srli t1,t4,32
+;   slli a0,a3,32
+;   srli a3,a0,32
+;   eq a4,t1,a3##ty=i32
+;   andi a7,a4,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   not a3,t1
+;   and a4,a2,a3
+;   or a0,a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 0x2a
+;   slli t4, a0, 0x20
+;   srli t1, t4, 0x20
+;   slli a0, a3, 0x20
+;   srli a3, a0, 0x20
+;   bne t1, a3, 0xc
+;   addi a4, zero, 1
+;   j 8
+;   mv a4, zero
+;   andi a7, a4, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   not a3, t1
+;   and a4, a2, a3
+;   or a0, a0, a4
+;   ret
+
+function %f(i32, i16, i16) -> i16 {
+block0(v0: i32, v1: i16, v2: i16):
+  v3 = iconst.i32 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i16 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a3,42
+;   slli t4,a0,32
+;   srli t1,t4,32
+;   slli a0,a3,32
+;   srli a3,a0,32
+;   eq a4,t1,a3##ty=i32
+;   andi a7,a4,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   not a3,t1
+;   and a4,a2,a3
+;   or a0,a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 0x2a
+;   slli t4, a0, 0x20
+;   srli t1, t4, 0x20
+;   slli a0, a3, 0x20
+;   srli a3, a0, 0x20
+;   bne t1, a3, 0xc
+;   addi a4, zero, 1
+;   j 8
+;   mv a4, zero
+;   andi a7, a4, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   not a3, t1
+;   and a4, a2, a3
+;   or a0, a0, a4
+;   ret
+
+function %f(i32, i32, i32) -> i32 {
+block0(v0: i32, v1: i32, v2: i32):
+  v3 = iconst.i32 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i32 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a3,42
+;   slli t4,a0,32
+;   srli t1,t4,32
+;   slli a0,a3,32
+;   srli a3,a0,32
+;   eq a4,t1,a3##ty=i32
+;   andi a7,a4,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   not a3,t1
+;   and a4,a2,a3
+;   or a0,a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 0x2a
+;   slli t4, a0, 0x20
+;   srli t1, t4, 0x20
+;   slli a0, a3, 0x20
+;   srli a3, a0, 0x20
+;   bne t1, a3, 0xc
+;   addi a4, zero, 1
+;   j 8
+;   mv a4, zero
+;   andi a7, a4, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   not a3, t1
+;   and a4, a2, a3
+;   or a0, a0, a4
+;   ret
+
+function %f(i32, i64, i64) -> i64 {
+block0(v0: i32, v1: i64, v2: i64):
+  v3 = iconst.i32 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i64 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a3,42
+;   slli t4,a0,32
+;   srli t1,t4,32
+;   slli a0,a3,32
+;   srli a3,a0,32
+;   eq a4,t1,a3##ty=i32
+;   andi a7,a4,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a1,t1
+;   not a3,t1
+;   and a4,a2,a3
+;   or a0,a0,a4
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a3, zero, 0x2a
+;   slli t4, a0, 0x20
+;   srli t1, t4, 0x20
+;   slli a0, a3, 0x20
+;   srli a3, a0, 0x20
+;   bne t1, a3, 0xc
+;   addi a4, zero, 1
+;   j 8
+;   mv a4, zero
+;   andi a7, a4, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a1, t1
+;   not a3, t1
+;   and a4, a2, a3
+;   or a0, a0, a4
+;   ret
+
+function %f(i32, i128, i128) -> i128 {
+block0(v0: i32, v1: i128, v2: i128):
+  v3 = iconst.i32 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i128 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a6,42
+;   slli a5,a0,32
+;   srli a5,a5,32
+;   slli a6,a6,32
+;   srli t3,a6,32
+;   eq t0,a5,t3##ty=i32
+;   andi t4,t0,255
+;   sltu t1,zero,t4
+;   sub a0,zero,t1
+;   and a6,a1,a0
+;   and a5,a2,a0
+;   not a7,a0
+;   not t3,a0
+;   and t0,a3,a7
+;   and t2,a4,t3
+;   or a0,a6,t0
+;   or a1,a5,t2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a6, zero, 0x2a
+;   slli a5, a0, 0x20
+;   srli a5, a5, 0x20
+;   slli a6, a6, 0x20
+;   srli t3, a6, 0x20
+;   bne a5, t3, 0xc
+;   addi t0, zero, 1
+;   j 8
+;   mv t0, zero
+;   andi t4, t0, 0xff
+;   snez t1, t4
+;   neg a0, t1
+;   and a6, a1, a0
+;   and a5, a2, a0
+;   not a7, a0
+;   not t3, a0
+;   and t0, a3, a7
+;   and t2, a4, t3
+;   or a0, a6, t0
+;   or a1, a5, t2
+;   ret
+
+function %f(i64, i8, i8) -> i8 {
+block0(v0: i64, v1: i8, v2: i8):
+  v3 = iconst.i64 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i8 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li t4,42
+;   eq t4,a0,t4##ty=i64
+;   andi a3,t4,255
+;   sltu a5,zero,a3
+;   sub a7,zero,a5
+;   and t4,a1,a7
+;   not t1,a7
+;   and a0,a2,t1
+;   or a0,t4,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t4, zero, 0x2a
+;   bne a0, t4, 0xc
+;   addi t4, zero, 1
+;   j 8
+;   mv t4, zero
+;   andi a3, t4, 0xff
+;   snez a5, a3
+;   neg a7, a5
+;   and t4, a1, a7
+;   not t1, a7
+;   and a0, a2, t1
+;   or a0, t4, a0
+;   ret
+
+function %f(i64, i16, i16) -> i16 {
+block0(v0: i64, v1: i16, v2: i16):
+  v3 = iconst.i64 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i16 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li t4,42
+;   eq t4,a0,t4##ty=i64
+;   andi a3,t4,255
+;   sltu a5,zero,a3
+;   sub a7,zero,a5
+;   and t4,a1,a7
+;   not t1,a7
+;   and a0,a2,t1
+;   or a0,t4,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t4, zero, 0x2a
+;   bne a0, t4, 0xc
+;   addi t4, zero, 1
+;   j 8
+;   mv t4, zero
+;   andi a3, t4, 0xff
+;   snez a5, a3
+;   neg a7, a5
+;   and t4, a1, a7
+;   not t1, a7
+;   and a0, a2, t1
+;   or a0, t4, a0
+;   ret
+
+function %f(i64, i32, i32) -> i32 {
+block0(v0: i64, v1: i32, v2: i32):
+  v3 = iconst.i64 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i32 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li t4,42
+;   eq t4,a0,t4##ty=i64
+;   andi a3,t4,255
+;   sltu a5,zero,a3
+;   sub a7,zero,a5
+;   and t4,a1,a7
+;   not t1,a7
+;   and a0,a2,t1
+;   or a0,t4,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t4, zero, 0x2a
+;   bne a0, t4, 0xc
+;   addi t4, zero, 1
+;   j 8
+;   mv t4, zero
+;   andi a3, t4, 0xff
+;   snez a5, a3
+;   neg a7, a5
+;   and t4, a1, a7
+;   not t1, a7
+;   and a0, a2, t1
+;   or a0, t4, a0
+;   ret
+
+function %f(i64, i64, i64) -> i64 {
+block0(v0: i64, v1: i64, v2: i64):
+  v3 = iconst.i64 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i64 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li t4,42
+;   eq t4,a0,t4##ty=i64
+;   andi a3,t4,255
+;   sltu a5,zero,a3
+;   sub a7,zero,a5
+;   and t4,a1,a7
+;   not t1,a7
+;   and a0,a2,t1
+;   or a0,t4,a0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t4, zero, 0x2a
+;   bne a0, t4, 0xc
+;   addi t4, zero, 1
+;   j 8
+;   mv t4, zero
+;   andi a3, t4, 0xff
+;   snez a5, a3
+;   neg a7, a5
+;   and t4, a1, a7
+;   not t1, a7
+;   and a0, a2, t1
+;   or a0, t4, a0
+;   ret
+
+function %f(i64, i128, i128) -> i128 {
+block0(v0: i64, v1: i128, v2: i128):
+  v3 = iconst.i64 42
+  v4 = icmp eq v0, v3
+  v5 = select_spectre_guard.i128 v4, v1, v2
+  return v5
+}
+
+; VCode:
+; block0:
+;   li a5,42
+;   eq a5,a0,a5##ty=i64
+;   andi a5,a5,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a1,t4
+;   and a1,a2,t4
+;   not a2,t4
+;   not a5,t4
+;   and a6,a3,a2
+;   and t3,a4,a5
+;   or a0,t1,a6
+;   or a1,a1,t3
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a5, zero, 0x2a
+;   bne a0, a5, 0xc
+;   addi a5, zero, 1
+;   j 8
+;   mv a5, zero
+;   andi a5, a5, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a1, t4
+;   and a1, a2, t4
+;   not a2, t4
+;   not a5, t4
+;   and a6, a3, a2
+;   and t3, a4, a5
+;   or a0, t1, a6
+;   or a1, a1, t3
+;   ret
+
+function %f(i128, i8, i8) -> i8 {
+block0(v0: i128, v1: i8, v2: i8):
+  v3 = iconst.i64 42
+  v4 = uextend.i128 v3
+  v5 = icmp eq v0, v4
+  v6 = select_spectre_guard.i8 v5, v1, v2
+  return v6
+}
+
+; VCode:
+; block0:
+;   li t1,42
+;   li t2,0
+;   eq t1,[a0,a1],[t1,t2]##ty=i128
+;   andi a5,t1,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a2,t4
+;   not a0,t4
+;   and a2,a3,a0
+;   or a0,t1,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t1, zero, 0x2a
+;   mv t2, zero
+;   bne a1, t2, 0x10
+;   bne a0, t1, 0xc
+;   addi t1, zero, 1
+;   j 8
+;   mv t1, zero
+;   andi a5, t1, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a2, t4
+;   not a0, t4
+;   and a2, a3, a0
+;   or a0, t1, a2
+;   ret
+
+function %f(i128, i16, i16) -> i16 {
+block0(v0: i128, v1: i16, v2: i16):
+  v3 = iconst.i64 42
+  v4 = uextend.i128 v3
+  v5 = icmp eq v0, v4
+  v6 = select_spectre_guard.i16 v5, v1, v2
+  return v6
+}
+
+; VCode:
+; block0:
+;   li t1,42
+;   li t2,0
+;   eq t1,[a0,a1],[t1,t2]##ty=i128
+;   andi a5,t1,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a2,t4
+;   not a0,t4
+;   and a2,a3,a0
+;   or a0,t1,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t1, zero, 0x2a
+;   mv t2, zero
+;   bne a1, t2, 0x10
+;   bne a0, t1, 0xc
+;   addi t1, zero, 1
+;   j 8
+;   mv t1, zero
+;   andi a5, t1, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a2, t4
+;   not a0, t4
+;   and a2, a3, a0
+;   or a0, t1, a2
+;   ret
+
+function %f(i128, i32, i32) -> i32 {
+block0(v0: i128, v1: i32, v2: i32):
+  v3 = iconst.i64 42
+  v4 = uextend.i128 v3
+  v5 = icmp eq v0, v4
+  v6 = select_spectre_guard.i32 v5, v1, v2
+  return v6
+}
+
+; VCode:
+; block0:
+;   li t1,42
+;   li t2,0
+;   eq t1,[a0,a1],[t1,t2]##ty=i128
+;   andi a5,t1,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a2,t4
+;   not a0,t4
+;   and a2,a3,a0
+;   or a0,t1,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t1, zero, 0x2a
+;   mv t2, zero
+;   bne a1, t2, 0x10
+;   bne a0, t1, 0xc
+;   addi t1, zero, 1
+;   j 8
+;   mv t1, zero
+;   andi a5, t1, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a2, t4
+;   not a0, t4
+;   and a2, a3, a0
+;   or a0, t1, a2
+;   ret
+
+function %f(i128, i64, i64) -> i64 {
+block0(v0: i128, v1: i64, v2: i64):
+  v3 = iconst.i64 42
+  v4 = uextend.i128 v3
+  v5 = icmp eq v0, v4
+  v6 = select_spectre_guard.i64 v5, v1, v2
+  return v6
+}
+
+; VCode:
+; block0:
+;   li t1,42
+;   li t2,0
+;   eq t1,[a0,a1],[t1,t2]##ty=i128
+;   andi a5,t1,255
+;   sltu a7,zero,a5
+;   sub t4,zero,a7
+;   and t1,a2,t4
+;   not a0,t4
+;   and a2,a3,a0
+;   or a0,t1,a2
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi t1, zero, 0x2a
+;   mv t2, zero
+;   bne a1, t2, 0x10
+;   bne a0, t1, 0xc
+;   addi t1, zero, 1
+;   j 8
+;   mv t1, zero
+;   andi a5, t1, 0xff
+;   snez a7, a5
+;   neg t4, a7
+;   and t1, a2, t4
+;   not a0, t4
+;   and a2, a3, a0
+;   or a0, t1, a2
+;   ret
+
+function %f(i128, i128, i128) -> i128 {
+block0(v0: i128, v1: i128, v2: i128):
+  v3 = iconst.i64 42
+  v4 = uextend.i128 v3
+  v5 = icmp eq v0, v4
+  v6 = select_spectre_guard.i128 v5, v1, v2
+  return v6
+}
+
+; VCode:
+; block0:
+;   li a6,42
+;   li a7,0
+;   eq a6,[a0,a1],[a6,a7]##ty=i128
+;   andi a7,a6,255
+;   sltu t4,zero,a7
+;   sub t1,zero,t4
+;   and a0,a2,t1
+;   and a2,a3,t1
+;   not a7,t1
+;   not a6,t1
+;   and t3,a4,a7
+;   and t0,a5,a6
+;   or a0,a0,t3
+;   or a1,a2,t0
+;   ret
+; 
+; Disassembled:
+; block0: ; offset 0x0
+;   addi a6, zero, 0x2a
+;   mv a7, zero
+;   bne a1, a7, 0x10
+;   bne a0, a6, 0xc
+;   addi a6, zero, 1
+;   j 8
+;   mv a6, zero
+;   andi a7, a6, 0xff
+;   snez t4, a7
+;   neg t1, t4
+;   and a0, a2, t1
+;   and a2, a3, t1
+;   not a7, t1
+;   not a6, t1
+;   and t3, a4, a7
+;   and t0, a5, a6
+;   or a0, a0, t3
+;   or a1, a2, t0
+;   ret
+
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 3e5fda406a2f..67f77c562caf 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,32 +41,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t3,a0,32
-;;   srli t0,t3,32
-;;   ld t4,8(a2)
-;;   addi t4,t4,-4
-;;   ld t1,0(a2)
-;;   add t1,t1,t0
-;;   li t2,0
-;;   ugt t4,t0,t4##ty=i64
-;;   selectif_spectre_guard t0,t2,t1##test=t4
-;;   sw a1,0(t0)
+;;   slli a3,a0,32
+;;   srli a3,a3,32
+;;   ld a4,8(a2)
+;;   addi a4,a4,-4
+;;   ugt a4,a3,a4##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sw a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t3,a0,32
-;;   srli t0,t3,32
-;;   ld t4,8(a1)
-;;   addi t4,t4,-4
-;;   ld t1,0(a1)
-;;   add t1,t1,t0
-;;   li t2,0
-;;   ugt t4,t0,t4##ty=i64
-;;   selectif_spectre_guard t0,t2,t1##test=t4
-;;   lw a0,0(t0)
+;;   slli a2,a0,32
+;;   srli a3,a2,32
+;;   ld a2,8(a1)
+;;   addi a2,a2,-4
+;;   ugt a4,a3,a2##ty=i64
+;;   ld a2,0(a1)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lw a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 79bda6806405..cb9f3b4a1435 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -41,40 +41,52 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t2,a0,32
-;;   srli a3,t2,32
-;;   ld a0,8(a2)
-;;   lui a4,1048575
-;;   addi a4,a4,4092
-;;   add a0,a0,a4
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   lui a4,1
-;;   add a2,a2,a4
-;;   li a4,0
-;;   ugt a0,a3,a0##ty=i64
-;;   selectif_spectre_guard a3,a4,a2##test=a0
-;;   sw a1,0(a3)
+;;   slli a5,a0,32
+;;   srli a7,a5,32
+;;   ld a6,8(a2)
+;;   lui t3,1048575
+;;   addi t3,t3,4092
+;;   add a6,a6,t3
+;;   ugt t3,a7,a6##ty=i64
+;;   ld a6,0(a2)
+;;   add a6,a6,a7
+;;   lui a7,1
+;;   add a6,a6,a7
+;;   li a7,0
+;;   andi a0,t3,255
+;;   sltu a2,zero,a0
+;;   sub a4,zero,a2
+;;   and a7,a7,a4
+;;   not t3,a4
+;;   and t0,a6,t3
+;;   or t2,a7,t0
+;;   sw a1,0(t2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t2,a0,32
-;;   srli a2,t2,32
-;;   ld a0,8(a1)
-;;   lui a3,1048575
-;;   addi a3,a3,4092
-;;   add a0,a0,a3
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   lui a3,1
-;;   add a1,a1,a3
-;;   li a3,0
-;;   ugt a0,a2,a0##ty=i64
-;;   selectif_spectre_guard a2,a3,a1##test=a0
-;;   lw a0,0(a2)
+;;   slli a5,a0,32
+;;   srli a7,a5,32
+;;   ld a6,8(a1)
+;;   lui t3,1048575
+;;   addi t3,t3,4092
+;;   add a6,a6,t3
+;;   ugt t3,a7,a6##ty=i64
+;;   ld a6,0(a1)
+;;   add a6,a6,a7
+;;   lui a7,1
+;;   add a6,a6,a7
+;;   li a7,0
+;;   andi a0,t3,255
+;;   sltu a2,zero,a0
+;;   sub a4,zero,a2
+;;   and a7,a7,a4
+;;   not t3,a4
+;;   and t0,a6,t3
+;;   or t2,a7,t0
+;;   lw a0,0(t2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index c6e94565290f..bb494a2e0f56 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,42 +41,54 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t2,a0,32
-;;   srli a3,t2,32
-;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0004
-;;   add t2,a3,a0
-;;   ult a4,t2,a3##ty=i64
-;;   trap_if a4,heap_oob
-;;   ld a4,8(a2)
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
-;;   add a2,a2,a3
-;;   li a3,0
-;;   ugt a4,t2,a4##ty=i64
-;;   selectif_spectre_guard a5,a3,a2##test=a4
-;;   sw a1,0(a5)
+;;   slli a5,a0,32
+;;   srli a7,a5,32
+;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0004
+;;   add a5,a7,a6
+;;   ult t3,a5,a7##ty=i64
+;;   trap_if t3,heap_oob
+;;   ld t3,8(a2)
+;;   ugt t3,a5,t3##ty=i64
+;;   ld t4,0(a2)
+;;   add a7,t4,a7
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
+;;   add a7,a7,t4
+;;   li t4,0
+;;   andi a2,t3,255
+;;   sltu a3,zero,a2
+;;   sub a5,zero,a3
+;;   and t3,t4,a5
+;;   not t4,a5
+;;   and t1,a7,t4
+;;   or a0,t3,t1
+;;   sw a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t2,a0,32
-;;   srli a2,t2,32
-;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0004
-;;   add t2,a2,a0
-;;   ult a3,t2,a2##ty=i64
-;;   trap_if a3,heap_oob
-;;   ld a3,8(a1)
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
-;;   add a1,a1,a2
-;;   li a2,0
-;;   ugt a3,t2,a3##ty=i64
-;;   selectif_spectre_guard a4,a2,a1##test=a3
-;;   lw a0,0(a4)
+;;   slli a5,a0,32
+;;   srli a7,a5,32
+;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0004
+;;   add a5,a7,a6
+;;   ult t3,a5,a7##ty=i64
+;;   trap_if t3,heap_oob
+;;   ld t3,8(a1)
+;;   ugt t3,a5,t3##ty=i64
+;;   ld t4,0(a1)
+;;   add a7,t4,a7
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
+;;   add a7,a7,t4
+;;   li t4,0
+;;   andi a1,t3,255
+;;   sltu a3,zero,a1
+;;   sub a5,zero,a3
+;;   and t3,t4,a5
+;;   not t4,a5
+;;   and t1,a7,t4
+;;   or a0,t3,t1
+;;   lw a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 2f91d75f152f..b9d0fdcb5c99 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,30 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a7,a0,32
-;;   srli t4,a7,32
-;;   ld t3,8(a2)
-;;   ld t0,0(a2)
-;;   add t0,t0,t4
-;;   li t1,0
-;;   uge t3,t4,t3##ty=i64
-;;   selectif_spectre_guard t4,t1,t0##test=t3
-;;   sb a1,0(t4)
+;;   slli a0,a0,32
+;;   srli a3,a0,32
+;;   ld a4,8(a2)
+;;   uge a4,a3,a4##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t3,a4,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a3,a3,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sb a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a7,a0,32
-;;   srli t4,a7,32
-;;   ld t3,8(a1)
-;;   ld t0,0(a1)
-;;   add t0,t0,t4
-;;   li t1,0
-;;   uge t3,t4,t3##ty=i64
-;;   selectif_spectre_guard t4,t1,t0##test=t3
-;;   lbu a0,0(t4)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   ld a3,8(a1)
+;;   uge a3,a2,a3##ty=i64
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   li a2,0
+;;   andi t3,a3,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a2,a2,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lbu a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index 06f9bb58ccce..fcbfb69265b1 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,40 +41,52 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t2,a0,32
-;;   srli a3,t2,32
-;;   ld a0,8(a2)
-;;   lui a4,1048575
-;;   addi a4,a4,4095
-;;   add a0,a0,a4
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   lui a4,1
-;;   add a2,a2,a4
-;;   li a4,0
-;;   ugt a0,a3,a0##ty=i64
-;;   selectif_spectre_guard a3,a4,a2##test=a0
-;;   sb a1,0(a3)
+;;   slli a5,a0,32
+;;   srli a7,a5,32
+;;   ld a6,8(a2)
+;;   lui t3,1048575
+;;   addi t3,t3,4095
+;;   add a6,a6,t3
+;;   ugt t3,a7,a6##ty=i64
+;;   ld a6,0(a2)
+;;   add a6,a6,a7
+;;   lui a7,1
+;;   add a6,a6,a7
+;;   li a7,0
+;;   andi a0,t3,255
+;;   sltu a2,zero,a0
+;;   sub a4,zero,a2
+;;   and a7,a7,a4
+;;   not t3,a4
+;;   and t0,a6,t3
+;;   or t2,a7,t0
+;;   sb a1,0(t2)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t2,a0,32
-;;   srli a2,t2,32
-;;   ld a0,8(a1)
-;;   lui a3,1048575
-;;   addi a3,a3,4095
-;;   add a0,a0,a3
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   lui a3,1
-;;   add a1,a1,a3
-;;   li a3,0
-;;   ugt a0,a2,a0##ty=i64
-;;   selectif_spectre_guard a2,a3,a1##test=a0
-;;   lbu a0,0(a2)
+;;   slli a5,a0,32
+;;   srli a7,a5,32
+;;   ld a6,8(a1)
+;;   lui t3,1048575
+;;   addi t3,t3,4095
+;;   add a6,a6,t3
+;;   ugt t3,a7,a6##ty=i64
+;;   ld a6,0(a1)
+;;   add a6,a6,a7
+;;   lui a7,1
+;;   add a6,a6,a7
+;;   li a7,0
+;;   andi a0,t3,255
+;;   sltu a2,zero,a0
+;;   sub a4,zero,a2
+;;   and a7,a7,a4
+;;   not t3,a4
+;;   and t0,a6,t3
+;;   or t2,a7,t0
+;;   lbu a0,0(t2)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index e9abd3009e39..5aa80eeb8d2b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,42 +41,54 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t2,a0,32
-;;   srli a3,t2,32
-;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0001
-;;   add t2,a3,a0
-;;   ult a4,t2,a3##ty=i64
-;;   trap_if a4,heap_oob
-;;   ld a4,8(a2)
-;;   ld a2,0(a2)
-;;   add a2,a2,a3
-;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
-;;   add a2,a2,a3
-;;   li a3,0
-;;   ugt a4,t2,a4##ty=i64
-;;   selectif_spectre_guard a5,a3,a2##test=a4
-;;   sb a1,0(a5)
+;;   slli a5,a0,32
+;;   srli a7,a5,32
+;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0001
+;;   add a5,a7,a6
+;;   ult t3,a5,a7##ty=i64
+;;   trap_if t3,heap_oob
+;;   ld t3,8(a2)
+;;   ugt t3,a5,t3##ty=i64
+;;   ld t4,0(a2)
+;;   add a7,t4,a7
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
+;;   add a7,a7,t4
+;;   li t4,0
+;;   andi a2,t3,255
+;;   sltu a3,zero,a2
+;;   sub a5,zero,a3
+;;   and t3,t4,a5
+;;   not t4,a5
+;;   and t1,a7,t4
+;;   or a0,t3,t1
+;;   sb a1,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t2,a0,32
-;;   srli a2,t2,32
-;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0001
-;;   add t2,a2,a0
-;;   ult a3,t2,a2##ty=i64
-;;   trap_if a3,heap_oob
-;;   ld a3,8(a1)
-;;   ld a1,0(a1)
-;;   add a1,a1,a2
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
-;;   add a1,a1,a2
-;;   li a2,0
-;;   ugt a3,t2,a3##ty=i64
-;;   selectif_spectre_guard a4,a2,a1##test=a3
-;;   lbu a0,0(a4)
+;;   slli a5,a0,32
+;;   srli a7,a5,32
+;;   auipc a6,0; ld a6,12(a6); j 12; .8byte 0xffff0001
+;;   add a5,a7,a6
+;;   ult t3,a5,a7##ty=i64
+;;   trap_if t3,heap_oob
+;;   ld t3,8(a1)
+;;   ugt t3,a5,t3##ty=i64
+;;   ld t4,0(a1)
+;;   add a7,t4,a7
+;;   auipc t4,0; ld t4,12(t4); j 12; .8byte 0xffff0000
+;;   add a7,a7,t4
+;;   li t4,0
+;;   andi a1,t3,255
+;;   sltu a3,zero,a1
+;;   sub a5,zero,a3
+;;   and t3,t4,a5
+;;   not t4,a5
+;;   and t1,a7,t4
+;;   or a0,t3,t1
+;;   lbu a0,0(a0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 9ead89e2b704..23fc37420d0e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,30 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a7,a0,32
-;;   srli t4,a7,32
-;;   ld t3,8(a2)
-;;   ld t0,0(a2)
-;;   add t0,t0,t4
-;;   li t1,0
-;;   ugt t3,t4,t3##ty=i64
-;;   selectif_spectre_guard t4,t1,t0##test=t3
-;;   sw a1,0(t4)
+;;   slli a0,a0,32
+;;   srli a3,a0,32
+;;   ld a4,8(a2)
+;;   ugt a4,a3,a4##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t3,a4,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a3,a3,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sw a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a7,a0,32
-;;   srli t4,a7,32
-;;   ld t3,8(a1)
-;;   ld t0,0(a1)
-;;   add t0,t0,t4
-;;   li t1,0
-;;   ugt t3,t4,t3##ty=i64
-;;   selectif_spectre_guard t4,t1,t0##test=t3
-;;   lw a0,0(t4)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   ld a3,8(a1)
+;;   ugt a3,a2,a3##ty=i64
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   li a2,0
+;;   andi t3,a3,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a2,a2,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lw a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 68ef87bca359..6f51038a81d4 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -41,34 +41,46 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t4,a0,32
-;;   srli t1,t4,32
-;;   ld t0,8(a2)
-;;   ld t2,0(a2)
-;;   add t2,t2,t1
-;;   lui a0,1
-;;   add t2,t2,a0
-;;   li a0,0
-;;   ugt t0,t1,t0##ty=i64
-;;   selectif_spectre_guard t1,a0,t2##test=t0
-;;   sw a1,0(t1)
+;;   slli a3,a0,32
+;;   srli a5,a3,32
+;;   ld a3,8(a2)
+;;   ugt a4,a5,a3##ty=i64
+;;   ld a3,0(a2)
+;;   add a3,a3,a5
+;;   lui a5,1
+;;   add a3,a3,a5
+;;   li a5,0
+;;   andi t0,a4,255
+;;   sltu t2,zero,t0
+;;   sub a2,zero,t2
+;;   and a4,a5,a2
+;;   not a5,a2
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   sw a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t4,a0,32
-;;   srli t1,t4,32
-;;   ld t0,8(a1)
-;;   ld t2,0(a1)
-;;   add t2,t2,t1
-;;   lui a0,1
-;;   add t2,t2,a0
-;;   li a0,0
-;;   ugt t0,t1,t0##ty=i64
-;;   selectif_spectre_guard t1,a0,t2##test=t0
-;;   lw a0,0(t1)
+;;   slli a2,a0,32
+;;   srli a5,a2,32
+;;   ld a3,8(a1)
+;;   ugt a4,a5,a3##ty=i64
+;;   ld a3,0(a1)
+;;   add a3,a3,a5
+;;   lui a5,1
+;;   add a3,a3,a5
+;;   li a5,0
+;;   andi t0,a4,255
+;;   sltu t2,zero,t0
+;;   sub a1,zero,t2
+;;   and a4,a5,a1
+;;   not a5,a1
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   lw a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index dbcfffdb0ef6..08fbad1904ca 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,34 +41,46 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t4,a0,32
-;;   srli t1,t4,32
-;;   ld t0,8(a2)
-;;   ld t2,0(a2)
-;;   add t2,t2,t1
-;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
-;;   add t2,t2,a0
-;;   li a0,0
-;;   ugt t0,t1,t0##ty=i64
-;;   selectif_spectre_guard t1,a0,t2##test=t0
-;;   sw a1,0(t1)
+;;   slli a3,a0,32
+;;   srli a5,a3,32
+;;   ld a3,8(a2)
+;;   ugt a4,a5,a3##ty=i64
+;;   ld a3,0(a2)
+;;   add a3,a3,a5
+;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
+;;   add a3,a3,a5
+;;   li a5,0
+;;   andi t0,a4,255
+;;   sltu t2,zero,t0
+;;   sub a2,zero,t2
+;;   and a4,a5,a2
+;;   not a5,a2
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   sw a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t4,a0,32
-;;   srli t1,t4,32
-;;   ld t0,8(a1)
-;;   ld t2,0(a1)
-;;   add t2,t2,t1
-;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
-;;   add t2,t2,a0
-;;   li a0,0
-;;   ugt t0,t1,t0##ty=i64
-;;   selectif_spectre_guard t1,a0,t2##test=t0
-;;   lw a0,0(t1)
+;;   slli a2,a0,32
+;;   srli a5,a2,32
+;;   ld a3,8(a1)
+;;   ugt a4,a5,a3##ty=i64
+;;   ld a3,0(a1)
+;;   add a3,a3,a5
+;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
+;;   add a3,a3,a5
+;;   li a5,0
+;;   andi t0,a4,255
+;;   sltu t2,zero,t0
+;;   sub a1,zero,t2
+;;   and a4,a5,a1
+;;   not a5,a1
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   lw a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index bc1e6cc71932..8ab4f482fd8f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,30 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli a7,a0,32
-;;   srli t4,a7,32
-;;   ld t3,8(a2)
-;;   ld t0,0(a2)
-;;   add t0,t0,t4
-;;   li t1,0
-;;   uge t3,t4,t3##ty=i64
-;;   selectif_spectre_guard t4,t1,t0##test=t3
-;;   sb a1,0(t4)
+;;   slli a0,a0,32
+;;   srli a3,a0,32
+;;   ld a4,8(a2)
+;;   uge a4,a3,a4##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t3,a4,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a3,a3,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sb a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli a7,a0,32
-;;   srli t4,a7,32
-;;   ld t3,8(a1)
-;;   ld t0,0(a1)
-;;   add t0,t0,t4
-;;   li t1,0
-;;   uge t3,t4,t3##ty=i64
-;;   selectif_spectre_guard t4,t1,t0##test=t3
-;;   lbu a0,0(t4)
+;;   slli a0,a0,32
+;;   srli a2,a0,32
+;;   ld a3,8(a1)
+;;   uge a3,a2,a3##ty=i64
+;;   ld a1,0(a1)
+;;   add a1,a1,a2
+;;   li a2,0
+;;   andi t3,a3,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a2,a2,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lbu a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index 9aabb5223de5..3be511d027e9 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,34 +41,46 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t4,a0,32
-;;   srli t1,t4,32
-;;   ld t0,8(a2)
-;;   ld t2,0(a2)
-;;   add t2,t2,t1
-;;   lui a0,1
-;;   add t2,t2,a0
-;;   li a0,0
-;;   ugt t0,t1,t0##ty=i64
-;;   selectif_spectre_guard t1,a0,t2##test=t0
-;;   sb a1,0(t1)
+;;   slli a3,a0,32
+;;   srli a5,a3,32
+;;   ld a3,8(a2)
+;;   ugt a4,a5,a3##ty=i64
+;;   ld a3,0(a2)
+;;   add a3,a3,a5
+;;   lui a5,1
+;;   add a3,a3,a5
+;;   li a5,0
+;;   andi t0,a4,255
+;;   sltu t2,zero,t0
+;;   sub a2,zero,t2
+;;   and a4,a5,a2
+;;   not a5,a2
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   sb a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t4,a0,32
-;;   srli t1,t4,32
-;;   ld t0,8(a1)
-;;   ld t2,0(a1)
-;;   add t2,t2,t1
-;;   lui a0,1
-;;   add t2,t2,a0
-;;   li a0,0
-;;   ugt t0,t1,t0##ty=i64
-;;   selectif_spectre_guard t1,a0,t2##test=t0
-;;   lbu a0,0(t1)
+;;   slli a2,a0,32
+;;   srli a5,a2,32
+;;   ld a3,8(a1)
+;;   ugt a4,a5,a3##ty=i64
+;;   ld a3,0(a1)
+;;   add a3,a3,a5
+;;   lui a5,1
+;;   add a3,a3,a5
+;;   li a5,0
+;;   andi t0,a4,255
+;;   sltu t2,zero,t0
+;;   sub a1,zero,t2
+;;   and a4,a5,a1
+;;   not a5,a1
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   lbu a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 28643b096e06..c5fac9a92678 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,34 +41,46 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t4,a0,32
-;;   srli t1,t4,32
-;;   ld t0,8(a2)
-;;   ld t2,0(a2)
-;;   add t2,t2,t1
-;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
-;;   add t2,t2,a0
-;;   li a0,0
-;;   ugt t0,t1,t0##ty=i64
-;;   selectif_spectre_guard t1,a0,t2##test=t0
-;;   sb a1,0(t1)
+;;   slli a3,a0,32
+;;   srli a5,a3,32
+;;   ld a3,8(a2)
+;;   ugt a4,a5,a3##ty=i64
+;;   ld a3,0(a2)
+;;   add a3,a3,a5
+;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
+;;   add a3,a3,a5
+;;   li a5,0
+;;   andi t0,a4,255
+;;   sltu t2,zero,t0
+;;   sub a2,zero,t2
+;;   and a4,a5,a2
+;;   not a5,a2
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   sb a1,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t4,a0,32
-;;   srli t1,t4,32
-;;   ld t0,8(a1)
-;;   ld t2,0(a1)
-;;   add t2,t2,t1
-;;   auipc a0,0; ld a0,12(a0); j 12; .8byte 0xffff0000
-;;   add t2,t2,a0
-;;   li a0,0
-;;   ugt t0,t1,t0##ty=i64
-;;   selectif_spectre_guard t1,a0,t2##test=t0
-;;   lbu a0,0(t1)
+;;   slli a2,a0,32
+;;   srli a5,a2,32
+;;   ld a3,8(a1)
+;;   ugt a4,a5,a3##ty=i64
+;;   ld a3,0(a1)
+;;   add a3,a3,a5
+;;   auipc a5,0; ld a5,12(a5); j 12; .8byte 0xffff0000
+;;   add a3,a3,a5
+;;   li a5,0
+;;   andi t0,a4,255
+;;   sltu t2,zero,t0
+;;   sub a1,zero,t2
+;;   and a4,a5,a1
+;;   not a5,a1
+;;   and a7,a3,a5
+;;   or t4,a4,a7
+;;   lbu a0,0(t4)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
index 77973fef2c22..95538dd91919 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,28 +41,40 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a7,8(a2)
-;;   addi a7,a7,-4
-;;   ld t3,0(a2)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   sw a1,0(t0)
+;;   ld a3,8(a2)
+;;   addi a3,a3,-4
+;;   ugt a4,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a0,a2,a0
+;;   li a3,0
+;;   andi a7,a4,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a2,a3,t1
+;;   not a3,t1
+;;   and a4,a0,a3
+;;   or a6,a2,a4
+;;   sw a1,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a7,8(a1)
-;;   addi a7,a7,-4
-;;   ld t3,0(a1)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   lw a0,0(t0)
+;;   ld a2,8(a1)
+;;   addi a2,a2,-4
+;;   ugt a3,a0,a2##ty=i64
+;;   ld a1,0(a1)
+;;   add a0,a1,a0
+;;   li a2,0
+;;   andi a7,a3,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a1,a2,t1
+;;   not a2,t1
+;;   and a4,a0,a2
+;;   or a6,a1,a4
+;;   lw a0,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 0fdb92005289..169c79927e88 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -41,36 +41,48 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld t1,8(a2)
-;;   lui t2,1048575
-;;   addi t2,t2,4092
-;;   add t1,t1,t2
-;;   ld t2,0(a2)
-;;   add t2,t2,a0
-;;   lui a2,1
-;;   add t2,t2,a2
-;;   li a2,0
-;;   ugt t1,a0,t1##ty=i64
-;;   selectif_spectre_guard a0,a2,t2##test=t1
-;;   sw a1,0(a0)
+;;   ld a4,8(a2)
+;;   lui a5,1048575
+;;   addi a5,a5,4092
+;;   add a4,a4,a5
+;;   ugt a5,a0,a4##ty=i64
+;;   ld a4,0(a2)
+;;   add a4,a4,a0
+;;   lui a6,1
+;;   add a4,a4,a6
+;;   li a6,0
+;;   andi t1,a5,255
+;;   sltu a0,zero,t1
+;;   sub a2,zero,a0
+;;   and a5,a6,a2
+;;   not a6,a2
+;;   and t3,a4,a6
+;;   or t0,a5,t3
+;;   sw a1,0(t0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld t1,8(a1)
-;;   lui t2,1048575
-;;   addi t2,t2,4092
-;;   add t1,t1,t2
-;;   ld t2,0(a1)
-;;   add t2,t2,a0
-;;   lui a1,1
-;;   add t2,t2,a1
-;;   li a1,0
-;;   ugt t1,a0,t1##ty=i64
-;;   selectif_spectre_guard a0,a1,t2##test=t1
-;;   lw a0,0(a0)
+;;   ld a4,8(a1)
+;;   lui a5,1048575
+;;   addi a5,a5,4092
+;;   add a4,a4,a5
+;;   ugt a5,a0,a4##ty=i64
+;;   ld a4,0(a1)
+;;   add a4,a4,a0
+;;   lui a6,1
+;;   add a4,a4,a6
+;;   li a6,0
+;;   andi t1,a5,255
+;;   sltu a0,zero,t1
+;;   sub a2,zero,a0
+;;   and a5,a6,a2
+;;   not a6,a2
+;;   and t3,a4,a6
+;;   or t0,a5,t3
+;;   lw a0,0(t0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index 7be7b3cbebfc..711ee993b425 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,38 +41,50 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
-;;   add t0,a0,t1
-;;   ult t2,t0,a0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a2)
-;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
-;;   add a0,a0,a2
-;;   li a2,0
-;;   ugt t2,t0,t2##ty=i64
-;;   selectif_spectre_guard a3,a2,a0##test=t2
-;;   sw a1,0(a3)
+;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0004
+;;   add a3,a0,a4
+;;   ult a5,a3,a0##ty=i64
+;;   trap_if a5,heap_oob
+;;   ld a5,8(a2)
+;;   ugt a6,a3,a5##ty=i64
+;;   ld a5,0(a2)
+;;   add a5,a5,a0
+;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
+;;   add a5,a5,a7
+;;   li a7,0
+;;   andi t2,a6,255
+;;   sltu a2,zero,t2
+;;   sub a3,zero,a2
+;;   and a6,a7,a3
+;;   not a7,a3
+;;   and t4,a5,a7
+;;   or t1,a6,t4
+;;   sw a1,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0004
-;;   add t0,a0,t1
-;;   ult t2,t0,a0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a1)
-;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
-;;   add a0,a0,a1
-;;   li a1,0
-;;   ugt t2,t0,t2##ty=i64
-;;   selectif_spectre_guard a2,a1,a0##test=t2
-;;   lw a0,0(a2)
+;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0004
+;;   add a3,a0,a4
+;;   ult a5,a3,a0##ty=i64
+;;   trap_if a5,heap_oob
+;;   ld a5,8(a1)
+;;   ugt a6,a3,a5##ty=i64
+;;   ld a5,0(a1)
+;;   add a5,a5,a0
+;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
+;;   add a5,a5,a7
+;;   li a7,0
+;;   andi t2,a6,255
+;;   sltu a1,zero,t2
+;;   sub a3,zero,a1
+;;   and a6,a7,a3
+;;   not a7,a3
+;;   and t4,a5,a7
+;;   or t1,a6,t4
+;;   lw a0,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 460e46f3ca53..c488b2fa0f75 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,26 +41,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a6,8(a2)
-;;   ld a7,0(a2)
-;;   add a7,a7,a0
-;;   li t3,0
-;;   uge a6,a0,a6##ty=i64
-;;   selectif_spectre_guard t4,t3,a7##test=a6
-;;   sb a1,0(t4)
+;;   ld t2,8(a2)
+;;   uge a3,a0,t2##ty=i64
+;;   ld t2,0(a2)
+;;   add t2,t2,a0
+;;   li a2,0
+;;   andi a6,a3,255
+;;   sltu t3,zero,a6
+;;   sub t0,zero,t3
+;;   and a0,a2,t0
+;;   not a2,t0
+;;   and a3,t2,a2
+;;   or a5,a0,a3
+;;   sb a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a6,8(a1)
-;;   ld a7,0(a1)
-;;   add a7,a7,a0
-;;   li t3,0
-;;   uge a6,a0,a6##ty=i64
-;;   selectif_spectre_guard t4,t3,a7##test=a6
-;;   lbu a0,0(t4)
+;;   ld t2,8(a1)
+;;   uge a2,a0,t2##ty=i64
+;;   ld t2,0(a1)
+;;   add t2,t2,a0
+;;   li a1,0
+;;   andi a6,a2,255
+;;   sltu t3,zero,a6
+;;   sub t0,zero,t3
+;;   and a0,a1,t0
+;;   not a1,t0
+;;   and a3,t2,a1
+;;   or a5,a0,a3
+;;   lbu a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index b3b6723fbe95..dcd8657c46ba 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,36 +41,48 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld t1,8(a2)
-;;   lui t2,1048575
-;;   addi t2,t2,4095
-;;   add t1,t1,t2
-;;   ld t2,0(a2)
-;;   add t2,t2,a0
-;;   lui a2,1
-;;   add t2,t2,a2
-;;   li a2,0
-;;   ugt t1,a0,t1##ty=i64
-;;   selectif_spectre_guard a0,a2,t2##test=t1
-;;   sb a1,0(a0)
+;;   ld a4,8(a2)
+;;   lui a5,1048575
+;;   addi a5,a5,4095
+;;   add a4,a4,a5
+;;   ugt a5,a0,a4##ty=i64
+;;   ld a4,0(a2)
+;;   add a4,a4,a0
+;;   lui a6,1
+;;   add a4,a4,a6
+;;   li a6,0
+;;   andi t1,a5,255
+;;   sltu a0,zero,t1
+;;   sub a2,zero,a0
+;;   and a5,a6,a2
+;;   not a6,a2
+;;   and t3,a4,a6
+;;   or t0,a5,t3
+;;   sb a1,0(t0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld t1,8(a1)
-;;   lui t2,1048575
-;;   addi t2,t2,4095
-;;   add t1,t1,t2
-;;   ld t2,0(a1)
-;;   add t2,t2,a0
-;;   lui a1,1
-;;   add t2,t2,a1
-;;   li a1,0
-;;   ugt t1,a0,t1##ty=i64
-;;   selectif_spectre_guard a0,a1,t2##test=t1
-;;   lbu a0,0(a0)
+;;   ld a4,8(a1)
+;;   lui a5,1048575
+;;   addi a5,a5,4095
+;;   add a4,a4,a5
+;;   ugt a5,a0,a4##ty=i64
+;;   ld a4,0(a1)
+;;   add a4,a4,a0
+;;   lui a6,1
+;;   add a4,a4,a6
+;;   li a6,0
+;;   andi t1,a5,255
+;;   sltu a0,zero,t1
+;;   sub a2,zero,a0
+;;   and a5,a6,a2
+;;   not a6,a2
+;;   and t3,a4,a6
+;;   or t0,a5,t3
+;;   lbu a0,0(t0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index 5bd731dbf01a..46030e9bcb2d 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,38 +41,50 @@
 
 ;; function u0:0:
 ;; block0:
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
-;;   add t0,a0,t1
-;;   ult t2,t0,a0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a2)
-;;   ld a2,0(a2)
-;;   add a0,a2,a0
-;;   auipc a2,0; ld a2,12(a2); j 12; .8byte 0xffff0000
-;;   add a0,a0,a2
-;;   li a2,0
-;;   ugt t2,t0,t2##ty=i64
-;;   selectif_spectre_guard a3,a2,a0##test=t2
-;;   sb a1,0(a3)
+;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0001
+;;   add a3,a0,a4
+;;   ult a5,a3,a0##ty=i64
+;;   trap_if a5,heap_oob
+;;   ld a5,8(a2)
+;;   ugt a6,a3,a5##ty=i64
+;;   ld a5,0(a2)
+;;   add a5,a5,a0
+;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
+;;   add a5,a5,a7
+;;   li a7,0
+;;   andi t2,a6,255
+;;   sltu a2,zero,t2
+;;   sub a3,zero,a2
+;;   and a6,a7,a3
+;;   not a7,a3
+;;   and t4,a5,a7
+;;   or t1,a6,t4
+;;   sb a1,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   auipc t1,0; ld t1,12(t1); j 12; .8byte 0xffff0001
-;;   add t0,a0,t1
-;;   ult t2,t0,a0##ty=i64
-;;   trap_if t2,heap_oob
-;;   ld t2,8(a1)
-;;   ld a1,0(a1)
-;;   add a0,a1,a0
-;;   auipc a1,0; ld a1,12(a1); j 12; .8byte 0xffff0000
-;;   add a0,a0,a1
-;;   li a1,0
-;;   ugt t2,t0,t2##ty=i64
-;;   selectif_spectre_guard a2,a1,a0##test=t2
-;;   lbu a0,0(a2)
+;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0001
+;;   add a3,a0,a4
+;;   ult a5,a3,a0##ty=i64
+;;   trap_if a5,heap_oob
+;;   ld a5,8(a1)
+;;   ugt a6,a3,a5##ty=i64
+;;   ld a5,0(a1)
+;;   add a5,a5,a0
+;;   auipc a7,0; ld a7,12(a7); j 12; .8byte 0xffff0000
+;;   add a5,a5,a7
+;;   li a7,0
+;;   andi t2,a6,255
+;;   sltu a1,zero,t2
+;;   sub a3,zero,a1
+;;   and a6,a7,a3
+;;   not a7,a3
+;;   and t4,a5,a7
+;;   or t1,a6,t4
+;;   lbu a0,0(t1)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index 17d9858dfb78..1bd978036ebe 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -41,26 +41,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a6,8(a2)
-;;   ld a7,0(a2)
-;;   add a7,a7,a0
-;;   li t3,0
-;;   ugt a6,a0,a6##ty=i64
-;;   selectif_spectre_guard t4,t3,a7##test=a6
-;;   sw a1,0(t4)
+;;   ld t2,8(a2)
+;;   ugt a3,a0,t2##ty=i64
+;;   ld t2,0(a2)
+;;   add t2,t2,a0
+;;   li a2,0
+;;   andi a6,a3,255
+;;   sltu t3,zero,a6
+;;   sub t0,zero,t3
+;;   and a0,a2,t0
+;;   not a2,t0
+;;   and a3,t2,a2
+;;   or a5,a0,a3
+;;   sw a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a6,8(a1)
-;;   ld a7,0(a1)
-;;   add a7,a7,a0
-;;   li t3,0
-;;   ugt a6,a0,a6##ty=i64
-;;   selectif_spectre_guard t4,t3,a7##test=a6
-;;   lw a0,0(t4)
+;;   ld t2,8(a1)
+;;   ugt a2,a0,t2##ty=i64
+;;   ld t2,0(a1)
+;;   add t2,t2,a0
+;;   li a1,0
+;;   andi a6,a2,255
+;;   sltu t3,zero,a6
+;;   sub t0,zero,t3
+;;   and a0,a1,t0
+;;   not a1,t0
+;;   and a3,t2,a1
+;;   or a5,a0,a3
+;;   lw a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 9f274425eb1c..ab8b1ebd3ea7 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -41,30 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld t3,8(a2)
-;;   ld t4,0(a2)
-;;   add t4,t4,a0
-;;   lui t0,1
-;;   add t4,t4,t0
-;;   li t0,0
-;;   ugt t3,a0,t3##ty=i64
-;;   selectif_spectre_guard t1,t0,t4##test=t3
-;;   sw a1,0(t1)
+;;   ld a3,8(a2)
+;;   ugt a3,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t3,a3,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a3,a4,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sw a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld t3,8(a1)
-;;   ld t4,0(a1)
-;;   add t4,t4,a0
-;;   lui t0,1
-;;   add t4,t4,t0
-;;   li t0,0
-;;   ugt t3,a0,t3##ty=i64
-;;   selectif_spectre_guard t1,t0,t4##test=t3
-;;   lw a0,0(t1)
+;;   ld a2,8(a1)
+;;   ugt a2,a0,a2##ty=i64
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
+;;   lui a3,1
+;;   add a1,a1,a3
+;;   li a3,0
+;;   andi t3,a2,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a2,a3,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lw a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
index b310f6a8f500..fb3ee241fa6b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat
@@ -41,30 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld t3,8(a2)
-;;   ld t4,0(a2)
-;;   add t4,t4,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
-;;   add t4,t4,t0
-;;   li t0,0
-;;   ugt t3,a0,t3##ty=i64
-;;   selectif_spectre_guard t1,t0,t4##test=t3
-;;   sw a1,0(t1)
+;;   ld a3,8(a2)
+;;   ugt a3,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0000
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t3,a3,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a3,a4,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sw a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld t3,8(a1)
-;;   ld t4,0(a1)
-;;   add t4,t4,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
-;;   add t4,t4,t0
-;;   li t0,0
-;;   ugt t3,a0,t3##ty=i64
-;;   selectif_spectre_guard t1,t0,t4##test=t3
-;;   lw a0,0(t1)
+;;   ld a2,8(a1)
+;;   ugt a2,a0,a2##ty=i64
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
+;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
+;;   add a1,a1,a3
+;;   li a3,0
+;;   andi t3,a2,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a2,a3,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lw a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index e7effd2d9852..61bf3ae3942a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -41,26 +41,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld a6,8(a2)
-;;   ld a7,0(a2)
-;;   add a7,a7,a0
-;;   li t3,0
-;;   uge a6,a0,a6##ty=i64
-;;   selectif_spectre_guard t4,t3,a7##test=a6
-;;   sb a1,0(t4)
+;;   ld t2,8(a2)
+;;   uge a3,a0,t2##ty=i64
+;;   ld t2,0(a2)
+;;   add t2,t2,a0
+;;   li a2,0
+;;   andi a6,a3,255
+;;   sltu t3,zero,a6
+;;   sub t0,zero,t3
+;;   and a0,a2,t0
+;;   not a2,t0
+;;   and a3,t2,a2
+;;   or a5,a0,a3
+;;   sb a1,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld a6,8(a1)
-;;   ld a7,0(a1)
-;;   add a7,a7,a0
-;;   li t3,0
-;;   uge a6,a0,a6##ty=i64
-;;   selectif_spectre_guard t4,t3,a7##test=a6
-;;   lbu a0,0(t4)
+;;   ld t2,8(a1)
+;;   uge a2,a0,t2##ty=i64
+;;   ld t2,0(a1)
+;;   add t2,t2,a0
+;;   li a1,0
+;;   andi a6,a2,255
+;;   sltu t3,zero,a6
+;;   sub t0,zero,t3
+;;   and a0,a1,t0
+;;   not a1,t0
+;;   and a3,t2,a1
+;;   or a5,a0,a3
+;;   lbu a0,0(a5)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index ab687a762d49..c91ab3179c4e 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -41,30 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld t3,8(a2)
-;;   ld t4,0(a2)
-;;   add t4,t4,a0
-;;   lui t0,1
-;;   add t4,t4,t0
-;;   li t0,0
-;;   ugt t3,a0,t3##ty=i64
-;;   selectif_spectre_guard t1,t0,t4##test=t3
-;;   sb a1,0(t1)
+;;   ld a3,8(a2)
+;;   ugt a3,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t3,a3,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a3,a4,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sb a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld t3,8(a1)
-;;   ld t4,0(a1)
-;;   add t4,t4,a0
-;;   lui t0,1
-;;   add t4,t4,t0
-;;   li t0,0
-;;   ugt t3,a0,t3##ty=i64
-;;   selectif_spectre_guard t1,t0,t4##test=t3
-;;   lbu a0,0(t1)
+;;   ld a2,8(a1)
+;;   ugt a2,a0,a2##ty=i64
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
+;;   lui a3,1
+;;   add a1,a1,a3
+;;   li a3,0
+;;   andi t3,a2,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a2,a3,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lbu a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
index c2ad22aaae60..ef2f55b8b21b 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat
@@ -41,30 +41,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   ld t3,8(a2)
-;;   ld t4,0(a2)
-;;   add t4,t4,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
-;;   add t4,t4,t0
-;;   li t0,0
-;;   ugt t3,a0,t3##ty=i64
-;;   selectif_spectre_guard t1,t0,t4##test=t3
-;;   sb a1,0(t1)
+;;   ld a3,8(a2)
+;;   ugt a3,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   auipc a4,0; ld a4,12(a4); j 12; .8byte 0xffff0000
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t3,a3,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a3,a4,t2
+;;   not a4,t2
+;;   and a5,a2,a4
+;;   or a7,a3,a5
+;;   sb a1,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   ld t3,8(a1)
-;;   ld t4,0(a1)
-;;   add t4,t4,a0
-;;   auipc t0,0; ld t0,12(t0); j 12; .8byte 0xffff0000
-;;   add t4,t4,t0
-;;   li t0,0
-;;   ugt t3,a0,t3##ty=i64
-;;   selectif_spectre_guard t1,t0,t4##test=t3
-;;   lbu a0,0(t1)
+;;   ld a2,8(a1)
+;;   ugt a2,a0,a2##ty=i64
+;;   ld a1,0(a1)
+;;   add a1,a1,a0
+;;   auipc a3,0; ld a3,12(a3); j 12; .8byte 0xffff0000
+;;   add a1,a1,a3
+;;   li a3,0
+;;   andi t3,a2,255
+;;   sltu t0,zero,t3
+;;   sub t2,zero,t0
+;;   and a2,a3,t2
+;;   not a3,t2
+;;   and a5,a1,a3
+;;   or a7,a2,a5
+;;   lbu a0,0(a7)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
index be47a58633e3..b709b33b0bfc 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -39,32 +39,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t3,a0,32
-;;   srli t0,t3,32
-;;   lui t4,65536
-;;   addi t4,t4,4092
-;;   ld t1,0(a2)
-;;   add t1,t1,t0
-;;   li t2,0
-;;   ugt t4,t0,t4##ty=i64
-;;   selectif_spectre_guard t0,t2,t1##test=t4
-;;   sw a1,0(t0)
+;;   slli a3,a0,32
+;;   srli a3,a3,32
+;;   lui a4,65536
+;;   addi a4,a4,4092
+;;   ugt a4,a3,a4##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sw a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t3,a0,32
-;;   srli t0,t3,32
-;;   lui t4,65536
-;;   addi t4,t4,4092
-;;   ld t1,0(a1)
-;;   add t1,t1,t0
-;;   li t2,0
-;;   ugt t4,t0,t4##ty=i64
-;;   selectif_spectre_guard t0,t2,t1##test=t4
-;;   lw a0,0(t0)
+;;   slli a2,a0,32
+;;   srli a3,a2,32
+;;   lui a2,65536
+;;   addi a2,a2,4092
+;;   ugt a4,a3,a2##ty=i64
+;;   ld a2,0(a1)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lw a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 70bc1ff324c8..a827bbe9882f 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -39,36 +39,48 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t0,a0,32
-;;   srli t2,t0,32
-;;   lui t1,65535
-;;   addi t1,t1,4092
-;;   ld a0,0(a2)
-;;   add a0,a0,t2
-;;   lui a2,1
-;;   add a0,a0,a2
-;;   li a2,0
-;;   ugt t1,t2,t1##ty=i64
-;;   selectif_spectre_guard t2,a2,a0##test=t1
-;;   sw a1,0(t2)
+;;   slli a3,a0,32
+;;   srli a6,a3,32
+;;   lui a4,65535
+;;   addi a4,a4,4092
+;;   ugt a5,a6,a4##ty=i64
+;;   ld a4,0(a2)
+;;   add a4,a4,a6
+;;   lui a6,1
+;;   add a4,a4,a6
+;;   li a6,0
+;;   andi t1,a5,255
+;;   sltu a0,zero,t1
+;;   sub a2,zero,a0
+;;   and a5,a6,a2
+;;   not a6,a2
+;;   and t3,a4,a6
+;;   or t0,a5,t3
+;;   sw a1,0(t0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t0,a0,32
-;;   srli t2,t0,32
-;;   lui t1,65535
-;;   addi t1,t1,4092
-;;   ld a0,0(a1)
-;;   add a0,a0,t2
-;;   lui a1,1
-;;   add a0,a0,a1
-;;   li a1,0
-;;   ugt t1,t2,t1##ty=i64
-;;   selectif_spectre_guard t2,a1,a0##test=t1
-;;   lw a0,0(t2)
+;;   slli a3,a0,32
+;;   srli a6,a3,32
+;;   lui a4,65535
+;;   addi a4,a4,4092
+;;   ugt a5,a6,a4##ty=i64
+;;   ld a4,0(a1)
+;;   add a4,a4,a6
+;;   lui a6,1
+;;   add a4,a4,a6
+;;   li a6,0
+;;   andi t1,a5,255
+;;   sltu a0,zero,t1
+;;   sub a2,zero,a0
+;;   and a5,a6,a2
+;;   not a6,a2
+;;   and t3,a4,a6
+;;   or t0,a5,t3
+;;   lw a0,0(t0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
index f3271adaf721..78de2ddc8dcc 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -39,32 +39,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t3,a0,32
-;;   srli t0,t3,32
-;;   lui t4,65536
-;;   addi t4,t4,4095
-;;   ld t1,0(a2)
-;;   add t1,t1,t0
-;;   li t2,0
-;;   ugt t4,t0,t4##ty=i64
-;;   selectif_spectre_guard t0,t2,t1##test=t4
-;;   sb a1,0(t0)
+;;   slli a3,a0,32
+;;   srli a3,a3,32
+;;   lui a4,65536
+;;   addi a4,a4,4095
+;;   ugt a4,a3,a4##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sb a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t3,a0,32
-;;   srli t0,t3,32
-;;   lui t4,65536
-;;   addi t4,t4,4095
-;;   ld t1,0(a1)
-;;   add t1,t1,t0
-;;   li t2,0
-;;   ugt t4,t0,t4##ty=i64
-;;   selectif_spectre_guard t0,t2,t1##test=t4
-;;   lbu a0,0(t0)
+;;   slli a2,a0,32
+;;   srli a3,a2,32
+;;   lui a2,65536
+;;   addi a2,a2,4095
+;;   ugt a4,a3,a2##ty=i64
+;;   ld a2,0(a1)
+;;   add a2,a2,a3
+;;   li a3,0
+;;   andi t4,a4,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a3,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lbu a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index decd139e2735..83e1ce6e0d67 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -39,36 +39,48 @@
 
 ;; function u0:0:
 ;; block0:
-;;   slli t0,a0,32
-;;   srli t2,t0,32
-;;   lui t1,65535
-;;   addi t1,t1,4095
-;;   ld a0,0(a2)
-;;   add a0,a0,t2
-;;   lui a2,1
-;;   add a0,a0,a2
-;;   li a2,0
-;;   ugt t1,t2,t1##ty=i64
-;;   selectif_spectre_guard t2,a2,a0##test=t1
-;;   sb a1,0(t2)
+;;   slli a3,a0,32
+;;   srli a6,a3,32
+;;   lui a4,65535
+;;   addi a4,a4,4095
+;;   ugt a5,a6,a4##ty=i64
+;;   ld a4,0(a2)
+;;   add a4,a4,a6
+;;   lui a6,1
+;;   add a4,a4,a6
+;;   li a6,0
+;;   andi t1,a5,255
+;;   sltu a0,zero,t1
+;;   sub a2,zero,a0
+;;   and a5,a6,a2
+;;   not a6,a2
+;;   and t3,a4,a6
+;;   or t0,a5,t3
+;;   sb a1,0(t0)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   slli t0,a0,32
-;;   srli t2,t0,32
-;;   lui t1,65535
-;;   addi t1,t1,4095
-;;   ld a0,0(a1)
-;;   add a0,a0,t2
-;;   lui a1,1
-;;   add a0,a0,a1
-;;   li a1,0
-;;   ugt t1,t2,t1##ty=i64
-;;   selectif_spectre_guard t2,a1,a0##test=t1
-;;   lbu a0,0(t2)
+;;   slli a3,a0,32
+;;   srli a6,a3,32
+;;   lui a4,65535
+;;   addi a4,a4,4095
+;;   ugt a5,a6,a4##ty=i64
+;;   ld a4,0(a1)
+;;   add a4,a4,a6
+;;   lui a6,1
+;;   add a4,a4,a6
+;;   li a6,0
+;;   andi t1,a5,255
+;;   sltu a0,zero,t1
+;;   sub a2,zero,a0
+;;   and a5,a6,a2
+;;   not a6,a2
+;;   and t3,a4,a6
+;;   or t0,a5,t3
+;;   lbu a0,0(t0)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
index f9cf2b3b6300..e30e0a0a1213 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat
@@ -39,28 +39,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui a7,65536
-;;   addi a7,a7,4092
-;;   ld t3,0(a2)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   sw a1,0(t0)
+;;   mv a4,a2
+;;   lui a2,65536
+;;   addi a2,a2,4092
+;;   ugt a2,a0,a2##ty=i64
+;;   ld a3,0(a4)
+;;   add a0,a3,a0
+;;   li a3,0
+;;   andi a7,a2,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a2,a3,t1
+;;   not a3,t1
+;;   and a4,a0,a3
+;;   or a6,a2,a4
+;;   sw a1,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a7,65536
-;;   addi a7,a7,4092
-;;   ld t3,0(a1)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   lw a0,0(t0)
+;;   mv a4,a1
+;;   lui a1,65536
+;;   addi a1,a1,4092
+;;   ugt a1,a0,a1##ty=i64
+;;   ld a2,0(a4)
+;;   add a0,a2,a0
+;;   li a2,0
+;;   andi a7,a1,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a1,a2,t1
+;;   not a2,t1
+;;   and a4,a0,a2
+;;   or a6,a1,a4
+;;   lw a0,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
index 338900641c6e..1c03fd957463 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -39,32 +39,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui t4,65535
-;;   addi t4,t4,4092
-;;   ld t0,0(a2)
-;;   add t0,t0,a0
-;;   lui t1,1
-;;   add t0,t0,t1
-;;   li t1,0
-;;   ugt t4,a0,t4##ty=i64
-;;   selectif_spectre_guard t2,t1,t0##test=t4
-;;   sw a1,0(t2)
+;;   lui a3,65535
+;;   addi a3,a3,4092
+;;   ugt a3,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t4,a3,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a4,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sw a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui t4,65535
-;;   addi t4,t4,4092
-;;   ld t0,0(a1)
-;;   add t0,t0,a0
-;;   lui t1,1
-;;   add t0,t0,t1
-;;   li t1,0
-;;   ugt t4,a0,t4##ty=i64
-;;   selectif_spectre_guard t2,t1,t0##test=t4
-;;   lw a0,0(t2)
+;;   lui a2,65535
+;;   addi a2,a2,4092
+;;   ugt a3,a0,a2##ty=i64
+;;   ld a2,0(a1)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t4,a3,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a4,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lw a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
index 048c78e4144b..d755a4f65adc 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat
@@ -39,28 +39,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui a7,65536
-;;   addi a7,a7,4095
-;;   ld t3,0(a2)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   sb a1,0(t0)
+;;   mv a4,a2
+;;   lui a2,65536
+;;   addi a2,a2,4095
+;;   ugt a2,a0,a2##ty=i64
+;;   ld a3,0(a4)
+;;   add a0,a3,a0
+;;   li a3,0
+;;   andi a7,a2,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a2,a3,t1
+;;   not a3,t1
+;;   and a4,a0,a3
+;;   or a6,a2,a4
+;;   sb a1,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a7,65536
-;;   addi a7,a7,4095
-;;   ld t3,0(a1)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   lbu a0,0(t0)
+;;   mv a4,a1
+;;   lui a1,65536
+;;   addi a1,a1,4095
+;;   ugt a1,a0,a1##ty=i64
+;;   ld a2,0(a4)
+;;   add a0,a2,a0
+;;   li a2,0
+;;   andi a7,a1,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a1,a2,t1
+;;   not a2,t1
+;;   and a4,a0,a2
+;;   or a6,a1,a4
+;;   lbu a0,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
index b12f888e44ad..6f2b6a18a934 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -39,32 +39,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui t4,65535
-;;   addi t4,t4,4095
-;;   ld t0,0(a2)
-;;   add t0,t0,a0
-;;   lui t1,1
-;;   add t0,t0,t1
-;;   li t1,0
-;;   ugt t4,a0,t4##ty=i64
-;;   selectif_spectre_guard t2,t1,t0##test=t4
-;;   sb a1,0(t2)
+;;   lui a3,65535
+;;   addi a3,a3,4095
+;;   ugt a3,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t4,a3,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a4,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sb a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui t4,65535
-;;   addi t4,t4,4095
-;;   ld t0,0(a1)
-;;   add t0,t0,a0
-;;   lui t1,1
-;;   add t0,t0,t1
-;;   li t1,0
-;;   ugt t4,a0,t4##ty=i64
-;;   selectif_spectre_guard t2,t1,t0##test=t4
-;;   lbu a0,0(t2)
+;;   lui a2,65535
+;;   addi a2,a2,4095
+;;   ugt a3,a0,a2##ty=i64
+;;   ld a2,0(a1)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t4,a3,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a4,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lbu a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
index a7226f095642..6d358beffe7a 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat
@@ -39,28 +39,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui a7,65536
-;;   addi a7,a7,4092
-;;   ld t3,0(a2)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   sw a1,0(t0)
+;;   mv a4,a2
+;;   lui a2,65536
+;;   addi a2,a2,4092
+;;   ugt a2,a0,a2##ty=i64
+;;   ld a3,0(a4)
+;;   add a0,a3,a0
+;;   li a3,0
+;;   andi a7,a2,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a2,a3,t1
+;;   not a3,t1
+;;   and a4,a0,a3
+;;   or a6,a2,a4
+;;   sw a1,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a7,65536
-;;   addi a7,a7,4092
-;;   ld t3,0(a1)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   lw a0,0(t0)
+;;   mv a4,a1
+;;   lui a1,65536
+;;   addi a1,a1,4092
+;;   ugt a1,a0,a1##ty=i64
+;;   ld a2,0(a4)
+;;   add a0,a2,a0
+;;   li a2,0
+;;   andi a7,a1,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a1,a2,t1
+;;   not a2,t1
+;;   and a4,a0,a2
+;;   or a6,a1,a4
+;;   lw a0,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
index 0ef257ed21a8..b40a4633afd5 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat
@@ -39,32 +39,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui t4,65535
-;;   addi t4,t4,4092
-;;   ld t0,0(a2)
-;;   add t0,t0,a0
-;;   lui t1,1
-;;   add t0,t0,t1
-;;   li t1,0
-;;   ugt t4,a0,t4##ty=i64
-;;   selectif_spectre_guard t2,t1,t0##test=t4
-;;   sw a1,0(t2)
+;;   lui a3,65535
+;;   addi a3,a3,4092
+;;   ugt a3,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t4,a3,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a4,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sw a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui t4,65535
-;;   addi t4,t4,4092
-;;   ld t0,0(a1)
-;;   add t0,t0,a0
-;;   lui t1,1
-;;   add t0,t0,t1
-;;   li t1,0
-;;   ugt t4,a0,t4##ty=i64
-;;   selectif_spectre_guard t2,t1,t0##test=t4
-;;   lw a0,0(t2)
+;;   lui a2,65535
+;;   addi a2,a2,4092
+;;   ugt a3,a0,a2##ty=i64
+;;   ld a2,0(a1)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t4,a3,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a4,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lw a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
index d7cb0c8ecfa6..4bbf4a4f3373 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat
@@ -39,28 +39,42 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui a7,65536
-;;   addi a7,a7,4095
-;;   ld t3,0(a2)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   sb a1,0(t0)
+;;   mv a4,a2
+;;   lui a2,65536
+;;   addi a2,a2,4095
+;;   ugt a2,a0,a2##ty=i64
+;;   ld a3,0(a4)
+;;   add a0,a3,a0
+;;   li a3,0
+;;   andi a7,a2,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a2,a3,t1
+;;   not a3,t1
+;;   and a4,a0,a3
+;;   or a6,a2,a4
+;;   sb a1,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui a7,65536
-;;   addi a7,a7,4095
-;;   ld t3,0(a1)
-;;   add t3,t3,a0
-;;   li t4,0
-;;   ugt a7,a0,a7##ty=i64
-;;   selectif_spectre_guard t0,t4,t3##test=a7
-;;   lbu a0,0(t0)
+;;   mv a4,a1
+;;   lui a1,65536
+;;   addi a1,a1,4095
+;;   ugt a1,a0,a1##ty=i64
+;;   ld a2,0(a4)
+;;   add a0,a2,a0
+;;   li a2,0
+;;   andi a7,a1,255
+;;   sltu t4,zero,a7
+;;   sub t1,zero,t4
+;;   and a1,a2,t1
+;;   not a2,t1
+;;   and a4,a0,a2
+;;   or a6,a1,a4
+;;   lbu a0,0(a6)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
index d67afb1fda15..7915fdfc5719 100644
--- a/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
+++ b/cranelift/filetests/filetests/isa/riscv64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat
@@ -39,32 +39,44 @@
 
 ;; function u0:0:
 ;; block0:
-;;   lui t4,65535
-;;   addi t4,t4,4095
-;;   ld t0,0(a2)
-;;   add t0,t0,a0
-;;   lui t1,1
-;;   add t0,t0,t1
-;;   li t1,0
-;;   ugt t4,a0,t4##ty=i64
-;;   selectif_spectre_guard t2,t1,t0##test=t4
-;;   sb a1,0(t2)
+;;   lui a3,65535
+;;   addi a3,a3,4095
+;;   ugt a3,a0,a3##ty=i64
+;;   ld a2,0(a2)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t4,a3,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a4,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   sb a1,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   lui t4,65535
-;;   addi t4,t4,4095
-;;   ld t0,0(a1)
-;;   add t0,t0,a0
-;;   lui t1,1
-;;   add t0,t0,t1
-;;   li t1,0
-;;   ugt t4,a0,t4##ty=i64
-;;   selectif_spectre_guard t2,t1,t0##test=t4
-;;   lbu a0,0(t2)
+;;   lui a2,65535
+;;   addi a2,a2,4095
+;;   ugt a3,a0,a2##ty=i64
+;;   ld a2,0(a1)
+;;   add a2,a2,a0
+;;   lui a4,1
+;;   add a2,a2,a4
+;;   li a4,0
+;;   andi t4,a3,255
+;;   sltu t1,zero,t4
+;;   sub a0,zero,t1
+;;   and a3,a4,a0
+;;   not a4,a0
+;;   and a6,a2,a4
+;;   or t3,a3,a6
+;;   lbu a0,0(t3)
 ;;   j label1
 ;; block1:
 ;;   ret
diff --git a/cranelift/filetests/filetests/runtests/selectif-spectre-guard.clif b/cranelift/filetests/filetests/runtests/selectif-spectre-guard.clif
index 1ce7fb2e4368..a34ad002593f 100644
--- a/cranelift/filetests/filetests/runtests/selectif-spectre-guard.clif
+++ b/cranelift/filetests/filetests/runtests/selectif-spectre-guard.clif
@@ -4,6 +4,7 @@ set enable_llvm_abi_extensions=true
 target aarch64
 target s390x
 target x86_64
+target riscv64
 
 function %select_spectre_guard_i8_eq(i8, i8, i8) -> i8 {
 block0(v0: i8, v1: i8, v2: i8):