From 4f601edc36efd45946230933978694d9bf80890c Mon Sep 17 00:00:00 2001
From: Johnnie Birch <johnnie.l.birch.jr@intel.com>
Date: Wed, 28 Jul 2021 23:33:42 -0700
Subject: [PATCH] Add x64 support for remaining int-to-int extend simd
 instructions

Adds remaming support for int to int extend simd instructions.
Specifically adds support for remaining I32x4->I64x2 instructions
---
 build.rs                               |  1 -
 cranelift/codegen/src/isa/x64/lower.rs | 31 ++++++++++++++++++++++----
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/build.rs b/build.rs
index 596f39caf619..7569c61c9d37 100644
--- a/build.rs
+++ b/build.rs
@@ -192,7 +192,6 @@ fn x64_should_panic(testsuite: &str, testname: &str, strategy: &str) -> bool {
     match (testsuite, testname) {
         ("simd", "simd_i16x8_extadd_pairwise_i8x16") => return true,
         ("simd", "simd_i32x4_extadd_pairwise_i16x8") => return true,
-        ("simd", "simd_int_to_int_extend") => return true,
         ("simd", _) => return false,
         _ => {}
     }
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 121bad94b078..657df3268447 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -4941,6 +4941,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                         (types::I16X8, types::I32X4) => {
                             ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::reg(src), dst));
                         }
+                        (types::I32X4, types::I64X2) => {
+                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::reg(src), dst));
+                        }
                         _ => unreachable!(),
                     },
                     Opcode::SwidenHigh => match (input_ty, output_ty) {
@@ -4966,6 +4969,16 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                             ));
                             ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::from(dst), dst));
                         }
+                        (types::I32X4, types::I64X2) => {
+                            ctx.emit(Inst::xmm_rm_r_imm(
+                                SseOpcode::Pshufd,
+                                RegMem::reg(src),
+                                dst,
+                                0xEE,
+                                OperandSize::Size32,
+                            ));
+                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::from(dst), dst));
+                        }
                         _ => unreachable!(),
                     },
                     Opcode::UwidenLow => match (input_ty, output_ty) {
@@ -4975,10 +4988,10 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                         (types::I16X8, types::I32X4) => {
                             ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::reg(src), dst));
                         }
-                        _ => unreachable!(
-                            "In UwidenLow: input_ty {:?}, output_ty {:?}",
-                            input_ty, output_ty
-                        ),
+                        (types::I32X4, types::I64X2) => {
+                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::reg(src), dst));
+                        }
+                        _ => unreachable!(),
                     },
                     Opcode::UwidenHigh => match (input_ty, output_ty) {
                         (types::I8X16, types::I16X8) => {
@@ -5003,6 +5016,16 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                             ));
                             ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::from(dst), dst));
                         }
+                        (types::I32X4, types::I64X2) => {
+                            ctx.emit(Inst::xmm_rm_r_imm(
+                                SseOpcode::Pshufd,
+                                RegMem::reg(src),
+                                dst,
+                                0xEE,
+                                OperandSize::Size32,
+                            ));
+                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::from(dst), dst));
+                        }
                         _ => unreachable!(),
                     },
                     _ => unreachable!(),