-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathREADME
272 lines (228 loc) · 10 KB
/
README
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
Copyright (C) Telecom ParisTech
This file must be used under the terms of the CeCILL.
This source file is licensed as described in the file COPYING, which
you should have received as part of this distribution. The terms
are also available at
http://www.cecill.info/licences/Licence_CeCILL_V2.1-en.txt
----------------------------
SIMPLE REGISTER DESIGN FILES
----------------------------
This directory and its sub-directories contain the VHDL source code, VHDL
simulation environment, simulation and synthesis scripts of a simple register
example for the Xilinx Zynq core.
Important note: the Makefiles and synthesis scripts rely on the HWPrj
infrastructure. Please download the HWPrj archive and unpack in the
simpleregister4zynq directory:
cd simpleregister4zynq
wget http://soc.eurecom.fr/EDC/hwprj.tgz
tar zxf hwprj.tgz
Alternately you can also fetch HWPrj from its git repository:
cd simpleregister4zynq
git submodule add [email protected]:renaud.pacalet/hwprj.git
Please see hwprj/README for explanations about HWPrj.
1) Content
----------
.
├── COPYING (Copyright notice and licences)
├── COPYING-FR (Copyright notice and licences)
├── COPYRIGHT (Copyright notice and licences)
├── hdl (HDL source files, scripts)
│ ├── axi (AXI protocol)
│ │ ├── axi_pkg.vhd
│ │ ├── dependencies.txt
│ │ └── Makefile
│ ├── axi_register (The simple register)
│ │ ├── axi_register.vhd
│ │ ├── axi_register_wrapper.vhd
│ │ ├── axi_register_wrapper.vsyn.tcl
│ │ ├── boot.bif
│ │ ├── dependencies.txt
│ │ ├── dts.hsi.tcl
│ │ ├── fsbl.hsi.tcl
│ │ └── Makefile
│ ├── global (Common utilities)
│ │ ├── dependencies.txt
│ │ ├── global.vhd
│ │ ├── Makefile
│ │ ├── numeric_std.vhd
│ │ ├── sim_utils_sim.vhd
│ │ ├── sim_utils.vhd
│ │ └── utils.vhd
│ └── random (Random generators)
│ ├── dependencies.txt
│ ├── Makefile
│ ├── random_pkg.vhd
│ └── rnd.vhd
├── Makefile (The main Makefile. Type 'make' to see the available targets).
└── README (This file)
hdl/axi:
The axi module (library axi_lib). Contains the axi_pkg package with
all AXI-related declarations.
hdl/axi_register:
The axi_register module (library axi_register_lib). The simple register and
its wrapper.
hdl/global:
The global module (library global_lib). Several general purpose packages.
hdl/random:
The random module (library random_lib). Random generators for simulation.
2) Short description
--------------------
The PL bitstream is that of a simple AXI-AXI bridge with two slave AXI ports,
one master AXI port, 8 internal 32-bits registers, an 8-bits general purpose
input and an 8 bits general purpose output:
+---+
|DDR|
+---+
^
|
---------+ +-------------------+ +-----------------|---
PS | | SIMPLE REGISTER | | PS v
| | | | +------+
M_AXI_GP1|<--->|S1_AXI<----->M_AXI |<--->|S_AXI_HP0<-->| DDR |
| | | | | Ctrl |
M_AXI_GP0|<--->|S0_AXI<-->REGs | | +------+
---------+ | | +---------------------
| |
Switches ---->|GPI GPO|----> LEDs
+-------------------+
The S1_AXI AXI slave port is forwarded to the M_AXI AXI master port. It is used
to access the DDR controller from the Processing System (PS) through the FPGA
fabric. The S0_AXI AXI slave port is used to access the internal registers. GPI
and GPO are general purpose 8 bits inputs and outputs. They are used for
debugging. GPI is typically connected to switches and GPO to LEDs. The mapping
of the S0_AXI address space is the following:
+------------+
0x40000000 | GPIR (ro) | General purpose input register (8 LSBs only, 24 MSBs reserved)
+------------+
0x40000004 | GPOR (rw) | General purpose output register (8 LSBs only, 24 MSBs reserved)
+------------+
Reserved bits read as zeroes and writing them has no effect. Writing a read-only
(ro) register returns a SLVERR response. Accessing an unmapped address returns a
DECERR response. The value of GPIR least significant byte is always equal to the
GPI input. The value of least significant byte of GPO depends on the value of
GPIR (and thus GPI):
+-------+-------------------------------------------------+
| GPIR | GPO |
+-------+-------------------------------------------------+
| 0x00 | GPOR |
+-------+-------------------------------------------------+
| other | 0x55 |
+-------+-------------------------------------------------+
Important note: thanks to the S1_AXI to M_AXI bridge the complete 1GB address
space 0x00000000 - 0x3FFFFFFF is also mapped to 0x80000000 - 0xBFFFFFFF. On
Zynq-based boards that do not map this entire GB (like, for instance, the
ZedBoard with only 512 MB of DDR), the unmapped region in 0x20000000 -
0x3FFFFFFF has a corresponding unmapped region in 0xA0000000 - 0xBFFFFFFF.
Accessing one or the other will raise errors. Moreover, depending on the
configuration, some Zynq systems have a reserved low addresses range that cannot
be accessed from the AXI_HP ports. In these systems this low range can be
accessed in the 0x00000000 - 0x3FFFFFFF range but not in the
0x80000000 - 0xBFFFFFFF range.
3) Building the whole example from scratch
------------------------------------------
#############################################################
# Fetch sources (if not already done, else simply git pull) #
#############################################################
export DISTRIB=<some-path>
export SIMPLEREGISTER4ZYNQ=$DISTRIB/simpleregister4zynq
export UBOOT=$DISTRIB/u-boot-xlnx
export KERNEL=$DISTRIB/linux-xlnx
export DEVICETREEXLNX=$DISTRIB/device-tree-xlnx
git clone --recursive [email protected]:renaud.pacalet/simpleregister4zynq.git $SIMPLEREGISTER4ZYNQ
git clone http://github.com/Xilinx/u-boot-xlnx.git $UBOOT
git clone http://github.com/Xilinx/linux-xlnx.git $KERNEL
git clone http://github.com/Xilinx/device-tree-xlnx.git $DEVICETREEXLNX
cd $DISTRIB
wget http://www.wiki.xilinx.com/file/view/arm_ramdisk.image.gz
##########
# U-Boot #
##########
cd $UBOOT
git pull
export CROSS_COMPILE=arm-xilinx-linux-gnueabi-
make distclean
rm -rf build
make O=build zynq_zed_config all
export PATH=$PATH:$UBOOT/build/tools
##########
# rootfs #
##########
# Note: to modify the root file system before building the image:
# cd $DISTRIB
# gunzip ramdisk.image.gz
# chmod u+rwx ramdisk.image
# mkdir tmp_mnt/
# sudo mount -o loop ramdisk.image tmp_mnt/
## Modify tmp_mnt/
# sudo umount tmp_mnt/
# gzip ramdisk.image
mkimage -A arm -T ramdisk -C gzip -d arm_ramdisk.image.gz uramdisk.image.gz
################
# Linux kernel #
################
cd $KERNEL
git pull
export CROSS_COMPILE=arm-xilinx-linux-gnueabi-
make distclean
make ARCH=arm xilinx_zynq_defconfig
make ARCH=arm menuconfig
make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage
export PATH=$KERNEL/scripts/dtc:$PATH
############################################
# Hardware and hardware dependant software #
############################################
export DESIGN=$SIMPLEREGISTER4ZYNQ/hdl/axi_register
cd $DESIGN
cp $UBOOT/build/u-boot u-boot.elf
make syn
make fsbl dtb bin
mkdir sdcard
cp axi_register_wrapper.vv-syn/top.sdk/dts/system.dtb sdcard
cp $KERNEL/arch/arm/boot/uImage sdcard
cp $DISTRIB/uramdisk.image.gz sdcard
cp boot.bin sdcard
4) Using the simple register on the ZedBoard
--------------------------------------------
a) Copy the provided files on a SD card:
cp boot.bin system.dtb uImage uramdisk.image.gz /media/SDCARD
sync
b) To avoid strange bugs, please cross-check the result of the copy:
- compute the md5sum of the provided files,
- copy the files on the SD card
- sync and un-mount the SD card
- mount the SD card again
- compute the md5sum of the SD card files and compare with the originals
c) Configure the ZedBoard jumpers to boot from SD card (set MIO4 and MIO5, unset
MIO2, MIO3 and MIO6), insert the SD card, plug the power and console USB
cable and power on.
d) Launch a terminal emulator like minicom (minicom -D /dev/ttyACM0) and stop
U-Boot by hitting the keyboard.
e) Set the following U-Boot environment variables:
setenv bootcmd 'run $modeboot'
setenv modeboot 'sdboot'
setenv sdboot 'fatload mmc 0 0x3000000 uImage && fatload mmc 0 0x2000000 uramdisk.image.gz && fatload mmc 0 0x2a00000 system.dtb && bootm 0x3000000 0x2000000 0x2a00000'
and save them on the QSPI flash:
saveenv
so that U-Boot remembers them for the next time.
f) Continue the boot sequence (boot), wait until Linux boots and start
interacting with the register (with devmem, for instance).
5) Example of experiments
-------------------------
# First test the design in the PL by setting the switches to any configuration
# other than 0x00 (e.g. 0x02) and looking at the LEDs: if the LEDs illuminate in
# the 0x55 configuration things are probably OK, else the PL does not work as
# expected.
# Reading the current status of the 8 switches:
zynq> devmem 0x40000000 32
0x00000002
# Illuminating the 8 LEDs (first set the switches to 0x00):
zynq> devmem 0x40000004 32 0xFF
# Reading in the external memory through the FPGA fabric:
zynq> devmem 0x90000000 32
# Power off
zynq> poweroff
The system is going down NOW!
Sent SIGTERM to all processes
Sent SIGKILL to all processes
Requesting system poweroff
reboot: System halted