minor cleanup on interrupt functions

digant73 · digant73 · commit 448f78203714 · 2025-02-08T20:04:31.000+01:00
diff --git a/TFT/src/User/Hal/buzzer.c b/TFT/src/User/Hal/buzzer.c
@@ -147,10 +147,8 @@ void Buzzer_AddSound(const uint16_t frequency, const uint16_t duration)
 
 void TIMER2_IRQHandler(void)  // GD32F2XX and GD32F3XX timer ISR
 {
-  if ((TIMER_INTF(TIMER2) & TIMER_INTF_UPIF) != 0)  // check for timer2 interrupt flag
+  if ((TIMER_INTF(TIMER2) & TIMER_INTF_UPIF) != 0)  // check for TIMER2 interrupt flag
   {
-    TIMER_INTF(TIMER2) &= ~TIMER_INTF_UPIF;         // clear interrupt flag
-
     if (buzzer.toggles > 0)                           // if a sound has to be played
     {
       buzzer.toggles--;
@@ -168,6 +166,8 @@ void TIMER2_IRQHandler(void)  // GD32F2XX and GD32F3XX timer ISR
         buzzer.toggles++;               // silence, no toggling, only counting
       }
     }
+
+    TIMER_INTF(TIMER2) &= ~TIMER_INTF_UPIF;  // as last, clear TIMER2 interrupt flag
   }
 }
 
@@ -177,8 +177,6 @@ void TIM3_IRQHandler(void)  // STM32FXX timer ISR
 {
   if ((TIM3->SR & TIM_SR_UIF) != 0)  // check for TIM3 interrupt flag
   {
-    TIM3->SR &= ~TIM_SR_UIF;         // clear interrupt flag
-
     if (buzzer.toggles > 0)                           // if a sound has to be played
     {
       buzzer.toggles--;
@@ -196,6 +194,8 @@ void TIM3_IRQHandler(void)  // STM32FXX timer ISR
         buzzer.toggles++;            // silence, no toggling, only counting
       }
     }
+
+    TIM3->SR &= ~TIM_SR_UIF;  // as last, clear TIM3 interrupt flag
   }
 }
 
diff --git a/TFT/src/User/Hal/gd32f20x/Serial.c b/TFT/src/User/Hal/gd32f20x/Serial.c
@@ -274,40 +274,40 @@ void Serial_Put(uint8_t port, const char * msg)
 void USART_IRQHandler(uint8_t port)
 {
   #if IDLE_LINE_IT == true  // IDLE Line interrupt
-    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_IDLEF) != RESET)  // check for IDLE Line interrupt
+    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_IDLEF) != RESET)  // check for IDLE Line interrupt flag
     {
-      USART_STAT0(Serial[port].uart);                                   // clear IDLE Line bit
-      USART_DATA(Serial[port].uart);
-
       dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - DMA_CHCNT(Serial[port].dma_stream, Serial[port].dma_channelRX);
+
+      USART_DATA(Serial[port].uart);                                    // clear RXNE pending flag
+      USART_STAT0(Serial[port].uart);                                   // as last, clear IDLE Line interrupt flag
     }
   #endif
 
   #ifdef TX_DMA_WRITE  // TX DMA based serial writing
-    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TC) != RESET)  // check for Transfer Complete (TC) interrupt
+    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TC) != RESET)             // check for Transfer Complete (TC) interrupt flag
     {
-      USART_STAT0(Serial[port].uart) &= ~USART_STAT0_TC;             // clear Transfer Complete (TC) bit
-
       // NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy
       // NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!
       //
       if (DMA_CHCNT(Serial[port].dma_stream, Serial[port].dma_channelTX) == 0)  // sending is complete
       {
         // NOTE: it marks message timestamp twice if transfer was split into 2 parts
-        dmaL1DataTX[port].timestamp = OS_GetTimeMs();              // keep track of last sent message timestamp
+        dmaL1DataTX[port].timestamp = OS_GetTimeMs();                           // keep track of last sent message timestamp
 
         dmaL1DataTX[port].rIndex = (dmaL1DataTX[port].rIndex + dmaL1DataTX[port].flag) % dmaL1DataTX[port].cacheSize;
         dmaL1DataTX[port].flag = 0;
 
-        if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex)  // is more data available?
-          Serial_Send_TX(port);                                    // continue sending data
+        if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex)               // is more data available?
+          Serial_Send_TX(port);                                                 // continue sending data
         else
-          USART_CTL0(Serial[port].uart) &= ~USART_CTL0_TCIE;       // disable Transfer Complete (TC) interrupt, nothing more to do
+          USART_CTL0(Serial[port].uart) &= ~USART_CTL0_TCIE;                    // disable Transfer Complete (TC) interrupt, nothing more to do
       }
       // else: more data is coming, wait for next Transfer Complete (TC) interrupt
+
+      USART_STAT0(Serial[port].uart) &= ~USART_STAT0_TC;                        // as last, clear Transfer Complete (TC) interrupt flag
     }
   #else  // TX interrupt based serial writing
-    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TBE) != RESET)                                  // check for TBE interrupt
+    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TBE) != RESET)                                  // check for TBE interrupt flag
     {
       if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex)                                       // is more data available?
       {
diff --git a/TFT/src/User/Hal/gd32f30x/Serial.c b/TFT/src/User/Hal/gd32f30x/Serial.c
@@ -264,40 +264,40 @@ void Serial_Put(uint8_t port, const char * msg)
 void USART_IRQHandler(uint8_t port)
 {
   #if IDLE_LINE_IT == true  // IDLE Line interrupt
-    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_IDLEF) != RESET)  // check for IDLE Line interrupt
+    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_IDLEF) != RESET)  // check for IDLE Line interrupt flag
     {
-      USART_STAT0(Serial[port].uart);                                   // clear IDLE Line bit
-      USART_DATA(Serial[port].uart);
-
       dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - DMA_CHCNT(Serial[port].dma_stream, Serial[port].dma_channelRX);
+
+      USART_DATA(Serial[port].uart);                                    // clear RXNE pending flag
+      USART_STAT0(Serial[port].uart);                                   // as last, clear IDLE Line interrupt flag
     }
   #endif
 
   #ifdef TX_DMA_WRITE  // TX DMA based serial writing
-    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TC) != RESET)  // check for Transfer Complete (TC) interrupt
+    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TC) != RESET)             // check for Transfer Complete (TC) interrupt flag
     {
-      USART_STAT0(Serial[port].uart) &= ~USART_STAT0_TC;             // clear Transfer Complete (TC) bit
-
       // NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy
       // NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!
       //
       if (DMA_CHCNT(Serial[port].dma_stream, Serial[port].dma_channelTX) == 0)  // sending is complete
       {
         // NOTE: it marks message timestamp twice if transfer was split into 2 parts
-        dmaL1DataTX[port].timestamp = OS_GetTimeMs();              // keep track of last sent message timestamp
+        dmaL1DataTX[port].timestamp = OS_GetTimeMs();                           // keep track of last sent message timestamp
 
         dmaL1DataTX[port].rIndex = (dmaL1DataTX[port].rIndex + dmaL1DataTX[port].flag) % dmaL1DataTX[port].cacheSize;
         dmaL1DataTX[port].flag = 0;
 
-        if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex)  // is more data available?
-          Serial_Send_TX(port);                                    // continue sending data
+        if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex)               // is more data available?
+          Serial_Send_TX(port);                                                 // continue sending data
         else
-          USART_CTL0(Serial[port].uart) &= ~USART_CTL0_TCIE;       // disable Transfer Complete (TC) interrupt, nothing more to do
+          USART_CTL0(Serial[port].uart) &= ~USART_CTL0_TCIE;                    // disable Transfer Complete (TC) interrupt, nothing more to do
       }
       // else: more data is coming, wait for next Transfer Complete (TC) interrupt
+
+      USART_STAT0(Serial[port].uart) &= ~USART_STAT0_TC;                        // as last, clear Transfer Complete (TC) interrupt flag
     }
   #else  // TX interrupt based serial writing
-    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TBE) != RESET)                                  // check for TBE interrupt
+    if ((USART_STAT0(Serial[port].uart) & USART_STAT0_TBE) != RESET)                                  // check for TBE interrupt flag
     {
       if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex)                                       // is more data available?
       {
diff --git a/TFT/src/User/Hal/stm32f10x/Serial.c b/TFT/src/User/Hal/stm32f10x/Serial.c
@@ -241,20 +241,18 @@ void Serial_Put(uint8_t port, const char * msg)
 void USART_IRQHandler(uint8_t port)
 {
   #if IDLE_LINE_IT == true  // IDLE Line interrupt
-    if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET)  // check for IDLE Line interrupt
+    if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET)  // check for IDLE Line interrupt flag
     {
-      Serial[port].uart->SR;                               // clear IDLE Line bit
-      Serial[port].uart->DR;
+      dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_streamRX->NDTR;
 
-      dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_channelRX->CNDTR;
+      Serial[port].uart->DR;                               // clear RXNE pending flag
+      Serial[port].uart->SR;                               // as last, clear IDLE Line interrupt flag
     }
   #endif
 
   #ifdef TX_DMA_WRITE  // TX DMA based serial writing
-    if ((Serial[port].uart->SR & USART_SR_TC) != RESET)  // check for Transfer Complete (TC) interrupt
+    if ((Serial[port].uart->SR & USART_SR_TC) != RESET)            // check for Transfer Complete (TC) interrupt flag
     {
-      Serial[port].uart->SR &= ~USART_SR_TC;             // clear Transfer Complete (TC) bit
-
       // NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy
       // NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!
       //
@@ -272,9 +270,11 @@ void USART_IRQHandler(uint8_t port)
           Serial[port].uart->CR1 &= ~USART_CR1_TCIE;               // disable Transfer Complete (TC) interrupt, nothing more to do
       }
       // else: more data is coming, wait for next Transfer Complete (TC) interrupt
+
+      Serial[port].uart->SR &= ~USART_SR_TC;                       // as last, clear Transfer Complete (TC) interrupt flag
     }
   #else  // TX interrupt based serial writing
-    if ((Serial[port].uart->SR & USART_SR_TXE) != RESET)                                          // check for TXE interrupt
+    if ((Serial[port].uart->SR & USART_SR_TXE) != RESET)                                          // check for TXE interrupt flag
     {
       if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex)                                   // is more data available?
       {
diff --git a/TFT/src/User/Hal/stm32f2_f4xx/Serial.c b/TFT/src/User/Hal/stm32f2_f4xx/Serial.c
@@ -292,20 +292,18 @@ void Serial_Put(uint8_t port, const char * msg)
 void USART_IRQHandler(uint8_t port)
 {
   #if IDLE_LINE_IT == true  // IDLE Line interrupt
-    if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET)  // check for IDLE Line interrupt
+    if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET)  // check for IDLE Line interrupt flag
     {
-      Serial[port].uart->SR;                               // clear IDLE Line bit
-      Serial[port].uart->DR;
-
       dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_streamRX->NDTR;
+
+      Serial[port].uart->DR;                               // clear RXNE pending flag
+      Serial[port].uart->SR;                               // as last, clear IDLE Line interrupt flag
     }
   #endif
 
   #ifdef TX_DMA_WRITE  // TX DMA based serial writing
-    if ((Serial[port].uart->SR & USART_SR_TC) != RESET)  // check for Transfer Complete (TC) interrupt
+    if ((Serial[port].uart->SR & USART_SR_TC) != RESET)            // check for Transfer Complete (TC) interrupt flag
     {
-      Serial[port].uart->SR &= ~USART_SR_TC;             // clear Transfer Complete (TC) bit
-
       // NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy
       // NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!
       //
@@ -323,9 +321,11 @@ void USART_IRQHandler(uint8_t port)
           Serial[port].uart->CR1 &= ~USART_CR1_TCIE;               // disable Transfer Complete (TC) interrupt, nothing more to do
       }
       // else: more data is coming, wait for next Transfer Complete (TC) interrupt
+
+      Serial[port].uart->SR &= ~USART_SR_TC;                       // as last, clear Transfer Complete (TC) interrupt flag
     }
   #else  // TX interrupt based serial writing
-    if ((Serial[port].uart->SR & USART_SR_TXE) != RESET)                                          // check for TXE interrupt
+    if ((Serial[port].uart->SR & USART_SR_TXE) != RESET)                                          // check for TXE interrupt flag
     {
       if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex)                                   // is more data available?
       {
diff --git a/TFT/src/User/os_timer.c b/TFT/src/User/os_timer.c
@@ -36,10 +36,8 @@ void OS_InitTimerMs(void)
 
 void TIMER6_IRQHandler(void)
 {
-  if ((TIMER_INTF(TIMER6) & TIMER_INTF_UPIF) != 0)
+  if ((TIMER_INTF(TIMER6) & TIMER_INTF_UPIF) != 0)  // check for TIMER6 interrupt flag
   {
-    TIMER_INTF(TIMER6) &= ~TIMER_INTF_UPIF;  // clear interrupt flag
-
     os_counter.ms++;
     os_counter.sec--;
 
@@ -53,17 +51,17 @@ void TIMER6_IRQHandler(void)
     }
 
     TS_CheckPress();  // check touch screen once a millisecond
+
+    TIMER_INTF(TIMER6) &= ~TIMER_INTF_UPIF;  // as last, clear TIMER6 interrupt flag
   }
 }
 
 #else
 
 void TIM7_IRQHandler(void)
 {
-  if ((TIM7->SR & TIM_SR_UIF) != 0)
+  if ((TIM7->SR & TIM_SR_UIF) != 0)  // check for TIM7 interrupt flag
   {
-    TIM7->SR &= ~TIM_SR_UIF;  // clear interrupt flag
-
     os_counter.ms++;
     os_counter.sec--;
 
@@ -77,6 +75,8 @@ void TIM7_IRQHandler(void)
     }
 
     TS_CheckPress();  // check touch screen once a millisecond
+
+    TIM7->SR &= ~TIM_SR_UIF;  // as last, clear TIM7 interrupt flag
   }
 }
 

Original file line number	Diff line number	Diff line change
`@@ -147,10 +147,8 @@ void Buzzer_AddSound(const uint16_t frequency, const uint16_t duration)`
`147`	`147`
`148`	`148`	`void TIMER2_IRQHandler(void) // GD32F2XX and GD32F3XX timer ISR`
`149`	`149`	`{`
`150`		`- if ((TIMER_INTF(TIMER2) & TIMER_INTF_UPIF) != 0) // check for timer2 interrupt flag`
	`150`	`+ if ((TIMER_INTF(TIMER2) & TIMER_INTF_UPIF) != 0) // check for TIMER2 interrupt flag`
`151`	`151`	`{`
`152`		`- TIMER_INTF(TIMER2) &= ~TIMER_INTF_UPIF; // clear interrupt flag`
`153`		`-`
`154`	`152`	`if (buzzer.toggles > 0) // if a sound has to be played`
`155`	`153`	`{`
`156`	`154`	`buzzer.toggles--;`
`@@ -168,6 +166,8 @@ void TIMER2_IRQHandler(void) // GD32F2XX and GD32F3XX timer ISR`
`168`	`166`	`buzzer.toggles++; // silence, no toggling, only counting`
`169`	`167`	`}`
`170`	`168`	`}`
	`169`	`+`
	`170`	`+ TIMER_INTF(TIMER2) &= ~TIMER_INTF_UPIF; // as last, clear TIMER2 interrupt flag`
`171`	`171`	`}`
`172`	`172`	`}`
`173`	`173`
`@@ -177,8 +177,6 @@ void TIM3_IRQHandler(void) // STM32FXX timer ISR`
`177`	`177`	`{`
`178`	`178`	`if ((TIM3->SR & TIM_SR_UIF) != 0) // check for TIM3 interrupt flag`
`179`	`179`	`{`
`180`		`- TIM3->SR &= ~TIM_SR_UIF; // clear interrupt flag`
`181`		`-`
`182`	`180`	`if (buzzer.toggles > 0) // if a sound has to be played`
`183`	`181`	`{`
`184`	`182`	`buzzer.toggles--;`
`@@ -196,6 +194,8 @@ void TIM3_IRQHandler(void) // STM32FXX timer ISR`
`196`	`194`	`buzzer.toggles++; // silence, no toggling, only counting`
`197`	`195`	`}`
`198`	`196`	`}`
	`197`	`+`
	`198`	`+ TIM3->SR &= ~TIM_SR_UIF; // as last, clear TIM3 interrupt flag`
`199`	`199`	`}`
`200`	`200`	`}`
`201`	`201`
Original file line number	Diff line number	Diff line change
`@@ -241,20 +241,18 @@ void Serial_Put(uint8_t port, const char * msg)`
`241`	`241`	`void USART_IRQHandler(uint8_t port)`
`242`	`242`	`{`
`243`	`243`	`#if IDLE_LINE_IT == true // IDLE Line interrupt`
`244`		`- if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET) // check for IDLE Line interrupt`
	`244`	`+ if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET) // check for IDLE Line interrupt flag`
`245`	`245`	`{`
`246`		`- Serial[port].uart->SR; // clear IDLE Line bit`
`247`		`- Serial[port].uart->DR;`
	`246`	`+ dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_streamRX->NDTR;`
`248`	`247`
`249`		`- dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_channelRX->CNDTR;`
	`248`	`+ Serial[port].uart->DR; // clear RXNE pending flag`
	`249`	`+ Serial[port].uart->SR; // as last, clear IDLE Line interrupt flag`
`250`	`250`	`}`
`251`	`251`	`#endif`
`252`	`252`
`253`	`253`	`#ifdef TX_DMA_WRITE // TX DMA based serial writing`
`254`		`- if ((Serial[port].uart->SR & USART_SR_TC) != RESET) // check for Transfer Complete (TC) interrupt`
	`254`	`+ if ((Serial[port].uart->SR & USART_SR_TC) != RESET) // check for Transfer Complete (TC) interrupt flag`
`255`	`255`	`{`
`256`		`- Serial[port].uart->SR &= ~USART_SR_TC; // clear Transfer Complete (TC) bit`
`257`		`-`
`258`	`256`	`// NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy`
`259`	`257`	`// NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!`
`260`	`258`	`//`
`@@ -272,9 +270,11 @@ void USART_IRQHandler(uint8_t port)`
`272`	`270`	`Serial[port].uart->CR1 &= ~USART_CR1_TCIE; // disable Transfer Complete (TC) interrupt, nothing more to do`
`273`	`271`	`}`
`274`	`272`	`// else: more data is coming, wait for next Transfer Complete (TC) interrupt`
	`273`	`+`
	`274`	`+ Serial[port].uart->SR &= ~USART_SR_TC; // as last, clear Transfer Complete (TC) interrupt flag`
`275`	`275`	`}`
`276`	`276`	`#else // TX interrupt based serial writing`
`277`		`- if ((Serial[port].uart->SR & USART_SR_TXE) != RESET) // check for TXE interrupt`
	`277`	`+ if ((Serial[port].uart->SR & USART_SR_TXE) != RESET) // check for TXE interrupt flag`
`278`	`278`	`{`
`279`	`279`	`if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?`
`280`	`280`	`{`
Original file line number	Diff line number	Diff line change
`@@ -292,20 +292,18 @@ void Serial_Put(uint8_t port, const char * msg)`
`292`	`292`	`void USART_IRQHandler(uint8_t port)`
`293`	`293`	`{`
`294`	`294`	`#if IDLE_LINE_IT == true // IDLE Line interrupt`
`295`		`- if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET) // check for IDLE Line interrupt`
	`295`	`+ if ((Serial[port].uart->SR & USART_SR_IDLE) != RESET) // check for IDLE Line interrupt flag`
`296`	`296`	`{`
`297`		`- Serial[port].uart->SR; // clear IDLE Line bit`
`298`		`- Serial[port].uart->DR;`
`299`		`-`
`300`	`297`	`dmaL1DataRX[port].wIndex = dmaL1DataRX[port].cacheSize - Serial[port].dma_streamRX->NDTR;`
	`298`	`+`
	`299`	`+ Serial[port].uart->DR; // clear RXNE pending flag`
	`300`	`+ Serial[port].uart->SR; // as last, clear IDLE Line interrupt flag`
`301`	`301`	`}`
`302`	`302`	`#endif`
`303`	`303`
`304`	`304`	`#ifdef TX_DMA_WRITE // TX DMA based serial writing`
`305`		`- if ((Serial[port].uart->SR & USART_SR_TC) != RESET) // check for Transfer Complete (TC) interrupt`
	`305`	`+ if ((Serial[port].uart->SR & USART_SR_TC) != RESET) // check for Transfer Complete (TC) interrupt flag`
`306`	`306`	`{`
`307`		`- Serial[port].uart->SR &= ~USART_SR_TC; // clear Transfer Complete (TC) bit`
`308`		`-`
`309`	`307`	`// NOTE 1: use the serial TC, not the DMA TC because this only indicates DMA is done, peripheral might be still busy`
`310`	`308`	`// NOTE 2: the TC interrupt is sometimes called while DMA is still active, so check NDTR status!`
`311`	`309`	`//`
`@@ -323,9 +321,11 @@ void USART_IRQHandler(uint8_t port)`
`323`	`321`	`Serial[port].uart->CR1 &= ~USART_CR1_TCIE; // disable Transfer Complete (TC) interrupt, nothing more to do`
`324`	`322`	`}`
`325`	`323`	`// else: more data is coming, wait for next Transfer Complete (TC) interrupt`
	`324`	`+`
	`325`	`+ Serial[port].uart->SR &= ~USART_SR_TC; // as last, clear Transfer Complete (TC) interrupt flag`
`326`	`326`	`}`
`327`	`327`	`#else // TX interrupt based serial writing`
`328`		`- if ((Serial[port].uart->SR & USART_SR_TXE) != RESET) // check for TXE interrupt`
	`328`	`+ if ((Serial[port].uart->SR & USART_SR_TXE) != RESET) // check for TXE interrupt flag`
`329`	`329`	`{`
`330`	`330`	`if (dmaL1DataTX[port].rIndex != dmaL1DataTX[port].wIndex) // is more data available?`
`331`	`331`	`{`
Original file line number	Diff line number	Diff line change
`@@ -36,10 +36,8 @@ void OS_InitTimerMs(void)`
`36`	`36`
`37`	`37`	`void TIMER6_IRQHandler(void)`
`38`	`38`	`{`
`39`		`- if ((TIMER_INTF(TIMER6) & TIMER_INTF_UPIF) != 0)`
	`39`	`+ if ((TIMER_INTF(TIMER6) & TIMER_INTF_UPIF) != 0) // check for TIMER6 interrupt flag`
`40`	`40`	`{`
`41`		`- TIMER_INTF(TIMER6) &= ~TIMER_INTF_UPIF; // clear interrupt flag`
`42`		`-`
`43`	`41`	`os_counter.ms++;`
`44`	`42`	`os_counter.sec--;`
`45`	`43`
`@@ -53,17 +51,17 @@ void TIMER6_IRQHandler(void)`
`53`	`51`	`}`
`54`	`52`
`55`	`53`	`TS_CheckPress(); // check touch screen once a millisecond`
	`54`	`+`
	`55`	`+ TIMER_INTF(TIMER6) &= ~TIMER_INTF_UPIF; // as last, clear TIMER6 interrupt flag`
`56`	`56`	`}`
`57`	`57`	`}`
`58`	`58`
`59`	`59`	`#else`
`60`	`60`
`61`	`61`	`void TIM7_IRQHandler(void)`
`62`	`62`	`{`
`63`		`- if ((TIM7->SR & TIM_SR_UIF) != 0)`
	`63`	`+ if ((TIM7->SR & TIM_SR_UIF) != 0) // check for TIM7 interrupt flag`
`64`	`64`	`{`
`65`		`- TIM7->SR &= ~TIM_SR_UIF; // clear interrupt flag`
`66`		`-`
`67`	`65`	`os_counter.ms++;`
`68`	`66`	`os_counter.sec--;`
`69`	`67`
`@@ -77,6 +75,8 @@ void TIM7_IRQHandler(void)`
`77`	`75`	`}`
`78`	`76`
`79`	`77`	`TS_CheckPress(); // check touch screen once a millisecond`
	`78`	`+`
	`79`	`+ TIM7->SR &= ~TIM_SR_UIF; // as last, clear TIM7 interrupt flag`
`80`	`80`	`}`
`81`	`81`	`}`
`82`	`82`