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device.cpp
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#include <cassert>
#include <climits>
#include <boost/property_tree/ptree.hpp>
#include <boost/property_tree/exceptions.hpp>
#include "device.h"
#include "log.h"
static Log::StaticLogger logger("device");
static Log::StaticLogger logger_asm("asm");
#define LOG_OPCODE(f, ...) SPDLOG_DEBUG(logger_asm, "PC:{:05X} SP:{:04X} OP:{:04X} " f, cpu_.pc_, cpu_.sp_, opcode, ## __VA_ARGS__);
struct OpcodeDetail
{
/// Return true for 2-word instructions
static constexpr bool opcode_is_32b(uint16_t opcode)
{
// 2-word instructions are JMP, CALL, LDS, STS
return (opcode & 0xFE0C) == 0x940C || (opcode & 0xFC0F) == 0x9000;
}
// NOPE
static unsigned int op_nope(Device& device, uint16_t) {
LOG_OPCODE("NOPE");
device.cpu_.pc_++;
return 1;
}
// BSET, SE{C,Z,N,V,S,H,T,I}
static unsigned int op_bset(Device& device, uint16_t opcode) {
const uint8_t s = (opcode >> 4) & 7;
LOG_OPCODE("BSET {}", s);
device.cpu_.sreg_.data |= (1 << s);
device.cpu_.pc_++;
return 1;
}
// BCLR, CL{C,Z,N,V,S,H,T,I}
static unsigned int op_bclr(Device& device, uint16_t opcode) {
const uint8_t s = (opcode >> 4) & 7;
LOG_OPCODE("BCLR {}", s);
device.cpu_.sreg_.data &= ~(1 << s);
device.cpu_.pc_++;
return 1;
}
// SBI
static unsigned int op_sbi(Device& device, uint16_t opcode) {
const uint8_t a = (opcode >> 3) & 0x1F;
const uint8_t b = opcode & 7;
LOG_OPCODE("SBI 0x{},{}", a, b);
//TODO this changes the whole byte, not just one bit
device.setIoMem(a, device.getIoMem(a) | (1 <<b));
device.cpu_.pc_++;
return 1;
}
// CBI
static unsigned int op_cbi(Device& device, uint16_t opcode) {
const uint8_t a = (opcode >> 3) & 0x1F;
const uint8_t b = opcode & 7;
LOG_OPCODE("CBI 0x{},{}", a, b);
//TODO this changes the whole byte, not just one bit
device.setIoMem(a, device.getIoMem(a) & ~(1 <<b));
device.cpu_.pc_++;
return 1;
}
// COM
static unsigned int op_com(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = 0xFF - Rd;
LOG_OPCODE("COM r{}", d);
device.cpu_.sreg_.C = 1;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = 0;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// NEG
static unsigned int op_neg(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = (0x100 - Rd) & 0xFF;
LOG_OPCODE("NEG r{}", d);
device.cpu_.sreg_.C = R != 0;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = R == 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = (R & Rd) & 0x08;
device.cpu_.pc_++;
return 1;
}
// SWAP
static unsigned int op_swap(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
LOG_OPCODE("SWAP r{}", d);
device.regfile_[d] = ((Rd & 0x0F) << 4) | ((Rd & 0xF0) >> 4);
device.cpu_.pc_++;
return 1;
}
// INC
static unsigned int op_inc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t R = ++device.regfile_[d];
LOG_OPCODE("INC r{}", d);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = R == 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// ASR
static unsigned int op_asr(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = (Rd >> 1) | (Rd & 0x80);
LOG_OPCODE("ASR r{}", d);
device.cpu_.sreg_.C = Rd & 1;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = device.cpu_.sreg_.N ^ device.cpu_.sreg_.C;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// LSR
static unsigned int op_lsr(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = (Rd >> 1);
LOG_OPCODE("LSR r{}", d);
device.cpu_.sreg_.C = Rd & 1;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = 0;
device.cpu_.sreg_.V = device.cpu_.sreg_.N ^ device.cpu_.sreg_.C;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// ROR
static unsigned int op_ror(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = (Rd >> 1) | (device.cpu_.sreg_.C << 7);
LOG_OPCODE("ROR r{}", d);
device.cpu_.sreg_.C = Rd & 1;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = device.cpu_.sreg_.N ^ device.cpu_.sreg_.C;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// DEC
static unsigned int op_dec(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t R = --device.regfile_[d];
LOG_OPCODE("DEC r{}", d);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = R == 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// CP
static unsigned int op_cp(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = Rd - Rr;
LOG_OPCODE("CP r{},r{}", d, r);
device.cpu_.sreg_.C = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & ~Rr & ~R) | (~Rd & Rr & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// CPC
static unsigned int op_cpc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = Rd - Rr - device.cpu_.sreg_.C;
LOG_OPCODE("CPC r{},r{}", d, r);
device.cpu_.sreg_.C = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0 && device.cpu_.sreg_.Z;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & ~Rr & ~R) | (~Rd & Rr & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// ADD, LSL
static unsigned int op_add_lsl(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = device.regfile_[d] = Rd + Rr;
LOG_OPCODE("ADD r{},r{}", d, r);
device.cpu_.sreg_.C = ((Rd & Rr) | (Rr & ~R) | (~R & Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & Rr & ~R) | (~Rd & ~Rr & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((Rd & Rr) | (Rr & ~R) | (~R & Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// ADC, ROL
static unsigned int op_adc_rol(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = device.regfile_[d] = Rd + Rr + device.cpu_.sreg_.C;
LOG_OPCODE("ADC r{},r{}", d, r);
device.cpu_.sreg_.C = ((Rd & Rr) | (Rr & ~R) | (~R & Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & Rr & ~R) | (~Rd & ~Rr & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((Rd & Rr) | (Rr & ~R) | (~R & Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// SUB
static unsigned int op_sub(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = device.regfile_[d] = Rd - Rr;
LOG_OPCODE("SUB r{},r{}", d, r);
device.cpu_.sreg_.C = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & ~Rr & ~R) | (~Rd & Rr & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// SBC
static unsigned int op_sbc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = device.regfile_[d] = Rd - Rr - device.cpu_.sreg_.C;
LOG_OPCODE("SBC r{},r{}", d, r);
device.cpu_.sreg_.C = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & ~Rr & ~R) | (~Rd & Rr & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((~Rd & Rr) | (Rr & R) | (R & ~Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// MUL
static unsigned int op_mul(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint16_t R = Rd * Rr;
LOG_OPCODE("MUL r{},r{}", d, r);
device.reg01_ = R;
device.cpu_.sreg_.C = R & 0x8000;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.pc_++;
return 2;
}
// MULS
static unsigned int op_muls(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
const uint8_t r = (opcode & 0xF) | 0x10; // 16 <= r <= 31
const int16_t Rd = u8_to_s16(device.regfile_[d]);
const int16_t Rr = u8_to_s16(device.regfile_[r]);
const uint16_t R = Rd * Rr;
LOG_OPCODE("MULS r{},r{}", d, r);
device.reg01_ = R;
device.cpu_.sreg_.C = R & 0x8000;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.pc_++;
return 2;
}
// MULSU
static unsigned int op_mulsu(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0x7) | 0x10; // 16 <= d <= 23
const uint8_t r = (opcode & 0x7) | 0x10; // 16 <= r <= 23
const int16_t Rd = u8_to_s16(device.regfile_[d]);
const uint8_t Rr = device.regfile_[r];
const uint16_t R = Rd * Rr;
LOG_OPCODE("MULSU r{},r{}", d, r);
device.reg01_ = R;
device.cpu_.sreg_.C = R & 0x8000;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.pc_++;
return 2;
}
// FMUL
static unsigned int op_fmul(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0x7) | 0x10; // 16 <= d <= 23
const uint8_t r = (opcode & 0x7) | 0x10; // 16 <= r <= 23
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
uint16_t R = Rd * Rr;
LOG_OPCODE("FMUL r{},r{}", d, r);
device.cpu_.sreg_.C = R & 0x8000; // before left shift
device.reg01_ = (R <<= 1);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.pc_++;
return 2;
}
// FMULS
static unsigned int op_fmuls(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0x7) | 0x10; // 16 <= d <= 23
const uint8_t r = (opcode & 0x7) | 0x10; // 16 <= r <= 23
const int16_t Rd = u8_to_s16(device.regfile_[d]);
const int16_t Rr = u8_to_s16(device.regfile_[r]);
uint16_t R = Rd * Rr;
LOG_OPCODE("FMULS r{},r{}", d, r);
device.cpu_.sreg_.C = R & 0x8000; // before left shift
device.reg01_ = (R <<= 1);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.pc_++;
return 2;
}
// FMULSU
static unsigned int op_fmulsu(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0x7) | 0x10; // 16 <= d <= 23
const uint8_t r = (opcode & 0x7) | 0x10; // 16 <= r <= 23
const int16_t Rd = u8_to_s16(device.regfile_[d]);
const uint8_t Rr = device.regfile_[r];
uint16_t R = Rd * Rr;
LOG_OPCODE("FMULSU r{},r{}", d, r);
device.cpu_.sreg_.C = R & 0x8000; // before left shift
device.reg01_ = (R <<= 1);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.pc_++;
return 2;
}
// AND, TST
static unsigned int op_and_tst(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = device.regfile_[d] = Rd & Rr;
LOG_OPCODE("AND r{},r{}", d, r);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = 0;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// EOR, CLR
static unsigned int op_eor_clr(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = device.regfile_[d] = Rd ^ Rr;
LOG_OPCODE("EOR r{},r{}", d, r);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = 0;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// OR
static unsigned int op_or(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
const uint8_t Rd = device.regfile_[d];
const uint8_t Rr = device.regfile_[r];
const uint8_t R = device.regfile_[d] = Rd | Rr;
LOG_OPCODE("OR r{},r{}", d, r);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = 0;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// MOV
static unsigned int op_mov(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t r = (opcode & 0xF) | ((opcode >> 5) & 0x10);
LOG_OPCODE("MOV r{},r{}", d, r);
device.regfile_[d] = device.regfile_[r];
device.cpu_.pc_++;
return 1;
}
// CPI
static unsigned int op_cpi(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
const uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
const uint8_t Rd = device.regfile_[d];
const uint8_t R = Rd - K;
LOG_OPCODE("CPI r{},0x{:02X}", d, K);
device.cpu_.sreg_.C = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & ~K & ~R) | (~Rd & K & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// SUBI
static unsigned int op_subi(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
const uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = Rd - K;
LOG_OPCODE("SUBI r{},0x{:02X}", d, K);
device.cpu_.sreg_.C = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & ~K & ~R) | (~Rd & K & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// SBCI
static unsigned int op_sbci(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
const uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = Rd - K - device.cpu_.sreg_.C;
LOG_OPCODE("SBCI r{},0x{:02X}", d, K);
device.cpu_.sreg_.C = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x80;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = ((Rd & ~K & ~R) | (~Rd & K & R)) & 0x80;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.sreg_.H = ((~Rd & K) | (K & R) | (R & ~Rd)) & 0x08;
device.cpu_.pc_++;
return 1;
}
// ANDI, CBR
static unsigned int op_andi_cbr(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
const uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = Rd & K;
LOG_OPCODE("ANDI r{},0x{:02X}", d, K);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = 0;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// ORI, SBR
static unsigned int op_ori_sbr(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
const uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
const uint8_t Rd = device.regfile_[d];
const uint8_t R = device.regfile_[d] = Rd | K;
LOG_OPCODE("ORI r{},0x{:02X}", d, K);
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x80;
device.cpu_.sreg_.V = 0;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// MOVW
static unsigned int op_movw(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 3) & 0x1E);
const uint8_t r = (opcode & 0xF) << 1;
LOG_OPCODE("MOVW r{}:r{},r{}:r{}", d, d+1, r, r+1);
register_set<16>(&device.regfile_[d], register_get<16>(&device.regfile_[r]));
device.cpu_.pc_++;
return 1;
}
// ADIW
static unsigned int op_adiw(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 3) & 0x6) + 24;
const uint8_t K = (opcode & 0xF) | ((opcode >> 2) & 0x30);
const uint16_t Rd = register_get<16>(&device.regfile_[d]);
const uint16_t R = Rd + K;
LOG_OPCODE("ADIW r{}:r{},0x{:02X}", d, d+1, K);
register_set<16>(&device.regfile_[d], R);
device.cpu_.sreg_.C = (~R & Rd) & 0x8000;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x8000;
device.cpu_.sreg_.V = (R & ~Rd) & 0x8000;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// SBIW
static unsigned int op_sbiw(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 3) & 0x6) + 24;
const uint8_t K = (opcode & 0xF) | ((opcode >> 2) & 0x30);
const uint16_t Rd = register_get<16>(&device.regfile_[d]);
const uint16_t R = Rd - K;
LOG_OPCODE("SBIW r{},0x{:02X}", d, K);
register_set<16>(&device.regfile_[d], R);
device.cpu_.sreg_.C = (R & ~Rd) & 0x8000;
device.cpu_.sreg_.Z = R == 0;
device.cpu_.sreg_.N = R & 0x8000;
device.cpu_.sreg_.V = (R & ~Rd) & 0x8000;
device.cpu_.sreg_.S = device.cpu_.sreg_.N ^ device.cpu_.sreg_.V;
device.cpu_.pc_++;
return 1;
}
// BLD
static unsigned int op_bld(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t b = opcode & 7;
LOG_OPCODE("BLD r{},{}", d, b);
device.regfile_[d] = (device.regfile_[d] & ~(1 << b)) | (device.cpu_.sreg_.T << b);
device.cpu_.pc_++;
return 1;
}
// BST
static unsigned int op_bst(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t b = opcode & 7;
LOG_OPCODE("BST r{},{}", d, b);
device.cpu_.sreg_.T = device.regfile_[d] & (1 << b);
device.cpu_.pc_++;
return 1;
}
// LDI, SER
static unsigned int op_ldi_ser(Device& device, uint16_t opcode) {
const uint8_t d = ((opcode >> 4) & 0xF) | 0x10; // 16 <= d <= 31
const uint8_t K = (opcode & 0xF) | ((opcode >> 4) & 0xF0);
LOG_OPCODE("LDI r{},0x{:02X}", d, K);
device.regfile_[d] = K;
device.cpu_.pc_++;
return 1;
}
// LDS (16-bit)
static unsigned int op_lds(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint16_t k = device.flash_data_[device.cpu_.pc_+1];
LOG_OPCODE("LDS r{},0x{:04X}", d, k);
const memptr_t addr = k | (device.cpu_.rampd_ << 16);
device.regfile_[d] = device.getDataMem(addr);
device.cpu_.pc_ += 2;
// assume the same for internal and external SRAM
return addr >= Device::MEM_SRAM_START ? 3 : 2;
}
// LD (X)
static unsigned int op_ld(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const memptr_t addr = device.regx_ | (device.cpu_.rampx_ << 16);
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LD r{},X @{:05X} = {:02X}", d, addr, device.regfile_[d]);
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= Device::MEM_SRAM_START ? 2 : 1;
}
// LD (X+)
static unsigned int op_ld_x_inc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 26 || d == 27) {
logger_asm->critical("undefined opcode behavior: LD r{},X+", d);
}
const memptr_t addr = device.regx_ | (device.cpu_.rampx_ << 16);
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LD r{},X+ @{:05X} = {:02X}", d, addr, device.regfile_[d]);
++device.regx_;
if(device.regx_ == 0) { // X overflow, update RAMPX
device.cpu_.rampx_++;
device.cpu_.rampx_ &= device.cpu_.ramp_mask_;
}
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= Device::MEM_SRAM_START ? 2 : 1;
}
// LD (-X)
static unsigned int op_ld_dec_x(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 26 || d == 27) {
logger_asm->critical("undefined opcode behavior: LD r{},-X", d);
}
--device.regx_;
if(device.regx_ == 0xFFFF) { // X underflow, update RAMPX
device.cpu_.rampx_--;
device.cpu_.rampx_ &= device.cpu_.ramp_mask_;
}
const memptr_t addr = device.regx_ | (device.cpu_.rampx_ << 16);
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LD r{},-X @{:05X} = {:02X}", d, addr, device.regfile_[d]);
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= Device::MEM_SRAM_START ? 3 : 2;
}
// LD (Y i), LDD (Y iv)
static unsigned int op_ld_y(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t q = (opcode & 0x7) | ((opcode >> 7) & 0x18) | ((opcode >> 8) & 0x20);
const memptr_t addr = (device.regy_ | (device.cpu_.rampy_ << 16)) + q;
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LDD r{},Y+{} @{:05X} = {:02X}", d, q, addr, device.regfile_[d]);
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= (q == 0 ? 2 : 1) + (Device::MEM_SRAM_START ? 1 : 0);
}
// LD (Y ii)
static unsigned int op_ld_y_inc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 28 || d == 29) {
logger_asm->critical("undefined opcode behavior: LD r{},Y+", d);
}
const memptr_t addr = device.regy_ | (device.cpu_.rampy_ << 16);
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LD r{},Y+ @{:05X} = {:02X}", d, addr, device.regfile_[d]);
++device.regy_;
if(device.regy_ == 0) { // Y overflow, update RAMPY
device.cpu_.rampy_++;
device.cpu_.rampy_ &= device.cpu_.ramp_mask_;
}
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= Device::MEM_SRAM_START ? 2 : 1;
}
// LD (Y iii)
static unsigned int op_ld_dec_y(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 28 || d == 29) {
logger_asm->critical("undefined opcode behavior: LD r{},-Y", d);
}
--device.regy_;
if(device.regy_ == 0xFFFF) { // Y underflow, update RAMPY
device.cpu_.rampy_--;
device.cpu_.rampy_ &= device.cpu_.ramp_mask_;
}
const memptr_t addr = device.regy_ | (device.cpu_.rampy_ << 16);
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LD r{},-Y @{:05X} = {:02X}", d, addr, device.regfile_[d]);
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= Device::MEM_SRAM_START ? 3 : 2;
}
// LD (Z i), LDD (Z iv)
static unsigned int op_ld_z(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t q = (opcode & 0x7) | ((opcode >> 7) & 0x18) | ((opcode >> 8) & 0x20);
const memptr_t addr = (device.regz_ | (device.cpu_.rampz_ << 16)) + q;
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LDD r{},Z+{} @{:05X} = {:02X}", d, q, addr, device.regfile_[d]);
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= (q == 0 ? 2 : 1) + (Device::MEM_SRAM_START ? 1 : 0);
}
// LD (Z ii)
static unsigned int op_ld_z_inc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 30 || d == 31) {
logger_asm->critical("undefined opcode behavior: LD r{},Z+", d);
}
const memptr_t addr = device.regz_ | (device.cpu_.rampz_ << 16);
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LD r{},Z+ @{:05X} = {:02X}", d, addr, device.regfile_[d]);
++device.regz_;
if(device.regz_ == 0) { // Z overflow, update RAMPZ
device.cpu_.rampz_++;
device.cpu_.rampz_ &= device.cpu_.ramp_mask_;
}
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= Device::MEM_SRAM_START ? 2 : 1;
}
// LD (Z iii)
static unsigned int op_ld_dec_z(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 30 || d == 31) {
logger_asm->critical("undefined opcode behavior: LD r{},-Z", d);
}
--device.regz_;
if(device.regz_ == 0xFFFF) { // Z underflow, update RAMPZ
device.cpu_.rampz_--;
device.cpu_.rampz_ &= device.cpu_.ramp_mask_;
}
const memptr_t addr = device.regz_ | (device.cpu_.rampz_ << 16);
device.regfile_[d] = device.getDataMem(addr);
LOG_OPCODE("LD r{},-Z @{:05X} = {:02X}", d, addr, device.regfile_[d]);
device.cpu_.pc_++;
// assume the same for internal and external SRAM
return addr >= Device::MEM_SRAM_START ? 3 : 2;
}
// STS (16-bit)
static unsigned int op_sts(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint16_t k = device.flash_data_[device.cpu_.pc_+1];
device.setDataMem(k | (device.cpu_.rampd_ << 16), device.regfile_[d]);
LOG_OPCODE("STS 0x{:04X},r{}", k, d);
device.cpu_.pc_ += 2;
return 2;
}
// ST (X i)
static unsigned int op_st_x(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const memptr_t addr = device.regx_ | (device.cpu_.rampx_ << 16);
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("ST X,r{} @{:05X} = {:02X}", d, addr, device.regfile_[d]);
device.cpu_.pc_++;
return 1;
}
// ST (X ii)
static unsigned int op_st_x_inc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 26 || d == 27) {
logger_asm->critical("undefined opcode behavior: ST X+,r{}", d);
}
const memptr_t addr = device.regx_ | (device.cpu_.rampx_ << 16);
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("ST X+,r{} @{:05X} = {:02X}", d, addr, device.regfile_[d]);
++device.regx_;
if(device.regx_ == 0) { // X overflow, update RAMPX
device.cpu_.rampx_++;
device.cpu_.rampx_ &= device.cpu_.ramp_mask_;
}
device.cpu_.pc_++;
return 1;
}
// ST (X iii)
static unsigned int op_st_dec_x(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 26 || d == 27) {
logger_asm->critical("undefined opcode behavior: ST -X,r{}", d);
}
--device.regx_;
if(device.regx_ == 0xFFFF) { // X underflow, update RAMPX
device.cpu_.rampx_--;
device.cpu_.rampx_ &= device.cpu_.ramp_mask_;
}
const memptr_t addr = device.regx_ | (device.cpu_.rampx_ << 16);
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("ST -X,r{} @{:05X} = {:02X}", d, addr, device.regfile_[d]);
device.cpu_.pc_++;
return 2;
}
// ST (Y i), STD (Y iv)
static unsigned int op_st_y(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t q = (opcode & 0x7) | ((opcode >> 7) & 0x18) | ((opcode >> 8) & 0x20);
const memptr_t addr = (device.regy_ | (device.cpu_.rampy_ << 16)) + q;
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("STD Y+{},r{} @{:05X} = {:02X}", q, d, addr, device.regfile_[d]);
device.cpu_.pc_++;
return q == 0 ? 1 : 2;
}
// ST (Y ii)
static unsigned int op_st_y_inc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 28 || d == 29) {
logger_asm->critical("undefined opcode behavior: ST Y+,r{}", d);
}
const memptr_t addr = device.regy_ | (device.cpu_.rampy_ << 16);
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("ST Y+,r{} @{:05X} = {:02X}", d, addr, device.regfile_[d]);
++device.regy_;
if(device.regy_ == 0) { // Y overflow, update RAMPY
device.cpu_.rampy_++;
device.cpu_.rampy_ &= device.cpu_.ramp_mask_;
}
device.cpu_.pc_++;
return 1;
}
// ST (Y iii)
static unsigned int op_st_dec_y(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 28 || d == 29) {
logger_asm->critical("undefined opcode behavior: ST -Y,r{}", d);
}
--device.regy_;
if(device.regy_ == 0xFFFF) { // Y underflow, update RAMPY
device.cpu_.rampy_--;
device.cpu_.rampy_ &= device.cpu_.ramp_mask_;
}
const memptr_t addr = device.regy_ | (device.cpu_.rampy_ << 16);
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("ST -Y,r{} @{:05X} = {:02X}", d, addr, device.regfile_[d]);
device.cpu_.pc_++;
return 2;
}
// ST (Z i), STD (Z iv)
static unsigned int op_st_z(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t q = (opcode & 0x7) | ((opcode >> 7) & 0x18) | ((opcode >> 8) & 0x20);
const memptr_t addr = (device.regz_ | (device.cpu_.rampz_ << 16)) + q;
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("STD Z+{},r{} @{:05X} = {:02X}", q, d, addr, device.regfile_[d]);
device.cpu_.pc_++;
return q == 0 ? 1 : 2;
}
// ST (Z ii)
static unsigned int op_st_z_inc(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 30 || d == 31) {
logger_asm->critical("undefined opcode behavior: ST Z+,r{}", d);
}
const memptr_t addr = device.regz_ | (device.cpu_.rampz_ << 16);
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("ST Z+,r{} @{:05X} = {:02X}", d, addr, device.regfile_[d]);
++device.regz_;
if(device.regz_ == 0) { // Z overflow, update RAMPZ
device.cpu_.rampz_++;
device.cpu_.rampz_ &= device.cpu_.ramp_mask_;
}
device.cpu_.pc_++;
return 1;
}
// ST (Z iii)
static unsigned int op_st_dec_z(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
if(d == 30 || d == 31) {
logger_asm->critical("undefined opcode behavior: ST -Z,r{}", d);
}
--device.regz_;
if(device.regz_ == 0xFFFF) { // Z underflow, update RAMPZ
device.cpu_.rampz_--;
device.cpu_.rampz_ &= device.cpu_.ramp_mask_;
}
const memptr_t addr = device.regz_ | (device.cpu_.rampz_ << 16);
device.setDataMem(addr, device.regfile_[d]);
LOG_OPCODE("ST -Z,r{} @{:05X} = {:02X}", d, addr, device.regfile_[d]);
device.cpu_.pc_++;
return 2;
}
// LPM (i)
static unsigned int op_lpm(Device& device, uint16_t) {
const uint16_t z = device.regz_;
const uint16_t v = device.flash_data_[z>>1];
LOG_OPCODE("LPM r0,Z");
device.regfile_[0] = (z & 1) ? (v >> 8) & 0xFF : (v & 0xFF);
device.cpu_.pc_++;
return 3;
}
// LPM (ii), (iii)
static unsigned int op_lpm_z(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint16_t z = device.regz_;
const uint16_t v = device.flash_data_[z>>1];
LOG_OPCODE("LPM r{},Z{}", d, (opcode & 1) ? "+" : "");
device.regfile_[d] = (z & 1) ? (v >> 8) & 0xFF : (v & 0xFF);
if(opcode & 1) {
++device.regz_;
}
device.cpu_.pc_++;
return 3;
}
// ELPM (i)
static unsigned int op_elpm(Device& device, uint16_t) {
const uint16_t z = device.regz_;
const uint16_t v = device.flash_data_[(z>>1) | (device.cpu_.rampz_ << 7)];
LOG_OPCODE("ELPM r0,Z");
device.regfile_[0] = (z & 1) ? (v >> 8) & 0xFF : (v & 0xFF);
device.cpu_.pc_++;
return 3;
}
// ELPM (ii), (iii)
static unsigned int op_elpm_z(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint16_t z = device.regz_;
const uint16_t v = device.flash_data_[(z>>1) | (device.cpu_.rampz_ << 7)];
LOG_OPCODE("ELPM r{},Z{}", d, (opcode & 1) ? "+" : "");
device.regfile_[d] = (z & 1) ? (v >> 8) & 0xFF : (v & 0xFF);
if(opcode & 1) {
++device.regz_;
if(device.regz_ == 0) { // Z overflow, update RAMPZ
device.cpu_.rampz_++;
device.cpu_.rampz_ &= device.cpu_.ramp_mask_;
}
}
device.cpu_.pc_++;
return 3;
}
// SPM, SPM#2
static unsigned int op_spm(Device& device, uint16_t) {
LOG_OPCODE("SPM");
//TODO
device.cpu_.pc_++;
return 1;
}
// XCH
static unsigned int op_xch(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
const uint8_t z = device.getDataMem(device.regz_);
LOG_OPCODE("XCH r{}", d);
device.setDataMem(device.regz_, Rd);
device.regfile_[d] = z;
device.cpu_.pc_++;
return 1;
}
// LAC
static unsigned int op_lac(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
const uint8_t z = device.getDataMem(device.regz_);
LOG_OPCODE("LAC r{}", d);
device.setDataMem(device.regz_, Rd & ~z);
device.cpu_.pc_++;
return 1;
}
// LAS
static unsigned int op_las(Device& device, uint16_t opcode) {
const uint8_t d = (opcode >> 4) & 0x1F;
const uint8_t Rd = device.regfile_[d];
const uint8_t z = device.getDataMem(device.regz_);
LOG_OPCODE("LAS r{}", d);
device.setDataMem(device.regz_, Rd | z);
device.regfile_[d] = z;
device.cpu_.pc_++;
return 1;
}