Tune DCC end of packet behavior (#504)

Adjusts the end of packet behavior of DCC packet generator, focusing on DCC->Marklin, Marklin->DCC transition, with and without the railcom cutout and with or without the half-zero bit.
- adds five extra one bits even if we are not generating a railcom cutout. This ensures that switching from DCC to Marklin is possible with keeping a DCC cutout window that will be used by a booster.
- Moves the half-zero to the beginning of the DCC preamble instead of being after the cutout. This makes the marklin-dcc interoperation better.
- Removes unnecessary states at the packet transition.
- Adds a hack for the resync handling at the beginning of
the DCC preamble.
- Adjusts the timing for the half-zero to be an upper half of
  one bit and a lower half of zero.
- Adds separate period setting for the PWM timer and the interval timer. 
- Fixes off by one errors in the counting of the preamble bits and the leadout bits.
- Adds a new bit type used during the leadout to avoid resynchronization
  at the packet start causing an output glitch.
- improves readability of some expressions
- Adds a truncated one bit after the cutout to complete the
  five onebits that are underlaid the cutout. The timing is HW-tunable.
  This is forced out with a `resync=true` after the output is reenabled.
- removes unnecessary interrupt disable from the write path.

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* Adds space for railcom cutout even if the DCC driver does not generate it.

This is necessary in case a booster is being driven which wants to add the railcom cutout.
Also adds support for generating a railcom half-zero even if no cutout is
generated.

* Adds half-zero feature and adjusts how many extra zero bits are generated.

* - Removes unnecessary states at the packet transition.
- Moves the generate halfzero feature to be at the beginning
of DCC packets instead of at the end of them.
- Adds a hack for the resync handling at the beginning of
the DCC preamble.
- Adjusts the timing for the half-zero to be an upper half of
  one bit and a lower half of zero.

* - Adds separate setting for the PWM timer and the interval timer.
- Fixes off by one errors in the counting of the preamble bits and the leadout bits.
- Adds a new bit type used during the leadout to avoid resynchronization
  causing an output glitch.
- simplifies some expressions
- Adds a truncated one bit after the cutout to complete the
  five onebits that are underlaid the cutout. The timing is HW-tunable.
  This is forced out with a resync=true after the output is reenabled.
- removes unnecessary interrupt disable from the write path.

* Fix whitespace.

* Removes commented code.