diff --git a/config/sources/families/include/sunxi64_common.inc b/config/sources/families/include/sunxi64_common.inc index 3bde6f758c2c..94ccc84bb1f8 100644 --- a/config/sources/families/include/sunxi64_common.inc +++ b/config/sources/families/include/sunxi64_common.inc @@ -36,7 +36,7 @@ case $BRANCH in edge) declare -g KERNEL_MAJOR_MINOR="6.12" # Major and minor versions of this kernel. - declare -g KERNELBRANCH="tag:v6.12.9" + declare -g KERNELBRANCH="tag:v6.12.13" ;; esac diff --git a/config/sources/families/include/sunxi_common.inc b/config/sources/families/include/sunxi_common.inc index c6578f762275..b95838292c01 100644 --- a/config/sources/families/include/sunxi_common.inc +++ b/config/sources/families/include/sunxi_common.inc @@ -37,7 +37,7 @@ case $BRANCH in edge) declare -g KERNEL_MAJOR_MINOR="6.12" # Major and minor versions of this kernel. - declare -g KERNELBRANCH="tag:v6.12.9" + declare -g KERNELBRANCH="tag:v6.12.13" ;; esac diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch index 374cfc9c1db0..28c42bb725b5 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch @@ -55,9 +55,9 @@ index 24383cb63770..16c739b56350 100644 + sun50i-h616-bananapi-m4-spi1-cs0-cs1-spidev.dtbo \ + sun50i-h616-bananapi-m4-spi1-cs0-spidev.dtbo \ + sun50i-h616-bananapi-m4-spi1-cs1-spidev.dtbo \ - sun50i-h616-i2c2-ph.dtbo \ - sun50i-h616-i2c3-ph.dtbo \ - sun50i-h616-i2c4-ph.dtbo \ + sun50i-h616-gpu.dtbo \ + sun50i-h616-i2c0-pi.dtbo \ + sun50i-h616-i2c1-pi.dtbo \ diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtso new file mode 100644 index 000000000000..4e78aa8f1f27 diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch index eb7a31cca488..873e4478df4d 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch @@ -9,10 +9,10 @@ Signed-off-by: Patrick Yavitz 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index 111111111111..222222222222 100644 +index 94be1b00d80a..e3659fb52dea 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -363,6 +363,30 @@ i2c0_pins: i2c0-pins { +@@ -370,6 +370,12 @@ i2c0_pins: i2c0-pins { function = "i2c0"; }; @@ -22,29 +22,11 @@ index 111111111111..222222222222 100644 + function = "i2c1"; + }; + -+ /omit-if-no-ref/ -+ i2c2_pi_pins: i2c2-pi-pins { -+ pins = "PI9", "PI10"; -+ function = "i2c2"; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c3_pg_pins: i2c3-pg-pins { -+ pins = "PG17", "PG18"; -+ function = "i2c3"; -+ }; -+ -+ /omit-if-no-ref/ -+ i2c4_pg_pins: i2c4-pg-pins { -+ pins = "PG15", "PG16"; -+ function = "i2c4"; -+ }; -+ + /omit-if-no-ref/ i2c2_ph_pins: i2c2-ph-pins { pins = "PH2", "PH3"; - function = "i2c2"; -@@ -444,6 +468,36 @@ spdif_tx_pin: spdif-tx-pin { - function = "spdif"; +@@ -461,6 +467,12 @@ spi1_cs0_pin: spi1-cs0-pin { + function = "spi1"; }; + /omit-if-no-ref/ @@ -53,12 +35,26 @@ index 111111111111..222222222222 100644 + function = "spi1"; + }; + + spdif_tx_pin: spdif-tx-pin { + pins = "PH4"; + function = "spdif"; +@@ -483,6 +495,12 @@ uart1_rts_cts_pins: uart1-rts-cts-pins { + function = "uart1"; + }; + + /omit-if-no-ref/ + uart2_pi_pins: uart2-pi-pins { + pins = "PI5", "PI6"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_pg_pins: uart2-pg-pins { + pins = "PG15", "PG16"; +@@ -507,6 +525,24 @@ uart2_ph_rts_cts_pins: uart2-ph-rts-cts-pins { + function = "uart2"; + }; + + /omit-if-no-ref/ + uart3_pi_pins: uart3-pi-pins { + pins = "PI9", "PI10"; @@ -77,9 +73,9 @@ index 111111111111..222222222222 100644 + function = "uart4"; + }; + - uart0_ph_pins: uart0-ph-pins { - pins = "PH0", "PH1"; - function = "uart0"; + /omit-if-no-ref/ + uart5_pins: uart5-pins { + pins = "PH2", "PH3"; -- Armbian diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/bigtereetech-cb1-i2c-gpio-and-ws2812.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch similarity index 70% rename from patch/kernel/archive/sunxi-6.12/patches.armbian/bigtereetech-cb1-i2c-gpio-and-ws2812.patch rename to patch/kernel/archive/sunxi-6.12/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch index 239c7a8d8198..deb579f87ad8 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/bigtereetech-cb1-i2c-gpio-and-ws2812.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch @@ -1,22 +1,20 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 20dc0b0f3da7895d50f2824b4608c5e44729f892 Mon Sep 17 00:00:00 2001 From: JohnTheCoolingFan Date: Sat, 25 Jan 2025 11:30:04 +0000 Subject: BigTreeTech CB1: dts: i2c gpio mode adjustment and ws2812 rgb_value Signed-off-by: JohnTheCoolingFan --- - arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts | 4 ++-- - arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts | 4 ++-- - arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 2 +- + .../boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts | 4 ++-- + .../boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts | 4 ++-- + .../arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts -index f878c23f1..b059ea08f 100644 +index f878c23f1d90..b059ea08fec0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts -@@ -19,12 +19,12 @@ &mmc2 { - &ws2812 { - gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ +@@ -21,8 +21,8 @@ &ws2812 { }; &i2c_gpio { @@ -27,15 +25,11 @@ index f878c23f1..b059ea08f 100644 }; &can0_pin_irq { - pins = "PI3"; - }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts -index e18dd854d..cc10be714 100644 +index e18dd854d74b..cc10be714676 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts -@@ -10,12 +10,12 @@ - &ws2812 { - gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */ +@@ -12,8 +12,8 @@ &ws2812 { }; &i2c_gpio { @@ -46,15 +40,11 @@ index e18dd854d..cc10be714 100644 }; &can0_pin_irq { - pins = "PC9"; - }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi -index 3b3a196ea..d18695148 100644 +index 3b3a196eaa93..d18695148ef5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi -@@ -106,11 +106,11 @@ wifi_pwrseq: wifi-pwrseq { - - ws2812: ws2812 { +@@ -108,7 +108,7 @@ ws2812: ws2812 { compatible = "rgb-ws2812"; pinctrl-names = "default"; rgb_cnt = <2>; @@ -63,8 +53,6 @@ index 3b3a196ea..d18695148 100644 status = "disabled"; }; - i2c_gpio: i2c-gpio { - #address-cells = <1>; -- -Created with Armbian build tools https://github.com/armbian/build +2.35.3 diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch index a50f63516b80..d52ffa3be0a8 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch @@ -1,23 +1,21 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 5607ccab3192a2cc9d70c6072f83d9b9060295c8 Mon Sep 17 00:00:00 2001 From: JohnTheCoolingFan Date: Sat, 25 Jan 2025 12:54:16 +0000 Subject: Fix ghost touches on tsc2007 tft screen Signed-off-by: JohnTheCoolingFan --- - arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 1 + - drivers/input/touchscreen/tsc2007.h | 1 + - drivers/input/touchscreen/tsc2007_core.c | 96 +++++----- - include/linux/platform_data/tsc2007.h | 1 + + .../sun50i-h616-bigtreetech-cb1.dtsi | 1 + + drivers/input/touchscreen/tsc2007.h | 1 + + drivers/input/touchscreen/tsc2007_core.c | 96 +++++++++---------- + include/linux/platform_data/tsc2007.h | 1 + 4 files changed, 49 insertions(+), 50 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi -index 2022990e4..3b3a196ea 100644 +index 2022990e4bc0..3b3a196eaa93 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi -@@ -123,10 +123,11 @@ i2c_gpio: i2c-gpio { - tft_tp: ns2009@48 { - compatible = "ti,tsc2007"; +@@ -125,6 +125,7 @@ tft_tp: ns2009@48 { reg = <0x48>; status = "disabled"; ti,x-plate-ohms = <660>; @@ -25,15 +23,11 @@ index 2022990e4..3b3a196ea 100644 ti,rt-thr = <3000>; ti,fuzzx = <32>; ti,fuzzy = <16>; - i2c,ignore-nak = <1>; - }; diff --git a/drivers/input/touchscreen/tsc2007.h b/drivers/input/touchscreen/tsc2007.h -index 5252b6c6d..7411b8bce 100644 +index 5252b6c6daeb..7411b8bce99c 100644 --- a/drivers/input/touchscreen/tsc2007.h +++ b/drivers/input/touchscreen/tsc2007.h -@@ -63,10 +63,11 @@ struct tsc2007 { - - struct i2c_client *client; +@@ -65,6 +65,7 @@ struct tsc2007 { u16 model; u16 x_plate_ohms; @@ -41,15 +35,11 @@ index 5252b6c6d..7411b8bce 100644 u16 max_rt; u16 rt_thr; u8 touched; - unsigned long poll_period; /* in jiffies */ - int fuzzx; diff --git a/drivers/input/touchscreen/tsc2007_core.c b/drivers/input/touchscreen/tsc2007_core.c -index 08bbbafbb..1ae1b1a3e 100644 +index 08bbbafbbae1..1ae1b1a3e367 100644 --- a/drivers/input/touchscreen/tsc2007_core.c +++ b/drivers/input/touchscreen/tsc2007_core.c -@@ -68,26 +68,24 @@ static void tsc2007_read_values(struct tsc2007 *tsc, struct ts_event *tc) - tsc2007_xfer(tsc, PWRDOWN); - } +@@ -70,22 +70,20 @@ static void tsc2007_read_values(struct tsc2007 *tsc, struct ts_event *tc) u32 tsc2007_calculate_resistance(struct tsc2007 *tsc, struct ts_event *tc) { @@ -82,11 +72,7 @@ index 08bbbafbb..1ae1b1a3e 100644 } bool tsc2007_is_pen_down(struct tsc2007 *ts) - { - /* -@@ -178,58 +176,45 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle) - { - struct tsc2007 *ts = handle; +@@ -180,6 +178,7 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle) struct input_dev *input = ts->input; struct ts_event tc; u32 rt; @@ -94,9 +80,7 @@ index 08bbbafbb..1ae1b1a3e 100644 if(!ts->stopped) { - mutex_lock(&ts->mlock); - tsc2007_read_values(ts, &tc); - mutex_unlock(&ts->mlock); +@@ -189,45 +188,31 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle) rt = tsc2007_calculate_resistance(ts, &tc); @@ -162,11 +146,7 @@ index 08bbbafbb..1ae1b1a3e 100644 } return IRQ_HANDLED; - } - -@@ -327,10 +312,17 @@ static int tsc2007_probe_properties(struct device *dev, struct tsc2007 *ts) - } else { - dev_err(dev, "Missing ti,x-plate-ohms device property\n"); +@@ -329,6 +314,13 @@ static int tsc2007_probe_properties(struct device *dev, struct tsc2007 *ts) return -EINVAL; } @@ -180,11 +160,7 @@ index 08bbbafbb..1ae1b1a3e 100644 ts->gpiod = devm_gpiod_get_optional(dev, NULL, GPIOD_IN); if (IS_ERR(ts->gpiod)) return PTR_ERR(ts->gpiod); - - if (ts->gpiod) -@@ -345,10 +337,11 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts, - const struct tsc2007_platform_data *pdata, - const struct i2c_device_id *id) +@@ -347,6 +339,7 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts, { ts->model = pdata->model; ts->x_plate_ohms = pdata->x_plate_ohms; @@ -192,11 +168,7 @@ index 08bbbafbb..1ae1b1a3e 100644 ts->max_rt = pdata->max_rt ? : MAX_12BIT; ts->poll_period = msecs_to_jiffies(pdata->poll_period ? : 1); ts->get_pendown_state = pdata->get_pendown_state; - ts->clear_penirq = pdata->clear_penirq; - ts->fuzzx = pdata->fuzzx; -@@ -358,10 +351,15 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts, - if (pdata->x_plate_ohms == 0) { - dev_err(dev, "x_plate_ohms is not set up in platform data\n"); +@@ -360,6 +353,11 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts, return -EINVAL; } @@ -208,11 +180,7 @@ index 08bbbafbb..1ae1b1a3e 100644 return 0; } - static void tsc2007_call_exit_platform_hw(void *data) - { -@@ -456,15 +454,13 @@ static int tsc2007_probe(struct i2c_client *client) - dev_err(&client->dev, "Failed to request irq %d: %d\n", - ts->irq, err); +@@ -458,11 +456,9 @@ static int tsc2007_probe(struct i2c_client *client) return err; } } else { @@ -226,15 +194,11 @@ index 08bbbafbb..1ae1b1a3e 100644 add_timer(&ts->timer); } - tsc2007_stop(ts); - diff --git a/include/linux/platform_data/tsc2007.h b/include/linux/platform_data/tsc2007.h -index a0ca52c41..f88e58032 100644 +index a0ca52c41ccb..f88e580322f0 100644 --- a/include/linux/platform_data/tsc2007.h +++ b/include/linux/platform_data/tsc2007.h -@@ -5,10 +5,11 @@ - /* linux/platform_data/tsc2007.h */ - +@@ -7,6 +7,7 @@ struct tsc2007_platform_data { u16 model; /* 2007. */ u16 x_plate_ohms; /* must be non-zero value */ @@ -242,8 +206,6 @@ index a0ca52c41..f88e58032 100644 u16 max_rt; /* max. resistance above which samples are ignored */ unsigned long poll_period; /* time (in ms) between samples */ int fuzzx; /* fuzz factor for X, Y and pressure axes */ - int fuzzy; - int fuzzz; -- -Created with Armbian build tools https://github.com/armbian/build +2.35.3 diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch index 14532b4e5dbc..b9f56092026c 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch @@ -80,18 +80,18 @@ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dt index ed68a644148e..5c0b573b622e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -495,7 +495,8 @@ gic: interrupt-controller@3021000 { +@@ -532,7 +532,8 @@ gic: interrupt-controller@3021000 { }; iommu: iommu@30f0000 { - compatible = "allwinner,sun50i-h616-iommu"; + compatible = "allwinner,sun50i-h616-iommu", -+ "allwinner,sun50i-h6-iommu"; ++ "allwinner,sun50i-h6-iommu"; reg = <0x030f0000 0x10000>; interrupts = ; clocks = <&ccu CLK_BUS_IOMMU>; -@@ -852,6 +853,78 @@ mdio1: mdio { - }; +@@ -885,6 +886,78 @@ lradc: lradc@5070800 { + status = "disabled"; }; + codec: codec@05096000 { diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/add-dtb-overlay-for-zero2w.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/add-dtb-overlay-for-zero2w.patch index 4ec1a4131b07..15909dbe0cec 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/add-dtb-overlay-for-zero2w.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/add-dtb-overlay-for-zero2w.patch @@ -1,64 +1,35 @@ -From f77a4d2907fa1976d81a27bcdb01266cf56fcd69 Mon Sep 17 00:00:00 2001 +From 2373a5f138261ca2ab372443db4a9b25f12fe823 Mon Sep 17 00:00:00 2001 From: chraac Date: Fri, 5 Apr 2024 10:57:18 +0800 Subject: add dtb overlay for zero2w --- - .../arm64/boot/dts/allwinner/overlay/Makefile | 16 ++++++++----- + .../arm64/boot/dts/allwinner/overlay/Makefile | 4 ++++ .../allwinner/overlay/sun50i-h616-gpu.dtso | 14 +++++++++++ .../overlay/sun50i-h616-i2c0-pi.dtso | 23 +++++++++++++++++++ .../overlay/sun50i-h616-i2c1-pi.dtso | 16 +++++++++++++ - ...616-i2c2.dtso => sun50i-h616-i2c2-ph.dtso} | 0 .../overlay/sun50i-h616-i2c2-pi.dtso | 23 +++++++++++++++++++ - ...616-i2c3.dtso => sun50i-h616-i2c3-ph.dtso} | 0 - ...616-i2c4.dtso => sun50i-h616-i2c4-ph.dtso} | 0 - ...6-uart2.dtso => sun50i-h616-uart2-ph.dtso} | 0 - ...6-uart5.dtso => sun50i-h616-uart5-ph.dtso} | 0 - 10 files changed, 86 insertions(+), 6 deletions(-) + 5 files changed, 80 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso - rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c2.dtso => sun50i-h616-i2c2-ph.dtso} (100%) create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso - rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c3.dtso => sun50i-h616-i2c3-ph.dtso} (100%) - rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-i2c4.dtso => sun50i-h616-i2c4-ph.dtso} (100%) - rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-uart2.dtso => sun50i-h616-uart2-ph.dtso} (100%) - rename arch/arm64/boot/dts/allwinner/overlay/{sun50i-h616-uart5.dtso => sun50i-h616-uart5-ph.dtso} (100%) diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile -index 369b2976b1bb..24383cb63770 100644 +index 718909b607a6..ccb89b5bf495 100644 --- a/arch/arm64/boot/dts/allwinner/overlay/Makefile +++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile -@@ -49,11 +49,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ +@@ -49,6 +49,10 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun50i-h6-uart2.dtbo \ sun50i-h6-uart3.dtbo \ sun50i-h6-w1-gpio.dtbo \ -- sun50i-h616-i2c2.dtbo \ -- sun50i-h616-i2c3.dtbo \ -- sun50i-h616-i2c4.dtbo \ -- sun50i-h616-uart2.dtbo \ -- sun50i-h616-uart5.dtbo \ -+ sun50i-h616-i2c2-ph.dtbo \ -+ sun50i-h616-i2c3-ph.dtbo \ -+ sun50i-h616-i2c4-ph.dtbo \ -+ sun50i-h616-uart2-ph.dtbo \ -+ sun50i-h616-uart5-ph.dtbo \ - sun50i-h616-spi-spidev.dtbo \ - sun50i-h616-spidev0_0.dtbo \ - sun50i-h616-spidev1_0.dtbo \ -@@ -63,7 +63,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ - sun50i-h616-tft35_spi.dtbo \ - sun50i-h616-mcp2515.dtbo \ - sun50i-h616-ws2812.dtbo \ -- sun50i-h616-light.dtbo -+ sun50i-h616-light.dtbo \ ++ sun50i-h616-gpu.dtbo \ + sun50i-h616-i2c0-pi.dtbo \ + sun50i-h616-i2c1-pi.dtbo \ + sun50i-h616-i2c2-pi.dtbo \ -+ sun50i-h616-gpu.dtbo - - scr-$(CONFIG_ARCH_SUNXI) += \ - sun50i-a64-fixup.scr \ + sun50i-h616-i2c2-ph.dtbo \ + sun50i-h616-i2c3-pg.dtbo \ + sun50i-h616-i2c3-ph.dtbo \ diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso new file mode 100644 index 000000000000..ac8846ac7d27 @@ -130,10 +101,6 @@ index 000000000000..05f3100967ff + }; + }; +}; -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso -similarity index 100% -rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso -rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso new file mode 100644 index 000000000000..0f7d7e9968d6 @@ -163,22 +130,6 @@ index 000000000000..0f7d7e9968d6 + }; + }; +}; -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso -similarity index 100% -rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso -rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso -similarity index 100% -rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso -rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso -similarity index 100% -rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso -rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5-ph.dtso -similarity index 100% -rename from arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso -rename to arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5-ph.dtso -- 2.35.3 diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch index db8965b7d46b..43ffdd0682cf 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch @@ -1,15 +1,15 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From e8bbd9b6907278702499477267c1dd9ffa3b7530 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Sat, 16 Apr 2022 11:51:35 +0300 Subject: add nodes for sunxi-info, sunxi-addr and sunxi-dump-reg --- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 ++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 19 ++++++++++ + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++ + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 19 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 111111111111..222222222222 100644 +index 0e7f44cf90c6..342dd620126c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -1256,6 +1256,25 @@ ths: thermal-sensor@5070400 { @@ -39,10 +39,10 @@ index 111111111111..222222222222 100644 thermal-zones { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index 111111111111..222222222222 100644 +index 440104413a30..450382ae1900 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -1006,6 +1006,25 @@ r_rsb: rsb@7083000 { +@@ -999,6 +999,25 @@ r_rsb: rsb@7083000 { #address-cells = <1>; #size-cells = <0>; }; @@ -69,5 +69,5 @@ index 111111111111..222222222222 100644 thermal-zones { -- -Armbian +2.35.3 diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch deleted file mode 100644 index 12d93b30eb0b..000000000000 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 8c8c43546c9ba3f6fb29ad65b08e4744586b688b Mon Sep 17 00:00:00 2001 -From: Gunjan Gupta -Date: Thu, 1 Feb 2024 22:38:21 +0000 -Subject: arm64: dts: H616: Add overlays that are also compatible with orange - pi zero2 and zero3 - ---- - .../arm64/boot/dts/allwinner/overlay/Makefile | 5 ++++ - .../allwinner/overlay/sun50i-h616-i2c2.dtso | 8 ++++++ - .../allwinner/overlay/sun50i-h616-i2c3.dtso | 8 ++++++ - .../allwinner/overlay/sun50i-h616-i2c4.dtso | 8 ++++++ - .../allwinner/overlay/sun50i-h616-uart2.dtso | 8 ++++++ - .../allwinner/overlay/sun50i-h616-uart5.dtso | 8 ++++++ - .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 26 ++++++++++++++++++- - 7 files changed, 70 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso - create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso - create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso - create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso - create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso - -diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile -index 84711585fc86..369b2976b1bb 100644 ---- a/arch/arm64/boot/dts/allwinner/overlay/Makefile -+++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile -@@ -49,6 +49,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ - sun50i-h6-uart2.dtbo \ - sun50i-h6-uart3.dtbo \ - sun50i-h6-w1-gpio.dtbo \ -+ sun50i-h616-i2c2.dtbo \ -+ sun50i-h616-i2c3.dtbo \ -+ sun50i-h616-i2c4.dtbo \ -+ sun50i-h616-uart2.dtbo \ -+ sun50i-h616-uart5.dtbo \ - sun50i-h616-spi-spidev.dtbo \ - sun50i-h616-spidev0_0.dtbo \ - sun50i-h616-spidev1_0.dtbo \ -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso -new file mode 100644 -index 000000000000..feebc9ad85fb ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2.dtso -@@ -0,0 +1,8 @@ -+/dts-v1/; -+/plugin/; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_ph_pins>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso -new file mode 100644 -index 000000000000..bb212d3c66da ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3.dtso -@@ -0,0 +1,8 @@ -+/dts-v1/; -+/plugin/; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_ph_pins>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso -new file mode 100644 -index 000000000000..8fbcc658b22c ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4.dtso -@@ -0,0 +1,8 @@ -+/dts-v1/; -+/plugin/; -+ -+&i2c4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c4_ph_pins>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso -new file mode 100644 -index 000000000000..6a6806906972 ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2.dtso -@@ -0,0 +1,8 @@ -+/dts-v1/; -+/plugin/; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso -new file mode 100644 -index 000000000000..4f172489276b ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso -@@ -0,0 +1,8 @@ -+/dts-v1/; -+/plugin/; -+ -+&uart5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart5_pins>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index 14502225ef64..400bab783cd0 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -363,11 +363,21 @@ i2c0_pins: i2c0-pins { - function = "i2c0"; - }; - -+ i2c2_ph_pins: i2c2-ph-pins { -+ pins = "PH2", "PH3"; -+ function = "i2c2"; -+ }; -+ - i2c3_ph_pins: i2c3-ph-pins { - pins = "PH4", "PH5"; - function = "i2c3"; - }; - -+ i2c4_ph_pins: i2c4-ph-pins { -+ pins = "PH6", "PH7"; -+ function = "i2c4"; -+ }; -+ - ir_rx_pin: ir-rx-pin { - pins = "PH10"; - function = "ir_rx"; -@@ -418,7 +428,6 @@ spi0_cs0_pin: spi0-cs0-pin { - function = "spi0"; - }; - -- /omit-if-no-ref/ - spi1_pins: spi1-pins { - pins = "PH6", "PH7", "PH8"; - function = "spi1"; -@@ -440,6 +449,21 @@ uart0_ph_pins: uart0-ph-pins { - function = "uart0"; - }; - -+ uart2_pins: uart2-pins { -+ pins = "PH5", "PH6"; -+ function = "uart2"; -+ }; -+ -+ uart2_rts_cts_pins: uart2-rts-cts-pins { -+ pins = "PH7", "PH8"; -+ function = "uart2"; -+ }; -+ -+ uart5_pins: uart5-pins { -+ pins = "PH2", "PH3"; -+ function = "uart5"; -+ }; -+ - /omit-if-no-ref/ - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch deleted file mode 100644 index 4db489d72677..000000000000 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: The-going <48602507+The-going@users.noreply.github.com> -Date: Sun, 13 Nov 2022 23:15:38 +0300 -Subject: arm64: dts: allwiner: sun50i-h616.dtsi: add usb,ehci,ohci - ---- - arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 ++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -100,12 +100,12 @@ reserved-memory { - ranges; - - /* -- * 256 KiB reserved for Trusted Firmware-A (BL31). -+ * 512 KiB reserved for Trusted Firmware-A (BL31). - * This is added by BL31 itself, but some bootloaders fail - * to propagate this into the DTB handed to kernels. - */ - secmon@40000000 { -- reg = <0x0 0x40000000 0x0 0x40000>; -+ reg = <0x0 0x40000000 0x0 0x80000>; - no-map; - }; - }; -@@ -590,6 +590,8 @@ spi0: spi@5010000 { - dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; -@@ -605,6 +607,8 @@ spi1: spi@5011000 { - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; -@@ -872,11 +876,14 @@ nmi_intc: interrupt-controller@7010320 { - r_pio: pinctrl@7022000 { - compatible = "allwinner,sun50i-h616-r-pinctrl"; - reg = <0x07022000 0x400>; -+ interrupts = ; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; -+ interrupt-controller; -+ #interrupt-cells = <3>; - - /omit-if-no-ref/ - r_i2c_pins: r-i2c-pins { --- -Armbian - diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch new file mode 100644 index 000000000000..10f57e68c8dc --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch @@ -0,0 +1,83 @@ +From 1989d73c62ac37fa9130595b0543c0459f77aed5 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sun, 9 Feb 2025 17:52:52 +0300 +Subject: [PATCH] arm64: dts: allwinner: Add axp313a.dtsi + +--- + arch/arm64/boot/dts/allwinner/axp313a.dtsi | 64 ++++++++++++++++++++++ + 1 file changed, 64 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/axp313a.dtsi + +diff --git a/arch/arm64/boot/dts/allwinner/axp313a.dtsi b/arch/arm64/boot/dts/allwinner/axp313a.dtsi +new file mode 100644 +index 000000000000..99057e975574 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/axp313a.dtsi +@@ -0,0 +1,64 @@ ++ ++&r_i2c { ++ status = "okay"; ++ ++ axp313a: pmic@36 { ++ compatible = "x-powers,axp313a"; ++ reg = <0x36>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&pio>; ++ ++ vin1-supply = <®_vcc5v>; ++ vin2-supply = <®_vcc5v>; ++ vin3-supply = <®_vcc5v>; ++ ++ regulators { ++ reg_dcdc1: dcdc1 { ++ regulator-name = "vdd-gpu"; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <990000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-name = "vdd-cpu"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-ramp-delay = <200>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-name = "vcc-dram"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_aldo1: aldo1 { ++ regulator-name = "vcc-1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dldo1: dldo1 { ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch index 42ec5fd2ad0c..4811159b3151 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch @@ -12,9 +12,9 @@ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dt index 111111111111..222222222222 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -160,6 +160,20 @@ crypto: crypto@1904000 { - resets = <&ccu RST_BUS_CE>; - }; +@@ -150,6 +150,20 @@ soc { + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + gpu: gpu@1800000 { + compatible = "allwinner,sun50i-h616-mali", @@ -30,9 +30,9 @@ index 111111111111..222222222222 100644 + status = "disabled"; + }; + - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h616-system-control"; - reg = <0x03000000 0x1000>; + crypto: crypto@1904000 { + compatible = "allwinner,sun50i-h616-crypto"; + reg = <0x01904000 0x800>; -- Armbian diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch index be642573851c..478921f43321 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch @@ -9,11 +9,11 @@ Signed-off-by: Jernej Skrabec 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index 111111111111..222222222222 100644 +index 6109f46d3fed..44906eb25c80 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -174,6 +174,17 @@ gpu: gpu@1800000 { - status = "disabled"; +@@ -174,6 +174,17 @@ crypto: crypto@1904000 { + resets = <&ccu RST_BUS_CE>; }; + video-codec@1c0e000 { diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-234-ph-pg-uart-25-ph-pg.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-234-ph-pg-uart-25-ph-pg.patch new file mode 100644 index 000000000000..9c2210f52639 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-234-ph-pg-uart-25-ph-pg.patch @@ -0,0 +1,253 @@ +From 75745c3387ef68fd5b0a0ae366fecfff4fa05931 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sat, 8 Feb 2025 16:38:23 +0300 +Subject: arm64: dts: h616(8): Add overlays i2c(234)ph,pg; uart(25)ph,pg + +--- + arch/arm64/boot/dts/allwinner/overlay/Makefile | 10 ++++++++++ + .../allwinner/overlay/sun50i-h616-i2c2-ph.dtso | 13 +++++++++++++ + .../allwinner/overlay/sun50i-h616-i2c3-pg.dtso | 13 +++++++++++++ + .../allwinner/overlay/sun50i-h616-i2c3-ph.dtso | 13 +++++++++++++ + .../allwinner/overlay/sun50i-h616-i2c4-pg.dtso | 13 +++++++++++++ + .../allwinner/overlay/sun50i-h616-i2c4-ph.dtso | 13 +++++++++++++ + .../overlay/sun50i-h616-uart2-pg-rts-cts.dtso | 15 +++++++++++++++ + .../allwinner/overlay/sun50i-h616-uart2-pg.dtso | 15 +++++++++++++++ + .../overlay/sun50i-h616-uart2-ph-rts-cts.dtso | 15 +++++++++++++++ + .../allwinner/overlay/sun50i-h616-uart2-ph.dtso | 15 +++++++++++++++ + .../dts/allwinner/overlay/sun50i-h616-uart5.dtso | 15 +++++++++++++++ + 11 files changed, 150 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-pg.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-pg.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg-rts-cts.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph-rts-cts.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso + create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso + +diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile +index 84711585fc86..718909b607a6 100644 +--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile ++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile +@@ -49,6 +49,16 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ + sun50i-h6-uart2.dtbo \ + sun50i-h6-uart3.dtbo \ + sun50i-h6-w1-gpio.dtbo \ ++ sun50i-h616-i2c2-ph.dtbo \ ++ sun50i-h616-i2c3-pg.dtbo \ ++ sun50i-h616-i2c3-ph.dtbo \ ++ sun50i-h616-i2c4-pg.dtbo \ ++ sun50i-h616-i2c4-ph.dtbo \ ++ sun50i-h616-uart2-pg.dtbo \ ++ sun50i-h616-uart2-pg-rts-cts.dtbo \ ++ sun50i-h616-uart2-ph.dtbo \ ++ sun50i-h616-uart2-ph-rts-cts.dtbo \ ++ sun50i-h616-uart5.dtbo \ + sun50i-h616-spi-spidev.dtbo \ + sun50i-h616-spidev0_0.dtbo \ + sun50i-h616-spidev1_0.dtbo \ +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso +new file mode 100644 +index 000000000000..663633f6c7c9 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_ph_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-pg.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-pg.dtso +new file mode 100644 +index 000000000000..eb71dcb593cc +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-pg.dtso +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&i2c3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pg_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso +new file mode 100644 +index 000000000000..b0aed6f59bb0 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&i2c3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_ph_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-pg.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-pg.dtso +new file mode 100644 +index 000000000000..6a83466f5b37 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-pg.dtso +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&i2c4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4_pg_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso +new file mode 100644 +index 000000000000..cfa737d701d8 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ fragment@0 { ++ target = <&i2c4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4_ph_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg-rts-cts.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg-rts-cts.dtso +new file mode 100644 +index 000000000000..7cee4ebec233 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg-rts-cts.dtso +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618"; ++ ++ fragment@0 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pg_pins>, <&uart2_pg_rts_cts_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg.dtso +new file mode 100644 +index 000000000000..298cb56023a1 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg.dtso +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618"; ++ ++ fragment@0 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pg_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph-rts-cts.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph-rts-cts.dtso +new file mode 100644 +index 000000000000..66193cde7526 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph-rts-cts.dtso +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618"; ++ ++ fragment@0 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_ph_pins>, <&uart2_ph_rts_cts_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso +new file mode 100644 +index 000000000000..438af7517b5a +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618"; ++ ++ fragment@0 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_ph_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso +new file mode 100644 +index 000000000000..27b4ab085d98 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618"; ++ ++ fragment@0 { ++ target = <&uart5>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch index 2799c1ce725f..9898f2242f0e 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch @@ -75,7 +75,7 @@ index 111111111111..222222222222 100644 vmmc-supply = <®_dcdce>; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index 111111111111..222222222222 100644 +index 450382ae1900..b7df6e4c054f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -7,8 +7,11 @@ @@ -103,9 +103,9 @@ index 111111111111..222222222222 100644 reserved-memory { #address-cells = <2>; #size-cells = <2>; -@@ -160,6 +169,50 @@ crypto: crypto@1904000 { - resets = <&ccu RST_BUS_CE>; - }; +@@ -150,6 +159,50 @@ soc { + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + bus@1000000 { + compatible = "allwinner,sun50i-h616-de33", @@ -186,7 +186,7 @@ index 111111111111..222222222222 100644 }; sram_c1: sram@1a00000 { -@@ -907,6 +979,147 @@ ohci3: usb@5311400 { +@@ -903,6 +975,147 @@ ohci3: usb@5311400 { status = "disabled"; }; diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch index f106a44ff296..95337d86843e 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch @@ -10,7 +10,7 @@ Signed-off-by: Jernej Skrabec 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts -index 111111111111..222222222222 100644 +index 26d25b5b59e0..2ccdc317af14 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -16,6 +16,7 @@ / { @@ -55,11 +55,11 @@ index 111111111111..222222222222 100644 status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index 111111111111..222222222222 100644 +index 44906eb25c80..440104413a30 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -327,6 +327,13 @@ mmc2_pins: mmc2-pins { - bias-pull-up; +@@ -286,6 +286,13 @@ ext_rgmii_pins: rgmii-pins { + drive-strength = <40>; }; + rmii_pins: rmii-pins { @@ -69,11 +69,11 @@ index 111111111111..222222222222 100644 + drive-strength = <40>; + }; + - /omit-if-no-ref/ - spi0_pins: spi0-pins { - pins = "PC0", "PC2", "PC4"; -@@ -721,6 +728,25 @@ lradc: lradc@5070800 { - status = "disabled"; + i2c0_pins: i2c0-pins { + pins = "PI5", "PI6"; + function = "i2c0"; +@@ -668,6 +675,25 @@ mdio0: mdio { + }; }; + emac1: ethernet@5030000 { @@ -95,9 +95,9 @@ index 111111111111..222222222222 100644 + }; + }; + - usbotg: usb@5100000 { - compatible = "allwinner,sun50i-h616-musb", - "allwinner,sun8i-h3-musb"; + spdif: spdif@5093000 { + compatible = "allwinner,sun50i-h616-spdif"; + reg = <0x05093000 0x400>; -- Armbian diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch new file mode 100644 index 000000000000..f31cabe5dae8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch @@ -0,0 +1,31 @@ +From abf887a3265a84d1593b319133e5ee106301a23a Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sun, 13 Nov 2022 23:15:38 +0300 +Subject: arm64: dts: sun50i-h616.dtsi: reserved memory 512K for BL31 + +--- + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index e88c1fbac6ac..acba4de960ce 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -100,12 +100,12 @@ reserved-memory { + ranges; + + /* +- * 256 KiB reserved for Trusted Firmware-A (BL31). ++ * 512 KiB reserved for Trusted Firmware-A (BL31). + * This is added by BL31 itself, but some bootloaders fail + * to propagate this into the DTB handed to kernels. + */ + secmon@40000000 { +- reg = <0x0 0x40000000 0x0 0x40000>; ++ reg = <0x0 0x40000000 0x0 0x80000>; + no-map; + }; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch index 6ecdb38769e9..eb89053da9dc 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch @@ -1,15 +1,15 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 19643d4a52afccb60743c52906065adb29a7a27a Mon Sep 17 00:00:00 2001 From: chraac Date: Fri, 15 Mar 2024 12:30:26 +0800 Subject: arm64: dts: sun50i-h618-orangepi-zero2w: Add missing nodes --- - arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 25 +- - arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts | 628 +++++++++- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 25 +- + .../allwinner/sun50i-h618-orangepi-zero2w.dts | 628 ++++++++++++++++-- 2 files changed, 586 insertions(+), 67 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index 111111111111..222222222222 100644 +index 971b3fd80763..67d0621b6dbd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -240,7 +240,7 @@ video-codec@1c0e000 { @@ -21,7 +21,7 @@ index 111111111111..222222222222 100644 #address-cells = <1>; #size-cells = <1>; ranges; -@@ -825,19 +825,28 @@ lradc: lradc@5070800 { +@@ -809,19 +809,28 @@ mdio0: mdio { }; emac1: ethernet@5030000 { @@ -58,7 +58,7 @@ index 111111111111..222222222222 100644 #size-cells = <0>; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts -index 111111111111..222222222222 100644 +index 6a4f0da97233..5a550d904534 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts @@ -7,10 +7,15 @@ @@ -771,5 +771,5 @@ index 111111111111..222222222222 100644 + }; +}; -- -Armbian +2.35.3 diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch new file mode 100644 index 000000000000..3a09e6f983e7 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch @@ -0,0 +1,101 @@ +From 5942e98140a7d7e58f335d578bd7f5a91b2068f1 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sat, 8 Feb 2025 12:37:21 +0300 +Subject: [PATCH] arm64: sun50i-h616: Add i2c(2,3,4), uart(2,5) pins + +Add a description of the pins for further use +in device trees and overlays. + +link to: +drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +--- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index b7df6e4c054f..971b3fd80763 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -370,11 +370,42 @@ i2c0_pins: i2c0-pins { + function = "i2c0"; + }; + ++ /omit-if-no-ref/ ++ i2c2_ph_pins: i2c2-ph-pins { ++ pins = "PH2", "PH3"; ++ function = "i2c2"; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c2_pi_pins: i2c2-pi-pins { ++ pins = "PI9", "PI10"; ++ function = "i2c2"; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c3_pg_pins: i2c3-pg-pins { ++ pins = "PG17", "PG18"; ++ function = "i2c3"; ++ }; ++ ++ /omit-if-no-ref/ + i2c3_ph_pins: i2c3-ph-pins { + pins = "PH4", "PH5"; + function = "i2c3"; + }; + ++ /omit-if-no-ref/ ++ i2c4_pg_pins: i2c4-pg-pins { ++ pins = "PG15", "PG16"; ++ function = "i2c4"; ++ }; ++ ++ /omit-if-no-ref/ ++ i2c4_ph_pins: i2c4-ph-pins { ++ pins = "PH6", "PH7"; ++ function = "i2c4"; ++ }; ++ + ir_rx_pin: ir-rx-pin { + pins = "PH10"; + function = "ir_rx"; +@@ -452,6 +483,36 @@ uart1_rts_cts_pins: uart1-rts-cts-pins { + function = "uart1"; + }; + ++ /omit-if-no-ref/ ++ uart2_pg_pins: uart2-pg-pins { ++ pins = "PG15", "PG16"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_pg_rts_cts_pins: uart2-pg-rts-cts-pins { ++ pins = "PG17", "PG18"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_ph_pins: uart2-ph-pins { ++ pins = "PH5", "PH6"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_ph_rts_cts_pins: uart2-ph-rts-cts-pins { ++ pins = "PH7", "PH8"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_pins: uart5-pins { ++ pins = "PH2", "PH3"; ++ function = "uart5"; ++ }; ++ + /omit-if-no-ref/ + x32clk_fanout_pin: x32clk-fanout-pin { + pins = "PG10"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch index 7f096f6f1276..1b207cd0d44d 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch @@ -11,7 +11,7 @@ diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_m index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -708,6 +708,14 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { +@@ -769,6 +769,14 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { .vi_num = 1, }; @@ -25,8 +25,8 @@ index 111111111111..222222222222 100644 + static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { .ccsc = CCSC_MIXER0_LAYOUT, - .mod_rate = 297000000, -@@ -794,6 +802,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = { + .de_type = sun8i_mixer_de2, +@@ -875,6 +883,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = { .compatible = "allwinner,sun8i-h3-de2-mixer-0", .data = &sun8i_h3_mixer0_cfg, }, diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/scripts-add-overlay-compilation-support.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/scripts-add-overlay-compilation-support.patch index f028dab71547..e92af80c7a14 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/scripts-add-overlay-compilation-support.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.armbian/scripts-add-overlay-compilation-support.patch @@ -66,7 +66,7 @@ index 111111111111..222222222222 100644 ifneq ($(obj),.) @@ -377,6 +380,15 @@ quiet_cmd_lz4_with_size = LZ4 $@ - cmd_lz4_with_size = { cat $(real-prereqs) | $(LZ4) -l -c1 stdin stdout; \ + cmd_lz4_with_size = { cat $(real-prereqs) | $(LZ4) -l -9 - -; \ $(size_append); } > $@ +# Fixup script mkimage provided by Armbian diff --git a/patch/kernel/archive/sunxi-6.12/patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch b/patch/kernel/archive/sunxi-6.12/patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch deleted file mode 100644 index 8569430015ea..000000000000 --- a/patch/kernel/archive/sunxi-6.12/patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: The-going <48602507+The-going@users.noreply.github.com> -Date: Sun, 23 Jan 2022 22:22:39 +0300 -Subject: sound:soc:sunxi:sun4i-spdif add mclk_multiplier - ---- - sound/soc/sunxi/sun4i-spdif.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/sound/soc/sunxi/sun4i-spdif.c b/sound/soc/sunxi/sun4i-spdif.c -index 111111111111..222222222222 100644 ---- a/sound/soc/sunxi/sun4i-spdif.c -+++ b/sound/soc/sunxi/sun4i-spdif.c -@@ -176,6 +176,7 @@ struct sun4i_spdif_quirks { - unsigned int reg_dac_txdata; - bool has_reset; - unsigned int val_fctl_ftx; -+ unsigned int mclk_multiplier; - }; - - struct sun4i_spdif_dev { -@@ -313,6 +314,7 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream, - default: - return -EINVAL; - } -+ mclk *= host->quirks->mclk_multiplier; - - ret = clk_set_rate(host->spdif_clk, mclk); - if (ret < 0) { -@@ -347,6 +349,7 @@ static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream, - default: - return -EINVAL; - } -+ mclk_div *= host->quirks->mclk_multiplier; - - reg_val = 0; - reg_val |= SUN4I_SPDIF_TXCFG_ASS; -@@ -540,24 +543,28 @@ static struct snd_soc_dai_driver sun4i_spdif_dai = { - static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = { - .reg_dac_txdata = SUN4I_SPDIF_TXFIFO, - .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX, -+ .mclk_multiplier = 1, - }; - - static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = { - .reg_dac_txdata = SUN4I_SPDIF_TXFIFO, - .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX, - .has_reset = true, -+ .mclk_multiplier = 1, - }; - - static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = { - .reg_dac_txdata = SUN8I_SPDIF_TXFIFO, - .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX, - .has_reset = true, -+ .mclk_multiplier = 4, - }; - - static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = { - .reg_dac_txdata = SUN8I_SPDIF_TXFIFO, - .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX, - .has_reset = true, -+ .mclk_multiplier = 1, - }; - - static const struct of_device_id sun4i_spdif_of_match[] = { --- -Armbian - diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch new file mode 100644 index 000000000000..6bd5c7665c81 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch @@ -0,0 +1,86 @@ +From b41f5a9ec8841c0342f101585c64c292019543d2 Mon Sep 17 00:00:00 2001 +From: Ryan Walklin +Date: Sun, 29 Sep 2024 22:04:54 +1300 +Subject: clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support + +The DE33 is a newer version of the Allwinner Display Engine IP block, +found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already +supported by the mainline driver. + +The DE33 in the H616 has mixer0 and writeback units. The clocks +and resets required are identical to the H3 and H5 respectively, so use +those existing structs for the H616 description. + +There are two additional 32-bit registers (at offsets 0x24 and 0x28) +which require clearing and setting respectively to bring up the +hardware. The function of these registers is currently unknown, and the +values are taken from the out-of-tree driver. + +Add the required clock description struct and compatible string to the +DE2 driver. + +Signed-off-by: Ryan Walklin +--- + drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +index 7683ea08d8e3..83eab6f132aa 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c ++++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +@@ -5,6 +5,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -239,6 +240,16 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = { + .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), + }; + ++static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = { ++ .ccu_clks = sun8i_de2_ccu_clks, ++ .num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks), ++ ++ .hw_clks = &sun8i_h3_de2_hw_clks, ++ ++ .resets = sun50i_h5_de2_resets, ++ .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), ++}; ++ + static int sunxi_de2_clk_probe(struct platform_device *pdev) + { + struct clk *bus_clk, *mod_clk; +@@ -291,6 +302,16 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) + goto err_disable_mod_clk; + } + ++ /* ++ * The DE33 requires these additional (unknown) registers set ++ * during initialisation. ++ */ ++ if (of_device_is_compatible(pdev->dev.of_node, ++ "allwinner,sun50i-h616-de33-clk")) { ++ writel(0, reg + 0x24); ++ writel(0x0000a980, reg + 0x28); ++ } ++ + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc); + if (ret) + goto err_assert_reset; +@@ -335,6 +356,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { + .compatible = "allwinner,sun50i-h6-de3-clk", + .data = &sun50i_h5_de2_clk_desc, + }, ++ { ++ .compatible = "allwinner,sun50i-h616-de33-clk", ++ .data = &sun50i_h616_de33_clk_desc, ++ }, + { } + }; + MODULE_DEVICE_TABLE(of, sunxi_de2_clk_ids); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch new file mode 100644 index 000000000000..d1e28132f06e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch @@ -0,0 +1,108 @@ +From 6c8bbaf43b8eaf62d4682ce66a35fc7f341f4a13 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Mon, 10 Feb 2025 15:45:13 +0300 +Subject: [PATCH] drm: sun4i: add sun50i-h616-hdmi-phy support + +--- + drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 71 ++++++++++++++++++++++++++ + 1 file changed, 71 insertions(+) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +index 4fa69c463dc4..8a07052037c3 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c ++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +@@ -124,6 +124,66 @@ static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = { + { ~0UL, 0x0000, 0x0000, 0x0000} + }; + ++static const struct dw_hdmi_mpll_config sun50i_h616_mpll_cfg[] = { ++ { ++ 27000000, { ++ {0x00b3, 0x0003}, ++ {0x2153, 0x0003}, ++ {0x40f3, 0x0003}, ++ }, ++ }, { ++ 74250000, { ++ {0x0072, 0x0003}, ++ {0x2145, 0x0003}, ++ {0x4061, 0x0003}, ++ }, ++ }, { ++ 148500000, { ++ {0x0051, 0x0003}, ++ {0x214c, 0x0003}, ++ {0x4064, 0x0003}, ++ }, ++ }, { ++ 297000000, { ++ {0x0040, 0x0003}, ++ {0x3b4c, 0x0003}, ++ {0x5a64, 0x0003}, ++ }, ++ }, { ++ 594000000, { ++ {0x1a40, 0x0003}, ++ {0x3b4c, 0x0003}, ++ {0x5a64, 0x0003}, ++ }, ++ }, { ++ ~0UL, { ++ {0x0000, 0x0000}, ++ {0x0000, 0x0000}, ++ {0x0000, 0x0000}, ++ }, ++ } ++}; ++ ++static const struct dw_hdmi_curr_ctrl sun50i_h616_cur_ctr[] = { ++ /* pixelclk bpp8 bpp10 bpp12 */ ++ { 27000000, { 0x0012, 0x0000, 0x0000 }, }, ++ { 74250000, { 0x0013, 0x0013, 0x0013 }, }, ++ { 148500000, { 0x0019, 0x0019, 0x0019 }, }, ++ { 297000000, { 0x0019, 0x001b, 0x0019 }, }, ++ { 594000000, { 0x0010, 0x0010, 0x0010 }, }, ++ { ~0UL, { 0x0000, 0x0000, 0x0000 }, } ++}; ++ ++static const struct dw_hdmi_phy_config sun50i_h616_phy_config[] = { ++ /*pixelclk symbol term vlev*/ ++ {27000000, 0x8009, 0x0007, 0x02b0}, ++ {74250000, 0x8019, 0x0004, 0x0290}, ++ {148500000, 0x8019, 0x0004, 0x0290}, ++ {297000000, 0x8039, 0x0004, 0x022b}, ++ {594000000, 0x8029, 0x0000, 0x008a}, ++ {~0UL, 0x0000, 0x0000, 0x0000} ++}; ++ + static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, + const struct drm_display_mode *mode) + { +@@ -626,6 +686,13 @@ static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = { + .phy_init = &sun50i_hdmi_phy_init_h6, + }; + ++static const struct sun8i_hdmi_phy_variant sun50i_h616_hdmi_phy = { ++ .cur_ctr = sun50i_h616_cur_ctr, ++ .mpll_cfg = sun50i_h616_mpll_cfg, ++ .phy_cfg = sun50i_h616_phy_config, ++ .phy_init = &sun50i_hdmi_phy_init_h6, ++}; ++ + static const struct of_device_id sun8i_hdmi_phy_of_table[] = { + { + .compatible = "allwinner,sun8i-a83t-hdmi-phy", +@@ -647,6 +714,10 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = { + .compatible = "allwinner,sun50i-h6-hdmi-phy", + .data = &sun50i_h6_hdmi_phy, + }, ++ { ++ .compatible = "allwinner,sun50i-h616-hdmi-phy", ++ .data = &sun50i_h616_hdmi_phy, ++ }, + { /* sentinel */ } + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch new file mode 100644 index 000000000000..f5555d4b0d2e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch @@ -0,0 +1,75 @@ +From 5c2859b3cccd1b1b3f1700fd70c06770f418247a Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:36 +1300 +Subject: drm: sun4i: de2: Initialize layer fields earlier + +drm_universal_plane_init() can already call some callbacks, like +format_mod_supported, during initialization. Because of that, fields +should be initialized beforehand. + +Signed-off-by: Jernej Skrabec +Co-developed-by: Ryan Walklin +Signed-off-by: Ryan Walklin +Reviewed-by: Chen-Yu Tsai +--- + drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 9 +++++---- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 9 +++++---- + 2 files changed, 10 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +index aa987bca1dbb..cb9b694fef10 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +@@ -295,6 +295,11 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, + if (!layer) + return ERR_PTR(-ENOMEM); + ++ layer->mixer = mixer; ++ layer->type = SUN8I_LAYER_TYPE_UI; ++ layer->channel = channel; ++ layer->overlay = 0; ++ + if (index == 0) + type = DRM_PLANE_TYPE_PRIMARY; + +@@ -325,10 +330,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, + } + + drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs); +- layer->mixer = mixer; +- layer->type = SUN8I_LAYER_TYPE_UI; +- layer->channel = channel; +- layer->overlay = 0; + + return layer; + } +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index f3a5329351ca..3c657b069d1f 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -478,6 +478,11 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + if (!layer) + return ERR_PTR(-ENOMEM); + ++ layer->mixer = mixer; ++ layer->type = SUN8I_LAYER_TYPE_VI; ++ layer->channel = index; ++ layer->overlay = 0; ++ + if (mixer->cfg->is_de3) { + formats = sun8i_vi_layer_de3_formats; + format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats); +@@ -536,10 +541,6 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + } + + drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs); +- layer->mixer = mixer; +- layer->type = SUN8I_LAYER_TYPE_VI; +- layer->channel = index; +- layer->overlay = 0; + + return layer; + } +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch new file mode 100644 index 000000000000..9125e4fa06cb --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch @@ -0,0 +1,178 @@ +From 54669ac67e47835b8cc3eea215026385a0050567 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:33 +1300 +Subject: drm: sun4i: de2/de3: Change CSC argument + +Currently, CSC module takes care only for converting YUV to RGB. +However, DE3 is more suited to work in YUV color space. Change CSC mode +argument to format type to be more neutral. New argument only tells +layer format type and doesn't imply output type. + +This commit doesn't make any functional change. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +Reviewed-by: Andre Przywara +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 22 +++++++++++----------- + drivers/gpu/drm/sun4i/sun8i_csc.h | 10 +++++----- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 16 ++++++++-------- + 3 files changed, 24 insertions(+), 24 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index 58480d8e4f70..6ebd1c3aa3ab 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -108,7 +108,7 @@ static const u32 yuv2rgb_de3[2][3][12] = { + }; + + static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, +- enum sun8i_csc_mode mode, ++ enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range) + { +@@ -118,12 +118,12 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, + + table = yuv2rgb[range][encoding]; + +- switch (mode) { +- case SUN8I_CSC_MODE_YUV2RGB: ++ switch (fmt_type) { ++ case FORMAT_TYPE_YUV: + base_reg = SUN8I_CSC_COEFF(base, 0); + regmap_bulk_write(map, base_reg, table, 12); + break; +- case SUN8I_CSC_MODE_YVU2RGB: ++ case FORMAT_TYPE_YVU: + for (i = 0; i < 12; i++) { + if ((i & 3) == 1) + base_reg = SUN8I_CSC_COEFF(base, i + 1); +@@ -141,7 +141,7 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, + } + + static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, +- enum sun8i_csc_mode mode, ++ enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range) + { +@@ -151,12 +151,12 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, + + table = yuv2rgb_de3[range][encoding]; + +- switch (mode) { +- case SUN8I_CSC_MODE_YUV2RGB: ++ switch (fmt_type) { ++ case FORMAT_TYPE_YUV: + addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); + regmap_bulk_write(map, addr, table, 12); + break; +- case SUN8I_CSC_MODE_YVU2RGB: ++ case FORMAT_TYPE_YVU: + for (i = 0; i < 12; i++) { + if ((i & 3) == 1) + addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, +@@ -206,7 +206,7 @@ static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) + } + + void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, +- enum sun8i_csc_mode mode, ++ enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range) + { +@@ -214,14 +214,14 @@ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, + + if (mixer->cfg->is_de3) { + sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer, +- mode, encoding, range); ++ fmt_type, encoding, range); + return; + } + + base = ccsc_base[mixer->cfg->ccsc][layer]; + + sun8i_csc_set_coefficients(mixer->engine.regs, base, +- mode, encoding, range); ++ fmt_type, encoding, range); + } + + void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h +index 828b86fd0cab..7322770f39f0 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.h ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.h +@@ -22,14 +22,14 @@ struct sun8i_mixer; + + #define SUN8I_CSC_CTRL_EN BIT(0) + +-enum sun8i_csc_mode { +- SUN8I_CSC_MODE_OFF, +- SUN8I_CSC_MODE_YUV2RGB, +- SUN8I_CSC_MODE_YVU2RGB, ++enum format_type { ++ FORMAT_TYPE_RGB, ++ FORMAT_TYPE_YUV, ++ FORMAT_TYPE_YVU, + }; + + void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, +- enum sun8i_csc_mode mode, ++ enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range); + void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable); +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index 9c09d9c08496..8a80934e928f 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -193,19 +193,19 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + return 0; + } + +-static u32 sun8i_vi_layer_get_csc_mode(const struct drm_format_info *format) ++static u32 sun8i_vi_layer_get_format_type(const struct drm_format_info *format) + { + if (!format->is_yuv) +- return SUN8I_CSC_MODE_OFF; ++ return FORMAT_TYPE_RGB; + + switch (format->format) { + case DRM_FORMAT_YVU411: + case DRM_FORMAT_YVU420: + case DRM_FORMAT_YVU422: + case DRM_FORMAT_YVU444: +- return SUN8I_CSC_MODE_YVU2RGB; ++ return FORMAT_TYPE_YVU; + default: +- return SUN8I_CSC_MODE_YUV2RGB; ++ return FORMAT_TYPE_YUV; + } + } + +@@ -213,7 +213,7 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, + int overlay, struct drm_plane *plane) + { + struct drm_plane_state *state = plane->state; +- u32 val, ch_base, csc_mode, hw_fmt; ++ u32 val, ch_base, fmt_type, hw_fmt; + const struct drm_format_info *fmt; + int ret; + +@@ -231,9 +231,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay), + SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val); + +- csc_mode = sun8i_vi_layer_get_csc_mode(fmt); +- if (csc_mode != SUN8I_CSC_MODE_OFF) { +- sun8i_csc_set_ccsc_coefficients(mixer, channel, csc_mode, ++ fmt_type = sun8i_vi_layer_get_format_type(fmt); ++ if (fmt_type != FORMAT_TYPE_RGB) { ++ sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_type, + state->color_encoding, + state->color_range); + sun8i_csc_enable_ccsc(mixer, channel, true); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch new file mode 100644 index 000000000000..a487d9d899f4 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch @@ -0,0 +1,221 @@ +From 09744193cdcf400e5a4c54d9309acf5aea3a591c Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:34 +1300 +Subject: drm: sun4i: de2/de3: Merge CSC functions into one + +At the moment the colour space conversion is handled by two functions: +one to setup the conversion parameters, and another one to enable the +conversion. Merging both into one gives more flexibility for upcoming +extensions to support whole YUV pipelines, in the DE33. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +Reviewed-by: Andre Przywara +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 89 ++++++++++---------------- + drivers/gpu/drm/sun4i/sun8i_csc.h | 9 ++- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 11 +--- + 3 files changed, 40 insertions(+), 69 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index 6ebd1c3aa3ab..0dcbc0866ae8 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -107,23 +107,28 @@ static const u32 yuv2rgb_de3[2][3][12] = { + }, + }; + +-static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, +- enum format_type fmt_type, +- enum drm_color_encoding encoding, +- enum drm_color_range range) ++static void sun8i_csc_setup(struct regmap *map, u32 base, ++ enum format_type fmt_type, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range) + { ++ u32 base_reg, val; + const u32 *table; +- u32 base_reg; + int i; + + table = yuv2rgb[range][encoding]; + + switch (fmt_type) { ++ case FORMAT_TYPE_RGB: ++ val = 0; ++ break; + case FORMAT_TYPE_YUV: ++ val = SUN8I_CSC_CTRL_EN; + base_reg = SUN8I_CSC_COEFF(base, 0); + regmap_bulk_write(map, base_reg, table, 12); + break; + case FORMAT_TYPE_YVU: ++ val = SUN8I_CSC_CTRL_EN; + for (i = 0; i < 12; i++) { + if ((i & 3) == 1) + base_reg = SUN8I_CSC_COEFF(base, i + 1); +@@ -135,28 +140,37 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, + } + break; + default: ++ val = 0; + DRM_WARN("Wrong CSC mode specified.\n"); + return; + } ++ ++ regmap_write(map, SUN8I_CSC_CTRL(base), val); + } + +-static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, +- enum format_type fmt_type, +- enum drm_color_encoding encoding, +- enum drm_color_range range) ++static void sun8i_de3_ccsc_setup(struct regmap *map, int layer, ++ enum format_type fmt_type, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range) + { ++ u32 addr, val, mask; + const u32 *table; +- u32 addr; + int i; + ++ mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); + table = yuv2rgb_de3[range][encoding]; + + switch (fmt_type) { ++ case FORMAT_TYPE_RGB: ++ val = 0; ++ break; + case FORMAT_TYPE_YUV: ++ val = mask; + addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); + regmap_bulk_write(map, addr, table, 12); + break; + case FORMAT_TYPE_YVU: ++ val = mask; + for (i = 0; i < 12; i++) { + if ((i & 3) == 1) + addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, +@@ -173,67 +187,30 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, + } + break; + default: ++ val = 0; + DRM_WARN("Wrong CSC mode specified.\n"); + return; + } +-} +- +-static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable) +-{ +- u32 val; +- +- if (enable) +- val = SUN8I_CSC_CTRL_EN; +- else +- val = 0; +- +- regmap_update_bits(map, SUN8I_CSC_CTRL(base), SUN8I_CSC_CTRL_EN, val); +-} +- +-static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) +-{ +- u32 val, mask; +- +- mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); +- +- if (enable) +- val = mask; +- else +- val = 0; + + regmap_update_bits(map, SUN50I_MIXER_BLEND_CSC_CTL(DE3_BLD_BASE), + mask, val); + } + +-void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, +- enum format_type fmt_type, +- enum drm_color_encoding encoding, +- enum drm_color_range range) +-{ +- u32 base; +- +- if (mixer->cfg->is_de3) { +- sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer, +- fmt_type, encoding, range); +- return; +- } +- +- base = ccsc_base[mixer->cfg->ccsc][layer]; +- +- sun8i_csc_set_coefficients(mixer->engine.regs, base, +- fmt_type, encoding, range); +-} +- +-void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) ++void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, ++ enum format_type fmt_type, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range) + { + u32 base; + + if (mixer->cfg->is_de3) { +- sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable); ++ sun8i_de3_ccsc_setup(mixer->engine.regs, layer, ++ fmt_type, encoding, range); + return; + } + + base = ccsc_base[mixer->cfg->ccsc][layer]; + +- sun8i_csc_enable(mixer->engine.regs, base, enable); ++ sun8i_csc_setup(mixer->engine.regs, base, ++ fmt_type, encoding, range); + } +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h +index 7322770f39f0..b7546e06e315 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.h ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.h +@@ -28,10 +28,9 @@ enum format_type { + FORMAT_TYPE_YVU, + }; + +-void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, +- enum format_type fmt_type, +- enum drm_color_encoding encoding, +- enum drm_color_range range); +-void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable); ++void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, ++ enum format_type fmt_type, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range); + + #endif +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index 8a80934e928f..f3a5329351ca 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -232,14 +232,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, + SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val); + + fmt_type = sun8i_vi_layer_get_format_type(fmt); +- if (fmt_type != FORMAT_TYPE_RGB) { +- sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_type, +- state->color_encoding, +- state->color_range); +- sun8i_csc_enable_ccsc(mixer, channel, true); +- } else { +- sun8i_csc_enable_ccsc(mixer, channel, false); +- } ++ sun8i_csc_set_ccsc(mixer, channel, fmt_type, ++ state->color_encoding, ++ state->color_range); + + if (!fmt->is_yuv) + val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch new file mode 100644 index 000000000000..2757ba5e21fd --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch @@ -0,0 +1,38 @@ +From 45d06599927825fe1fa3c374508d6d0c8c9f9f52 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:48 +1300 +Subject: drm: sun4i: de2/de3: add generic blender register reference function + +The DE2 and DE3 engines have a blender register range within the +mixer engine register map, whereas the DE33 separates this out into +a separate display group. + +Prepare for this by adding a function to look the blender reference up, +with a subsequent patch to add a conditional based on the DE type. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h +index 82956cb97cfd..75facc7d1fa6 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h +@@ -224,6 +224,12 @@ sun8i_blender_base(struct sun8i_mixer *mixer) + return mixer->cfg->de_type == sun8i_mixer_de3 ? DE3_BLD_BASE : DE2_BLD_BASE; + } + ++static inline struct regmap * ++sun8i_blender_regmap(struct sun8i_mixer *mixer) ++{ ++ return mixer->engine.regs; ++} ++ + static inline u32 + sun8i_channel_base(struct sun8i_mixer *mixer, int channel) + { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch new file mode 100644 index 000000000000..0df4a242c2ee --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch @@ -0,0 +1,257 @@ +From b49e4fb3439c50eb6effc559366b3e88e2ac2f27 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:45 +1300 +Subject: drm: sun4i: de2/de3: add mixer version enum + +The Allwinner DE2 and DE3 display engine mixers are currently identified +by a simple boolean flag. This will not scale to support additional DE +variants. + +Convert the boolean flag to an enum. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +Reviewed-by: Andre Przywara +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 2 +- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 14 ++++++++++++-- + drivers/gpu/drm/sun4i/sun8i_mixer.h | 11 ++++++++--- + drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 2 +- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 8 ++++---- + drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 4 ++-- + 6 files changed, 28 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index e12a81fa9108..2d5a2cf7cba2 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -365,7 +365,7 @@ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, + { + u32 base; + +- if (mixer->cfg->is_de3) { ++ if (mixer->cfg->de_type == sun8i_mixer_de3) { + sun8i_de3_ccsc_setup(&mixer->engine, layer, + fmt_type, encoding, range); + return; +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c +index a50c583852ed..16e018aa4aae 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c +@@ -584,7 +584,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, + base = sun8i_blender_base(mixer); + + /* Reset registers and disable unused sub-engines */ +- if (mixer->cfg->is_de3) { ++ if (mixer->cfg->de_type == sun8i_mixer_de3) { + for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4) + regmap_write(mixer->engine.regs, i, 0); + +@@ -675,6 +675,7 @@ static void sun8i_mixer_remove(struct platform_device *pdev) + + static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { + .ccsc = CCSC_MIXER0_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .scaler_mask = 0xf, + .scanline_yuv = 2048, + .ui_num = 3, +@@ -683,6 +684,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { + + static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { + .ccsc = CCSC_MIXER1_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .scaler_mask = 0x3, + .scanline_yuv = 2048, + .ui_num = 1, +@@ -691,6 +693,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { + + static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { + .ccsc = CCSC_MIXER0_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .mod_rate = 432000000, + .scaler_mask = 0xf, + .scanline_yuv = 2048, +@@ -700,6 +703,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { + + static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { + .ccsc = CCSC_MIXER0_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .mod_rate = 297000000, + .scaler_mask = 0xf, + .scanline_yuv = 2048, +@@ -709,6 +713,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { + + static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { + .ccsc = CCSC_MIXER1_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .mod_rate = 297000000, + .scaler_mask = 0x3, + .scanline_yuv = 2048, +@@ -717,6 +722,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { + }; + + static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { ++ .de_type = sun8i_mixer_de2, + .vi_num = 2, + .ui_num = 1, + .scaler_mask = 0x3, +@@ -727,6 +733,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { + + static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { + .ccsc = CCSC_D1_MIXER0_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .mod_rate = 297000000, + .scaler_mask = 0x3, + .scanline_yuv = 2048, +@@ -736,6 +743,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { + + static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { + .ccsc = CCSC_MIXER1_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .mod_rate = 297000000, + .scaler_mask = 0x1, + .scanline_yuv = 1024, +@@ -745,6 +753,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { + + static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { + .ccsc = CCSC_MIXER0_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .mod_rate = 297000000, + .scaler_mask = 0xf, + .scanline_yuv = 4096, +@@ -754,6 +763,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { + + static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { + .ccsc = CCSC_MIXER1_LAYOUT, ++ .de_type = sun8i_mixer_de2, + .mod_rate = 297000000, + .scaler_mask = 0x3, + .scanline_yuv = 2048, +@@ -763,7 +773,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { + + static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { + .ccsc = CCSC_MIXER0_LAYOUT, +- .is_de3 = true, ++ .de_type = sun8i_mixer_de3, + .has_formatter = 1, + .mod_rate = 600000000, + .scaler_mask = 0xf, +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h +index 8417b8fef2e1..82956cb97cfd 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h +@@ -151,6 +151,11 @@ enum { + CCSC_D1_MIXER0_LAYOUT, + }; + ++enum sun8i_mixer_type { ++ sun8i_mixer_de2, ++ sun8i_mixer_de3, ++}; ++ + /** + * struct sun8i_mixer_cfg - mixer HW configuration + * @vi_num: number of VI channels +@@ -172,7 +177,7 @@ struct sun8i_mixer_cfg { + int scaler_mask; + int ccsc; + unsigned long mod_rate; +- unsigned int is_de3 : 1; ++ unsigned int de_type; + unsigned int has_formatter : 1; + unsigned int scanline_yuv; + }; +@@ -216,13 +221,13 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine) + static inline u32 + sun8i_blender_base(struct sun8i_mixer *mixer) + { +- return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE; ++ return mixer->cfg->de_type == sun8i_mixer_de3 ? DE3_BLD_BASE : DE2_BLD_BASE; + } + + static inline u32 + sun8i_channel_base(struct sun8i_mixer *mixer, int channel) + { +- if (mixer->cfg->is_de3) ++ if (mixer->cfg->de_type == sun8i_mixer_de3) + return DE3_CH_BASE + channel * DE3_CH_SIZE; + else + return DE2_CH_BASE + channel * DE2_CH_SIZE; +diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c +index ae0806bccac7..504ffa0971a4 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c ++++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c +@@ -93,7 +93,7 @@ static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel) + { + int vi_num = mixer->cfg->vi_num; + +- if (mixer->cfg->is_de3) ++ if (mixer->cfg->de_type == sun8i_mixer_de3) + return DE3_VI_SCALER_UNIT_BASE + + DE3_VI_SCALER_UNIT_SIZE * vi_num + + DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num); +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index 3c657b069d1f..4647e9bcccaa 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -25,7 +25,7 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel, + + ch_base = sun8i_channel_base(mixer, channel); + +- if (mixer->cfg->is_de3) { ++ if (mixer->cfg->de_type >= sun8i_mixer_de3) { + mask = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK | + SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK; + val = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA +@@ -483,7 +483,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + layer->channel = index; + layer->overlay = 0; + +- if (mixer->cfg->is_de3) { ++ if (mixer->cfg->de_type >= sun8i_mixer_de3) { + formats = sun8i_vi_layer_de3_formats; + format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats); + } else { +@@ -507,7 +507,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + + plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num; + +- if (mixer->cfg->vi_num == 1 || mixer->cfg->is_de3) { ++ if (mixer->cfg->vi_num == 1 || mixer->cfg->de_type >= sun8i_mixer_de3) { + ret = drm_plane_create_alpha_property(&layer->plane); + if (ret) { + dev_err(drm->dev, "Couldn't add alpha property\n"); +@@ -524,7 +524,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + + supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) | + BIT(DRM_COLOR_YCBCR_BT709); +- if (mixer->cfg->is_de3) ++ if (mixer->cfg->de_type >= sun8i_mixer_de3) + supported_encodings |= BIT(DRM_COLOR_YCBCR_BT2020); + + supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +index 2e49a6e5f1f1..aa346c3beb30 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +@@ -835,7 +835,7 @@ static const u32 bicubic4coefftab32[480] = { + + static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel) + { +- if (mixer->cfg->is_de3) ++ if (mixer->cfg->de_type == sun8i_mixer_de3) + return DE3_VI_SCALER_UNIT_BASE + + DE3_VI_SCALER_UNIT_SIZE * channel; + else +@@ -982,7 +982,7 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, + cvphase = vphase; + } + +- if (mixer->cfg->is_de3) { ++ if (mixer->cfg->de_type >= sun8i_mixer_de3) { + u32 val; + + if (format->hsub == 1 && format->vsub == 1) +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch new file mode 100644 index 000000000000..96847a05dce8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch @@ -0,0 +1,64 @@ +From 000c586a34ad82e4673e6dfda5457147b0d85606 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:35 +1300 +Subject: drm: sun4i: de2/de3: call csc setup also for UI layer + +Currently, only VI layer calls CSC setup function. This comes from DE2 +limitation, which doesn't have CSC unit for UI layers. However, DE3 has +separate CSC units for each layer. This allows display pipeline to make +output signal in different color spaces. To support both use cases, add +a call to CSC setup function also in UI layer code. For DE2, this will +be a no-op, but it will allow DE3 to output signal in multiple formats. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 8 +++++--- + drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 6 ++++++ + 2 files changed, 11 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index 0dcbc0866ae8..68d955c63b05 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -209,8 +209,10 @@ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, + return; + } + +- base = ccsc_base[mixer->cfg->ccsc][layer]; ++ if (layer < mixer->cfg->vi_num) { ++ base = ccsc_base[mixer->cfg->ccsc][layer]; + +- sun8i_csc_setup(mixer->engine.regs, base, +- fmt_type, encoding, range); ++ sun8i_csc_setup(mixer->engine.regs, base, ++ fmt_type, encoding, range); ++ } + } +diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +index b90e5edef4e8..aa987bca1dbb 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +@@ -20,6 +20,7 @@ + #include + #include + ++#include "sun8i_csc.h" + #include "sun8i_mixer.h" + #include "sun8i_ui_layer.h" + #include "sun8i_ui_scaler.h" +@@ -135,6 +136,11 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel, + SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), + SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val); + ++ /* Note: encoding and range arguments are ignored for RGB */ ++ sun8i_csc_set_ccsc(mixer, channel, FORMAT_TYPE_RGB, ++ DRM_COLOR_YCBCR_BT601, ++ DRM_COLOR_YCBCR_FULL_RANGE); ++ + return 0; + } + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch new file mode 100644 index 000000000000..4357b5b775ab --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch @@ -0,0 +1,121 @@ +From 18890b5c9dbf9270b7f0e42875d6b8bd14ee6624 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:46 +1300 +Subject: drm: sun4i: de2/de3: refactor mixer initialisation + +Now that the DE variant can be selected by enum, take the oppportunity +to factor out some common initialisation code to a separate function. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +Reviewed-by: Andre Przywara +--- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 64 +++++++++++++++-------------- + 1 file changed, 34 insertions(+), 30 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c +index 16e018aa4aae..18745af08954 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c +@@ -468,6 +468,38 @@ static int sun8i_mixer_of_get_id(struct device_node *node) + return of_ep.id; + } + ++static void sun8i_mixer_init(struct sun8i_mixer *mixer) ++{ ++ unsigned int base = sun8i_blender_base(mixer); ++ int plane_cnt, i; ++ ++ /* Enable the mixer */ ++ regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, ++ SUN8I_MIXER_GLOBAL_CTL_RT_EN); ++ ++ /* Set background color to black */ ++ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), ++ SUN8I_MIXER_BLEND_COLOR_BLACK); ++ ++ /* ++ * Set fill color of bottom plane to black. Generally not needed ++ * except when VI plane is at bottom (zpos = 0) and enabled. ++ */ ++ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), ++ SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); ++ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), ++ SUN8I_MIXER_BLEND_COLOR_BLACK); ++ ++ plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num; ++ for (i = 0; i < plane_cnt; i++) ++ regmap_write(mixer->engine.regs, ++ SUN8I_MIXER_BLEND_MODE(base, i), ++ SUN8I_MIXER_BLEND_MODE_DEF); ++ ++ regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), ++ SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); ++} ++ + static int sun8i_mixer_bind(struct device *dev, struct device *master, + void *data) + { +@@ -476,8 +508,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, + struct sun4i_drv *drv = drm->dev_private; + struct sun8i_mixer *mixer; + void __iomem *regs; +- unsigned int base; +- int plane_cnt; + int i, ret; + + /* +@@ -581,8 +611,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, + + list_add_tail(&mixer->engine.list, &drv->engine_list); + +- base = sun8i_blender_base(mixer); +- + /* Reset registers and disable unused sub-engines */ + if (mixer->cfg->de_type == sun8i_mixer_de3) { + for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4) +@@ -598,7 +626,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, + regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0); + regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0); +- } else { ++ } else if (mixer->cfg->de_type == sun8i_mixer_de2) { + for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4) + regmap_write(mixer->engine.regs, i, 0); + +@@ -611,31 +639,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, + regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0); + } + +- /* Enable the mixer */ +- regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, +- SUN8I_MIXER_GLOBAL_CTL_RT_EN); +- +- /* Set background color to black */ +- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), +- SUN8I_MIXER_BLEND_COLOR_BLACK); +- +- /* +- * Set fill color of bottom plane to black. Generally not needed +- * except when VI plane is at bottom (zpos = 0) and enabled. +- */ +- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), +- SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); +- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), +- SUN8I_MIXER_BLEND_COLOR_BLACK); +- +- plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num; +- for (i = 0; i < plane_cnt; i++) +- regmap_write(mixer->engine.regs, +- SUN8I_MIXER_BLEND_MODE(base, i), +- SUN8I_MIXER_BLEND_MODE_DEF); +- +- regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), +- SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); ++ sun8i_mixer_init(mixer); + + return 0; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch new file mode 100644 index 000000000000..ae503d937cb6 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch @@ -0,0 +1,117 @@ +From a756d6b4ac645ac3c18d5758faec068b3c8819a6 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:49 +1300 +Subject: drm: sun4i: de2/de3: use generic register reference function for + layer configuration + +Use the new blender register lookup function where required in the layer +commit and update code. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 5 +++-- + drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 7 +++++-- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 6 ++++-- + 3 files changed, 12 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c +index 18745af08954..600084286b39 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c +@@ -277,6 +277,7 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, + { + struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); + u32 bld_base = sun8i_blender_base(mixer); ++ struct regmap *bld_regs = sun8i_blender_regmap(mixer); + struct drm_plane_state *plane_state; + struct drm_plane *plane; + u32 route = 0, pipe_en = 0; +@@ -316,8 +317,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, + pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); + } + +- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route); +- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), ++ regmap_write(bld_regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route); ++ regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), + pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); + + regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, +diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +index cb9b694fef10..7f1231cf0f01 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +@@ -24,6 +24,7 @@ + #include "sun8i_mixer.h" + #include "sun8i_ui_layer.h" + #include "sun8i_ui_scaler.h" ++#include "sun8i_vi_scaler.h" + + static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel, + int overlay, struct drm_plane *plane) +@@ -52,6 +53,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, + { + struct drm_plane_state *state = plane->state; + u32 src_w, src_h, dst_w, dst_h; ++ struct regmap *bld_regs; + u32 bld_base, ch_base; + u32 outsize, insize; + u32 hphase, vphase; +@@ -60,6 +62,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, + channel, overlay); + + bld_base = sun8i_blender_base(mixer); ++ bld_regs = sun8i_blender_regmap(mixer); + ch_base = sun8i_channel_base(mixer, channel); + + src_w = drm_rect_width(&state->src) >> 16; +@@ -104,10 +107,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, + DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", + state->dst.x1, state->dst.y1); + DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); +- regmap_write(mixer->engine.regs, ++ regmap_write(bld_regs, + SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), + SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1)); +- regmap_write(mixer->engine.regs, ++ regmap_write(bld_regs, + SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), + outsize); + +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index e348fd0a3d81..d19349eecc9d 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -55,6 +55,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + struct drm_plane_state *state = plane->state; + const struct drm_format_info *format = state->fb->format; + u32 src_w, src_h, dst_w, dst_h; ++ struct regmap *bld_regs; + u32 bld_base, ch_base; + u32 outsize, insize; + u32 hphase, vphase; +@@ -66,6 +67,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + channel, overlay); + + bld_base = sun8i_blender_base(mixer); ++ bld_regs = sun8i_blender_regmap(mixer); + ch_base = sun8i_channel_base(mixer, channel); + + src_w = drm_rect_width(&state->src) >> 16; +@@ -182,10 +184,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", + state->dst.x1, state->dst.y1); + DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); +- regmap_write(mixer->engine.regs, ++ regmap_write(bld_regs, + SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), + SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1)); +- regmap_write(mixer->engine.regs, ++ regmap_write(bld_regs, + SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), + outsize); + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch new file mode 100644 index 000000000000..14f17b6d5d69 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch @@ -0,0 +1,164 @@ +From 8bdcc131fedb576a8db65bb6e87ca8742660add0 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:37 +1300 +Subject: drm: sun4i: de3: Add YUV formatter module + +The display engine formatter (FMT) module is present in the DE3 engine +and provides YUV444 to YUV422/YUV420 conversion, format re-mapping and +color depth conversion. + +Add support for this module. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/Makefile | 3 +- + drivers/gpu/drm/sun4i/sun50i_fmt.c | 82 ++++++++++++++++++++++++++++++ + drivers/gpu/drm/sun4i/sun50i_fmt.h | 32 ++++++++++++ + 3 files changed, 116 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/sun4i/sun50i_fmt.c + create mode 100644 drivers/gpu/drm/sun4i/sun50i_fmt.h + +diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile +index bad7497a0d11..3f516329f51e 100644 +--- a/drivers/gpu/drm/sun4i/Makefile ++++ b/drivers/gpu/drm/sun4i/Makefile +@@ -16,7 +16,8 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk.o + + sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \ + sun8i_vi_layer.o sun8i_ui_scaler.o \ +- sun8i_vi_scaler.o sun8i_csc.o ++ sun8i_vi_scaler.o sun8i_csc.o \ ++ sun50i_fmt.o + + sun4i-tcon-y += sun4i_crtc.o + sun4i-tcon-y += sun4i_tcon_dclk.o +diff --git a/drivers/gpu/drm/sun4i/sun50i_fmt.c b/drivers/gpu/drm/sun4i/sun50i_fmt.c +new file mode 100644 +index 000000000000..050a8716ae86 +--- /dev/null ++++ b/drivers/gpu/drm/sun4i/sun50i_fmt.c +@@ -0,0 +1,82 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (C) Jernej Skrabec ++ */ ++ ++#include ++ ++#include "sun50i_fmt.h" ++ ++static bool sun50i_fmt_is_10bit(u32 format) ++{ ++ switch (format) { ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static u32 sun50i_fmt_get_colorspace(u32 format) ++{ ++ switch (format) { ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ return SUN50I_FMT_CS_YUV420; ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ return SUN50I_FMT_CS_YUV422; ++ default: ++ return SUN50I_FMT_CS_YUV444RGB; ++ } ++} ++ ++static void sun50i_fmt_de3_limits(u32 *limits, u32 colorspace, bool bit10) ++{ ++ if (colorspace != SUN50I_FMT_CS_YUV444RGB) { ++ limits[0] = SUN50I_FMT_LIMIT(64, 940); ++ limits[1] = SUN50I_FMT_LIMIT(64, 960); ++ limits[2] = SUN50I_FMT_LIMIT(64, 960); ++ } else if (bit10) { ++ limits[0] = SUN50I_FMT_LIMIT(0, 1023); ++ limits[1] = SUN50I_FMT_LIMIT(0, 1023); ++ limits[2] = SUN50I_FMT_LIMIT(0, 1023); ++ } else { ++ limits[0] = SUN50I_FMT_LIMIT(0, 1021); ++ limits[1] = SUN50I_FMT_LIMIT(0, 1021); ++ limits[2] = SUN50I_FMT_LIMIT(0, 1021); ++ } ++} ++ ++void sun50i_fmt_setup(struct sun8i_mixer *mixer, u16 width, ++ u16 height, u32 format) ++{ ++ u32 colorspace, limit[3], base; ++ struct regmap *regs; ++ bool bit10; ++ ++ colorspace = sun50i_fmt_get_colorspace(format); ++ bit10 = sun50i_fmt_is_10bit(format); ++ base = SUN50I_FMT_DE3; ++ regs = sun8i_blender_regmap(mixer); ++ ++ sun50i_fmt_de3_limits(limit, colorspace, bit10); ++ ++ regmap_write(regs, SUN50I_FMT_CTRL(base), 0); ++ ++ regmap_write(regs, SUN50I_FMT_SIZE(base), ++ SUN8I_MIXER_SIZE(width, height)); ++ regmap_write(regs, SUN50I_FMT_SWAP(base), 0); ++ regmap_write(regs, SUN50I_FMT_DEPTH(base), bit10); ++ regmap_write(regs, SUN50I_FMT_FORMAT(base), colorspace); ++ regmap_write(regs, SUN50I_FMT_COEF(base), 0); ++ ++ regmap_write(regs, SUN50I_FMT_LMT_Y(base), limit[0]); ++ regmap_write(regs, SUN50I_FMT_LMT_C0(base), limit[1]); ++ regmap_write(regs, SUN50I_FMT_LMT_C1(base), limit[2]); ++ ++ regmap_write(regs, SUN50I_FMT_CTRL(base), 1); ++} +diff --git a/drivers/gpu/drm/sun4i/sun50i_fmt.h b/drivers/gpu/drm/sun4i/sun50i_fmt.h +new file mode 100644 +index 000000000000..4127f7206aad +--- /dev/null ++++ b/drivers/gpu/drm/sun4i/sun50i_fmt.h +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Copyright (C) Jernej Skrabec ++ */ ++ ++#ifndef _SUN50I_FMT_H_ ++#define _SUN50I_FMT_H_ ++ ++#include "sun8i_mixer.h" ++ ++#define SUN50I_FMT_DE3 0xa8000 ++ ++#define SUN50I_FMT_CTRL(base) ((base) + 0x00) ++#define SUN50I_FMT_SIZE(base) ((base) + 0x04) ++#define SUN50I_FMT_SWAP(base) ((base) + 0x08) ++#define SUN50I_FMT_DEPTH(base) ((base) + 0x0c) ++#define SUN50I_FMT_FORMAT(base) ((base) + 0x10) ++#define SUN50I_FMT_COEF(base) ((base) + 0x14) ++#define SUN50I_FMT_LMT_Y(base) ((base) + 0x20) ++#define SUN50I_FMT_LMT_C0(base) ((base) + 0x24) ++#define SUN50I_FMT_LMT_C1(base) ((base) + 0x28) ++ ++#define SUN50I_FMT_LIMIT(low, high) (((high) << 16) | (low)) ++ ++#define SUN50I_FMT_CS_YUV444RGB 0 ++#define SUN50I_FMT_CS_YUV422 1 ++#define SUN50I_FMT_CS_YUV420 2 ++ ++void sun50i_fmt_setup(struct sun8i_mixer *mixer, u16 width, ++ u16 height, u32 format); ++ ++#endif +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch new file mode 100644 index 000000000000..e4d21564c020 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch @@ -0,0 +1,569 @@ +From 0788787d1240dba85ecbbdb559cb46d413975656 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:50 +1300 +Subject: drm: sun4i: de3: Implement AFBC support + +Buffers, compressed with AFBC, are supported by the DE3 and above, and +are generally more efficient for memory transfers. Add support for them. + +Currently it's implemented only for VI layers, but vendor code and +documentation suggest UI layers can have them too. However, I haven't +observed any SoC with such feature. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/Makefile | 2 +- + drivers/gpu/drm/sun4i/sun50i_afbc.c | 250 +++++++++++++++++++++++++ + drivers/gpu/drm/sun4i/sun50i_afbc.h | 87 +++++++++ + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 84 +++++++-- + 4 files changed, 409 insertions(+), 14 deletions(-) + create mode 100644 drivers/gpu/drm/sun4i/sun50i_afbc.c + create mode 100644 drivers/gpu/drm/sun4i/sun50i_afbc.h + +diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile +index 3f516329f51e..78290f1660fb 100644 +--- a/drivers/gpu/drm/sun4i/Makefile ++++ b/drivers/gpu/drm/sun4i/Makefile +@@ -17,7 +17,7 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk.o + sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \ + sun8i_vi_layer.o sun8i_ui_scaler.o \ + sun8i_vi_scaler.o sun8i_csc.o \ +- sun50i_fmt.o ++ sun50i_fmt.o sun50i_afbc.o + + sun4i-tcon-y += sun4i_crtc.o + sun4i-tcon-y += sun4i_tcon_dclk.o +diff --git a/drivers/gpu/drm/sun4i/sun50i_afbc.c b/drivers/gpu/drm/sun4i/sun50i_afbc.c +new file mode 100644 +index 000000000000..b55e1c553371 +--- /dev/null ++++ b/drivers/gpu/drm/sun4i/sun50i_afbc.c +@@ -0,0 +1,250 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (C) Jernej Skrabec ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "sun50i_afbc.h" ++#include "sun8i_mixer.h" ++ ++static u32 sun50i_afbc_get_base(struct sun8i_mixer *mixer, unsigned int channel) ++{ ++ u32 base = sun8i_channel_base(mixer, channel); ++ ++ if (mixer->cfg->de_type == sun8i_mixer_de3) ++ return base + SUN50I_AFBC_CH_OFFSET; ++ ++ return base + 0x4000; ++} ++ ++bool sun50i_afbc_format_mod_supported(struct sun8i_mixer *mixer, ++ u32 format, u64 modifier) ++{ ++ u64 mode; ++ ++ if (modifier == DRM_FORMAT_MOD_INVALID) ++ return false; ++ ++ if (modifier == DRM_FORMAT_MOD_LINEAR) { ++ if (format == DRM_FORMAT_YUV420_8BIT || ++ format == DRM_FORMAT_YUV420_10BIT || ++ format == DRM_FORMAT_Y210) ++ return false; ++ return true; ++ } ++ ++ if (mixer->cfg->de_type == sun8i_mixer_de2) ++ return false; ++ ++ mode = AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | ++ AFBC_FORMAT_MOD_SPARSE | ++ AFBC_FORMAT_MOD_SPLIT; ++ ++ switch (format) { ++ case DRM_FORMAT_RGBA8888: ++ case DRM_FORMAT_RGB888: ++ case DRM_FORMAT_RGB565: ++ case DRM_FORMAT_RGBA4444: ++ case DRM_FORMAT_RGBA5551: ++ case DRM_FORMAT_RGBA1010102: ++ mode |= AFBC_FORMAT_MOD_YTR; ++ break; ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_Y210: ++ case DRM_FORMAT_YUV420_8BIT: ++ case DRM_FORMAT_YUV420_10BIT: ++ break; ++ default: ++ return false; ++ } ++ ++ return modifier == DRM_FORMAT_MOD_ARM_AFBC(mode); ++} ++ ++void sun50i_afbc_atomic_update(struct sun8i_mixer *mixer, unsigned int channel, ++ struct drm_plane *plane) ++{ ++ struct drm_plane_state *state = plane->state; ++ struct drm_framebuffer *fb = state->fb; ++ const struct drm_format_info *format = fb->format; ++ struct drm_gem_dma_object *gem; ++ u32 base, val, src_w, src_h; ++ u32 def_color0, def_color1; ++ struct regmap *regs; ++ dma_addr_t dma_addr; ++ ++ base = sun50i_afbc_get_base(mixer, channel); ++ regs = mixer->engine.regs; ++ ++ src_w = drm_rect_width(&state->src) >> 16; ++ src_h = drm_rect_height(&state->src) >> 16; ++ ++ val = SUN50I_FBD_SIZE_HEIGHT(src_h); ++ val |= SUN50I_FBD_SIZE_WIDTH(src_w); ++ regmap_write(regs, SUN50I_FBD_SIZE(base), val); ++ ++ val = SUN50I_FBD_BLK_SIZE_HEIGHT(DIV_ROUND_UP(src_h, 16)); ++ val = SUN50I_FBD_BLK_SIZE_WIDTH(DIV_ROUND_UP(src_w, 16)); ++ regmap_write(regs, SUN50I_FBD_BLK_SIZE(base), val); ++ ++ val = SUN50I_FBD_SRC_CROP_TOP(0); ++ val |= SUN50I_FBD_SRC_CROP_LEFT(0); ++ regmap_write(regs, SUN50I_FBD_SRC_CROP(base), val); ++ ++ val = SUN50I_FBD_LAY_CROP_TOP(state->src.y1 >> 16); ++ val |= SUN50I_FBD_LAY_CROP_LEFT(state->src.x1 >> 16); ++ regmap_write(regs, SUN50I_FBD_LAY_CROP(base), val); ++ ++ /* ++ * Default color is always set to white, in colorspace and bitness ++ * that coresponds to used format. If it is actually used or not ++ * depends on AFBC buffer. At least in Cedrus it can be turned on ++ * or off. ++ * NOTE: G and B channels are off by 1 (up). It's unclear if this ++ * is because HW need such value or it is due to good enough code ++ * in vendor driver and HW clips the value anyway. ++ */ ++ def_color0 = 0; ++ def_color1 = 0; ++ ++ val = 0; ++ switch (format->format) { ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_YUV420_10BIT: ++ val |= SUN50I_FBD_FMT_SBS1(2); ++ val |= SUN50I_FBD_FMT_SBS0(1); ++ break; ++ case DRM_FORMAT_Y210: ++ val |= SUN50I_FBD_FMT_SBS1(3); ++ val |= SUN50I_FBD_FMT_SBS0(2); ++ break; ++ default: ++ val |= SUN50I_FBD_FMT_SBS1(1); ++ val |= SUN50I_FBD_FMT_SBS0(1); ++ break; ++ } ++ switch (format->format) { ++ case DRM_FORMAT_RGBA8888: ++ val |= SUN50I_FBD_FMT_YUV_TRAN; ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGBA_8888); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(255) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(255); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(256) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(256); ++ break; ++ case DRM_FORMAT_RGB888: ++ val |= SUN50I_FBD_FMT_YUV_TRAN; ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGB_888); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(255); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(256) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(256); ++ break; ++ case DRM_FORMAT_RGB565: ++ val |= SUN50I_FBD_FMT_YUV_TRAN; ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGB_565); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(31); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(64) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(32); ++ break; ++ case DRM_FORMAT_RGBA4444: ++ val |= SUN50I_FBD_FMT_YUV_TRAN; ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGBA_4444); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(15) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(15); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(16) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(16); ++ break; ++ case DRM_FORMAT_RGBA5551: ++ val |= SUN50I_FBD_FMT_YUV_TRAN; ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGBA_5551); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(1) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(31); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(32) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(32); ++ break; ++ case DRM_FORMAT_RGBA1010102: ++ val |= SUN50I_FBD_FMT_YUV_TRAN; ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGBA1010102); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(3) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(1023); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(1024) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(1024); ++ break; ++ case DRM_FORMAT_YUV420_8BIT: ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_YUV420); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(255); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(128) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(128); ++ break; ++ case DRM_FORMAT_YUYV: ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_YUV422); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(255); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(128) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(128); ++ break; ++ case DRM_FORMAT_YUV420_10BIT: ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_P010); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(1023); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(512) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(512); ++ break; ++ case DRM_FORMAT_Y210: ++ val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_P210); ++ def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) | ++ SUN50I_FBD_DEFAULT_COLOR0_YR(1023); ++ def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(512) | ++ SUN50I_FBD_DEFAULT_COLOR1_VB(512); ++ break; ++ } ++ regmap_write(regs, SUN50I_FBD_FMT(base), val); ++ ++ /* Get the physical address of the buffer in memory */ ++ gem = drm_fb_dma_get_gem_obj(fb, 0); ++ ++ DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->dma_addr); ++ ++ /* Compute the start of the displayed memory */ ++ dma_addr = gem->dma_addr + fb->offsets[0]; ++ ++ regmap_write(regs, SUN50I_FBD_LADDR(base), lower_32_bits(dma_addr)); ++ regmap_write(regs, SUN50I_FBD_HADDR(base), upper_32_bits(dma_addr)); ++ ++ val = SUN50I_FBD_OVL_SIZE_HEIGHT(src_h); ++ val |= SUN50I_FBD_OVL_SIZE_WIDTH(src_w); ++ regmap_write(regs, SUN50I_FBD_OVL_SIZE(base), val); ++ ++ val = SUN50I_FBD_OVL_COOR_Y(0); ++ val |= SUN50I_FBD_OVL_COOR_X(0); ++ regmap_write(regs, SUN50I_FBD_OVL_COOR(base), val); ++ ++ regmap_write(regs, SUN50I_FBD_OVL_BG_COLOR(base), ++ SUN8I_MIXER_BLEND_COLOR_BLACK); ++ regmap_write(regs, SUN50I_FBD_DEFAULT_COLOR0(base), def_color0); ++ regmap_write(regs, SUN50I_FBD_DEFAULT_COLOR1(base), def_color1); ++ ++ val = SUN50I_FBD_CTL_GLB_ALPHA(state->alpha >> 16); ++ val |= SUN50I_FBD_CTL_CLK_GATE; ++ val |= (state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? ++ SUN50I_FBD_CTL_ALPHA_MODE_PIXEL : ++ SUN50I_FBD_CTL_ALPHA_MODE_COMBINED; ++ val |= SUN50I_FBD_CTL_FBD_EN; ++ regmap_write(regs, SUN50I_FBD_CTL(base), val); ++} ++ ++void sun50i_afbc_disable(struct sun8i_mixer *mixer, unsigned int channel) ++{ ++ u32 base = sun50i_afbc_get_base(mixer, channel); ++ ++ regmap_write(mixer->engine.regs, SUN50I_FBD_CTL(base), 0); ++} +diff --git a/drivers/gpu/drm/sun4i/sun50i_afbc.h b/drivers/gpu/drm/sun4i/sun50i_afbc.h +new file mode 100644 +index 000000000000..cea685c86855 +--- /dev/null ++++ b/drivers/gpu/drm/sun4i/sun50i_afbc.h +@@ -0,0 +1,87 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Copyright (C) Jernej Skrabec ++ */ ++ ++#ifndef _SUN50I_AFBC_H_ ++#define _SUN50I_AFBC_H_ ++ ++#include ++ ++#define SUN50I_AFBC_CH_OFFSET 0x300 ++ ++#define SUN50I_AFBC_RGBA_8888 0x02 ++#define SUN50I_AFBC_RGB_888 0x08 ++#define SUN50I_AFBC_RGB_565 0x0a ++#define SUN50I_AFBC_RGBA_4444 0x0e ++#define SUN50I_AFBC_RGBA_5551 0x12 ++#define SUN50I_AFBC_RGBA1010102 0x16 ++#define SUN50I_AFBC_YUV422 0x26 ++#define SUN50I_AFBC_YUV420 0x2a ++#define SUN50I_AFBC_P010 0x30 ++#define SUN50I_AFBC_P210 0x32 ++ ++#define SUN50I_FBD_CTL(base) ((base) + 0x00) ++#define SUN50I_FBD_CTL_GLB_ALPHA(v) ((v) << 24) ++#define SUN50I_FBD_CTL_CLK_GATE BIT(4) ++#define SUN50I_FBD_CTL_ALPHA_MODE_PIXEL ((0) << 2) ++#define SUN50I_FBD_CTL_ALPHA_MODE_LAYER ((1) << 2) ++#define SUN50I_FBD_CTL_ALPHA_MODE_COMBINED ((2) << 2) ++#define SUN50I_FBD_CTL_FBD_FCEN BIT(1) ++#define SUN50I_FBD_CTL_FBD_EN BIT(0) ++ ++#define SUN50I_FBD_SIZE(base) ((base) + 0x08) ++#define SUN50I_FBD_SIZE_HEIGHT(v) (((v) - 1) << 16) ++#define SUN50I_FBD_SIZE_WIDTH(v) (((v) - 1) << 0) ++ ++#define SUN50I_FBD_BLK_SIZE(base) ((base) + 0x0c) ++#define SUN50I_FBD_BLK_SIZE_HEIGHT(v) ((v) << 16) ++#define SUN50I_FBD_BLK_SIZE_WIDTH(v) ((v) << 0) ++ ++#define SUN50I_FBD_SRC_CROP(base) ((base) + 0x10) ++#define SUN50I_FBD_SRC_CROP_TOP(v) ((v) << 16) ++#define SUN50I_FBD_SRC_CROP_LEFT(v) ((v) << 0) ++ ++#define SUN50I_FBD_LAY_CROP(base) ((base) + 0x14) ++#define SUN50I_FBD_LAY_CROP_TOP(v) ((v) << 16) ++#define SUN50I_FBD_LAY_CROP_LEFT(v) ((v) << 0) ++ ++#define SUN50I_FBD_FMT(base) ((base) + 0x18) ++#define SUN50I_FBD_FMT_SBS1(v) ((v) << 18) ++#define SUN50I_FBD_FMT_SBS0(v) ((v) << 16) ++#define SUN50I_FBD_FMT_YUV_TRAN BIT(7) ++#define SUN50I_FBD_FMT_IN_FMT(v) ((v) << 0) ++ ++#define SUN50I_FBD_LADDR(base) ((base) + 0x20) ++#define SUN50I_FBD_HADDR(base) ((base) + 0x24) ++ ++#define SUN50I_FBD_OVL_SIZE(base) ((base) + 0x30) ++#define SUN50I_FBD_OVL_SIZE_HEIGHT(v) (((v) - 1) << 16) ++#define SUN50I_FBD_OVL_SIZE_WIDTH(v) (((v) - 1) << 0) ++ ++#define SUN50I_FBD_OVL_COOR(base) ((base) + 0x34) ++#define SUN50I_FBD_OVL_COOR_Y(v) ((v) << 16) ++#define SUN50I_FBD_OVL_COOR_X(v) ((v) << 0) ++ ++#define SUN50I_FBD_OVL_BG_COLOR(base) ((base) + 0x38) ++#define SUN50I_FBD_OVL_FILL_COLOR(base) ((base) + 0x3c) ++ ++#define SUN50I_FBD_DEFAULT_COLOR0(base) ((base) + 0x50) ++#define SUN50I_FBD_DEFAULT_COLOR0_ALPHA(v) ((v) << 16) ++#define SUN50I_FBD_DEFAULT_COLOR0_YR(v) ((v) << 0) ++ ++#define SUN50I_FBD_DEFAULT_COLOR1(base) ((base) + 0x54) ++#define SUN50I_FBD_DEFAULT_COLOR1_VB(v) ((v) << 16) ++#define SUN50I_FBD_DEFAULT_COLOR1_UG(v) ((v) << 0) ++ ++struct sun8i_mixer; ++struct drm_plane; ++ ++bool sun50i_afbc_format_mod_supported(struct sun8i_mixer *mixer, ++ u32 format, u64 modifier); ++ ++void sun50i_afbc_atomic_update(struct sun8i_mixer *mixer, unsigned int channel, ++ struct drm_plane *plane); ++void sun50i_afbc_disable(struct sun8i_mixer *mixer, unsigned int channel); ++ ++#endif +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index d19349eecc9d..84f8917e2dd8 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -11,8 +11,10 @@ + #include + #include + #include ++#include + #include + ++#include "sun50i_afbc.h" + #include "sun8i_csc.h" + #include "sun8i_mixer.h" + #include "sun8i_vi_layer.h" +@@ -50,7 +52,7 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel, + + static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + int overlay, struct drm_plane *plane, +- unsigned int zpos) ++ unsigned int zpos, bool afbc) + { + struct drm_plane_state *state = plane->state; + const struct drm_format_info *format = state->fb->format; +@@ -135,7 +137,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + + required = src_h * 100 / dst_h; + +- if (ability < required) { ++ if (!afbc && ability < required) { + DRM_DEBUG_DRIVER("Using vertical coarse scaling\n"); + vm = src_h; + vn = (u32)ability * dst_h / 100; +@@ -145,7 +147,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + /* it seems that every RGB scaler has buffer for 2048 pixels */ + scanline = subsampled ? mixer->cfg->scanline_yuv : 2048; + +- if (src_w > scanline) { ++ if (!afbc && src_w > scanline) { + DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n"); + hm = src_w; + hn = scanline; +@@ -308,6 +310,15 @@ static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel, + return 0; + } + ++static void sun8i_vi_layer_prepare_non_linear(struct sun8i_mixer *mixer, ++ int channel, int overlay) ++{ ++ u32 base = sun8i_channel_base(mixer, channel); ++ ++ regmap_write(mixer->engine.regs, ++ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, overlay), 0); ++} ++ + static int sun8i_vi_layer_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) + { +@@ -348,18 +359,45 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, + struct sun8i_layer *layer = plane_to_sun8i_layer(plane); + unsigned int zpos = new_state->normalized_zpos; + struct sun8i_mixer *mixer = layer->mixer; ++ struct drm_framebuffer *fb = plane->state->fb; ++ bool afbc = drm_is_afbc(fb->modifier); + +- if (!new_state->crtc || !new_state->visible) ++ if (!new_state->crtc || !new_state->visible) { ++ if (mixer->cfg->de_type >= sun8i_mixer_de3) ++ sun50i_afbc_disable(mixer, layer->channel); + return; ++ } + + sun8i_vi_layer_update_coord(mixer, layer->channel, +- layer->overlay, plane, zpos); +- sun8i_vi_layer_update_alpha(mixer, layer->channel, +- layer->overlay, plane); +- sun8i_vi_layer_update_formats(mixer, layer->channel, +- layer->overlay, plane); +- sun8i_vi_layer_update_buffer(mixer, layer->channel, +- layer->overlay, plane); ++ layer->overlay, plane, zpos, afbc); ++ ++ if (afbc) { ++ u32 fmt_type; ++ ++ sun8i_vi_layer_prepare_non_linear(mixer, layer->channel, ++ layer->overlay); ++ sun50i_afbc_atomic_update(mixer, layer->channel, plane); ++ ++ fmt_type = sun8i_vi_layer_get_format_type(fb->format); ++ sun8i_csc_set_ccsc(mixer, layer->channel, fmt_type, ++ plane->state->color_encoding, ++ plane->state->color_range); ++ } else { ++ sun8i_vi_layer_update_alpha(mixer, layer->channel, ++ layer->overlay, plane); ++ sun8i_vi_layer_update_formats(mixer, layer->channel, ++ layer->overlay, plane); ++ sun8i_vi_layer_update_buffer(mixer, layer->channel, ++ layer->overlay, plane); ++ } ++} ++ ++static bool sun8i_vi_layer_format_mod_supported(struct drm_plane *plane, ++ u32 format, u64 modifier) ++{ ++ struct sun8i_layer *layer = plane_to_sun8i_layer(plane); ++ ++ return sun50i_afbc_format_mod_supported(layer->mixer, format, modifier); + } + + static const struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = { +@@ -374,6 +412,7 @@ static const struct drm_plane_funcs sun8i_vi_layer_funcs = { + .disable_plane = drm_atomic_helper_disable_plane, + .reset = drm_atomic_helper_plane_reset, + .update_plane = drm_atomic_helper_update_plane, ++ .format_mod_supported = sun8i_vi_layer_format_mod_supported, + }; + + /* +@@ -457,6 +496,11 @@ static const u32 sun8i_vi_layer_de3_formats[] = { + DRM_FORMAT_YVU411, + DRM_FORMAT_YVU420, + DRM_FORMAT_YVU422, ++ ++ /* AFBC only formats */ ++ DRM_FORMAT_YUV420_8BIT, ++ DRM_FORMAT_YUV420_10BIT, ++ DRM_FORMAT_Y210, + }; + + static const uint64_t sun8i_layer_modifiers[] = { +@@ -464,6 +508,18 @@ static const uint64_t sun8i_layer_modifiers[] = { + DRM_FORMAT_MOD_INVALID + }; + ++static const uint64_t sun50i_layer_de3_modifiers[] = { ++ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | ++ AFBC_FORMAT_MOD_SPARSE | ++ AFBC_FORMAT_MOD_SPLIT), ++ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | ++ AFBC_FORMAT_MOD_YTR | ++ AFBC_FORMAT_MOD_SPARSE | ++ AFBC_FORMAT_MOD_SPLIT), ++ DRM_FORMAT_MOD_LINEAR, ++ DRM_FORMAT_MOD_INVALID ++}; ++ + struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + struct sun8i_mixer *mixer, + int index) +@@ -472,6 +528,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + u32 supported_encodings, supported_ranges; + unsigned int plane_cnt, format_count; + struct sun8i_layer *layer; ++ const uint64_t *modifiers; + const u32 *formats; + int ret; + +@@ -487,9 +544,11 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + if (mixer->cfg->de_type >= sun8i_mixer_de3) { + formats = sun8i_vi_layer_de3_formats; + format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats); ++ modifiers = sun50i_layer_de3_modifiers; + } else { + formats = sun8i_vi_layer_formats; + format_count = ARRAY_SIZE(sun8i_vi_layer_formats); ++ modifiers = sun8i_layer_modifiers; + } + + if (!mixer->cfg->ui_num && index == 0) +@@ -499,8 +558,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, + ret = drm_universal_plane_init(drm, &layer->plane, 0, + &sun8i_vi_layer_funcs, + formats, format_count, +- sun8i_layer_modifiers, +- type, NULL); ++ modifiers, type, NULL); + if (ret) { + dev_err(drm->dev, "Couldn't initialize layer\n"); + return ERR_PTR(ret); +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch new file mode 100644 index 000000000000..8a814bcaf3db --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch @@ -0,0 +1,126 @@ +From 3b6462ebad249f4762acfd8e262442bb0cda95b4 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:40 +1300 +Subject: drm: sun4i: de3: add YUV support to the DE3 mixer + +The mixer in the DE3 display engine supports YUV 8 and 10 bit +formats in addition to 8-bit RGB. Add the required register +configuration and format enumeration callback functions to the mixer, +and store the in-use output format (defaulting to RGB) and color +encoding in engine variables. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 53 ++++++++++++++++++++++++++-- + drivers/gpu/drm/sun4i/sunxi_engine.h | 5 +++ + 2 files changed, 55 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c +index 252827715de1..a50c583852ed 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c +@@ -23,7 +23,10 @@ + #include + #include + ++#include ++ + #include "sun4i_drv.h" ++#include "sun50i_fmt.h" + #include "sun8i_mixer.h" + #include "sun8i_ui_layer.h" + #include "sun8i_vi_layer.h" +@@ -390,12 +393,52 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, + + DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", + interlaced ? "on" : "off"); ++ ++ if (engine->format == MEDIA_BUS_FMT_RGB888_1X24) ++ val = SUN8I_MIXER_BLEND_COLOR_BLACK; ++ else ++ val = 0xff108080; ++ ++ regmap_write(mixer->engine.regs, ++ SUN8I_MIXER_BLEND_BKCOLOR(bld_base), val); ++ regmap_write(mixer->engine.regs, ++ SUN8I_MIXER_BLEND_ATTR_FCOLOR(bld_base, 0), val); ++ ++ if (mixer->cfg->has_formatter) ++ sun50i_fmt_setup(mixer, mode->hdisplay, ++ mode->vdisplay, mixer->engine.format); ++} ++ ++static u32 *sun8i_mixer_get_supported_fmts(struct sunxi_engine *engine, u32 *num) ++{ ++ struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); ++ u32 *formats, count; ++ ++ count = 0; ++ ++ formats = kcalloc(5, sizeof(*formats), GFP_KERNEL); ++ if (!formats) ++ return NULL; ++ ++ if (mixer->cfg->has_formatter) { ++ formats[count++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; ++ formats[count++] = MEDIA_BUS_FMT_YUV8_1X24; ++ formats[count++] = MEDIA_BUS_FMT_UYVY8_1X16; ++ formats[count++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; ++ } ++ ++ formats[count++] = MEDIA_BUS_FMT_RGB888_1X24; ++ ++ *num = count; ++ ++ return formats; + } + + static const struct sunxi_engine_ops sun8i_engine_ops = { +- .commit = sun8i_mixer_commit, +- .layers_init = sun8i_layers_init, +- .mode_set = sun8i_mixer_mode_set, ++ .commit = sun8i_mixer_commit, ++ .layers_init = sun8i_layers_init, ++ .mode_set = sun8i_mixer_mode_set, ++ .get_supported_fmts = sun8i_mixer_get_supported_fmts, + }; + + static const struct regmap_config sun8i_mixer_regmap_config = { +@@ -456,6 +499,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, + dev_set_drvdata(dev, mixer); + mixer->engine.ops = &sun8i_engine_ops; + mixer->engine.node = dev->of_node; ++ /* default output format, supported by all mixers */ ++ mixer->engine.format = MEDIA_BUS_FMT_RGB888_1X24; ++ /* default color encoding, ignored with RGB I/O */ ++ mixer->engine.encoding = DRM_COLOR_YCBCR_BT601; + + if (of_property_present(dev->of_node, "iommus")) { + /* +diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h +index c48cbc1aceb8..ffafc29b3a0c 100644 +--- a/drivers/gpu/drm/sun4i/sunxi_engine.h ++++ b/drivers/gpu/drm/sun4i/sunxi_engine.h +@@ -6,6 +6,8 @@ + #ifndef _SUNXI_ENGINE_H_ + #define _SUNXI_ENGINE_H_ + ++#include ++ + struct drm_plane; + struct drm_crtc; + struct drm_device; +@@ -151,6 +153,9 @@ struct sunxi_engine { + + int id; + ++ u32 format; ++ enum drm_color_encoding encoding; ++ + /* Engine list management */ + struct list_head list; + }; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch new file mode 100644 index 000000000000..5fb39d4f07d6 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch @@ -0,0 +1,83 @@ +From ff794822d56721795fec59dea66164cc19ba792c Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:43 +1300 +Subject: drm: sun4i: de3: add YUV support to the TCON + +Account for U/V channel subsampling by reducing the dot clock and +resolution with a divider in the DE3 timing controller if a YUV format +is selected. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun4i_tcon.c | 26 +++++++++++++++++++------- + 1 file changed, 19 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c +index 3675c87461e9..af67bf2e6e09 100644 +--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c ++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c +@@ -649,14 +649,26 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, + static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, + const struct drm_display_mode *mode) + { +- unsigned int bp, hsync, vsync, vtotal; ++ unsigned int bp, hsync, vsync, vtotal, div; ++ struct sun4i_crtc *scrtc = tcon->crtc; ++ struct sunxi_engine *engine = scrtc->engine; + u8 clk_delay; + u32 val; + + WARN_ON(!tcon->quirks->has_channel_1); + ++ switch (engine->format) { ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ div = 2; ++ break; ++ default: ++ div = 1; ++ break; ++ } ++ + /* Configure the dot clock */ +- clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); ++ clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000 / div); + + /* Adjust clock delay */ + clk_delay = sun4i_tcon_get_clk_delay(mode, 1); +@@ -675,17 +687,17 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, + + /* Set the input resolution */ + regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, +- SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | ++ SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay / div) | + SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); + + /* Set the upscaling resolution */ + regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, +- SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | ++ SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay / div) | + SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); + + /* Set the output resolution */ + regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, +- SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | ++ SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay / div) | + SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); + + /* Set horizontal display timings */ +@@ -693,8 +705,8 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, + DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", + mode->htotal, bp); + regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, +- SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | +- SUN4I_TCON1_BASIC3_H_BACKPORCH(bp)); ++ SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal / div) | ++ SUN4I_TCON1_BASIC3_H_BACKPORCH(bp / div)); + + bp = mode->crtc_vtotal - mode->crtc_vsync_start; + DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch new file mode 100644 index 000000000000..68774b67bf48 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch @@ -0,0 +1,225 @@ +From a23ed976ee720c2445791716d975f040ef576c2b Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:42 +1300 +Subject: drm: sun4i: de3: add YUV support to the color space correction module + +Add coefficients and support for YUV formats to the display engine +colorspace and dynamic range correction submodule. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 164 +++++++++++++++++++++++++++++- + 1 file changed, 162 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index 8a336ccb27d3..e12a81fa9108 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -5,6 +5,8 @@ + + #include + ++#include ++ + #include "sun8i_csc.h" + #include "sun8i_mixer.h" + +@@ -107,6 +109,135 @@ static const u32 yuv2rgb_de3[2][3][12] = { + }, + }; + ++/* always convert to limited mode */ ++static const u32 rgb2yuv_de3[3][12] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x0000837A, 0x0001021D, 0x00003221, 0x00000040, ++ 0xFFFFB41C, 0xFFFF6B03, 0x0000E0E1, 0x00000200, ++ 0x0000E0E1, 0xFFFF43B1, 0xFFFFDB6E, 0x00000200, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x00005D7C, 0x00013A7C, 0x00001FBF, 0x00000040, ++ 0xFFFFCC78, 0xFFFF52A7, 0x0000E0E1, 0x00000200, ++ 0x0000E0E1, 0xFFFF33BE, 0xFFFFEB61, 0x00000200, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ 0x00007384, 0x00012A21, 0x00001A13, 0x00000040, ++ 0xFFFFC133, 0xFFFF5DEC, 0x0000E0E1, 0x00000200, ++ 0x0000E0E1, 0xFFFF3135, 0xFFFFEDEA, 0x00000200, ++ }, ++}; ++ ++/* always convert to limited mode */ ++static const u32 yuv2yuv_de3[2][3][3][12] = { ++ [DRM_COLOR_YCBCR_LIMITED_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x00020000, 0x00000000, 0x00000000, 0x00000000, ++ 0x00000000, 0x00020000, 0x00000000, 0x00000000, ++ 0x00000000, 0x00000000, 0x00020000, 0x00000000, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x00020000, 0xFFFFC4D7, 0xFFFF9589, 0xFFC00040, ++ 0x00000000, 0x0002098B, 0x00003AAF, 0xFE000200, ++ 0x00000000, 0x0000266D, 0x00020CF8, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ 0x00020000, 0xFFFFBFCE, 0xFFFFC5FF, 0xFFC00040, ++ 0x00000000, 0x00020521, 0x00001F89, 0xFE000200, ++ 0x00000000, 0x00002C87, 0x00020F07, 0xFE000200, ++ }, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x00020000, 0x000032D9, 0x00006226, 0xFFC00040, ++ 0x00000000, 0x0001FACE, 0xFFFFC759, 0xFE000200, ++ 0x00000000, 0xFFFFDAE7, 0x0001F780, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x00020000, 0x00000000, 0x00000000, 0x00000000, ++ 0x00000000, 0x00020000, 0x00000000, 0x00000000, ++ 0x00000000, 0x00000000, 0x00020000, 0x00000000, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ 0x00020000, 0xFFFFF782, 0x00003036, 0xFFC00040, ++ 0x00000000, 0x0001FD99, 0xFFFFE5CA, 0xFE000200, ++ 0x00000000, 0x000005E4, 0x0002015A, 0xFE000200, ++ }, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x00020000, 0x00003B03, 0x000034D2, 0xFFC00040, ++ 0x00000000, 0x0001FD8C, 0xFFFFE183, 0xFE000200, ++ 0x00000000, 0xFFFFD4F3, 0x0001F3FA, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x00020000, 0x00000916, 0xFFFFD061, 0xFFC00040, ++ 0x00000000, 0x0002021C, 0x00001A40, 0xFE000200, ++ 0x00000000, 0xFFFFFA19, 0x0001FE5A, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ 0x00020000, 0x00000000, 0x00000000, 0x00000000, ++ 0x00000000, 0x00020000, 0x00000000, 0x00000000, ++ 0x00000000, 0x00000000, 0x00020000, 0x00000000, ++ }, ++ }, ++ }, ++ [DRM_COLOR_YCBCR_FULL_RANGE] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x0001B7B8, 0x00000000, 0x00000000, 0x00000040, ++ 0x00000000, 0x0001C1C2, 0x00000000, 0xFE000200, ++ 0x00000000, 0x00000000, 0x0001C1C2, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x0001B7B8, 0xFFFFCC08, 0xFFFFA27B, 0x00000040, ++ 0x00000000, 0x0001CA24, 0x0000338D, 0xFE000200, ++ 0x00000000, 0x000021C1, 0x0001CD26, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ 0x0001B7B8, 0xFFFFC79C, 0xFFFFCD0C, 0x00000040, ++ 0x00000000, 0x0001C643, 0x00001BB4, 0xFE000200, ++ 0x00000000, 0x0000271D, 0x0001CEF5, 0xFE000200, ++ }, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x0001B7B8, 0x00002CAB, 0x00005638, 0x00000040, ++ 0x00000000, 0x0001BD32, 0xFFFFCE3C, 0xFE000200, ++ 0x00000000, 0xFFFFDF6A, 0x0001BA4A, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x0001B7B8, 0x00000000, 0x00000000, 0x00000040, ++ 0x00000000, 0x0001C1C2, 0x00000000, 0xFE000200, ++ 0x00000000, 0x00000000, 0x0001C1C2, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ 0x0001B7B8, 0xFFFFF88A, 0x00002A5A, 0x00000040, ++ 0x00000000, 0x0001BFA5, 0xFFFFE8FA, 0xFE000200, ++ 0x00000000, 0x0000052D, 0x0001C2F1, 0xFE000200, ++ }, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ [DRM_COLOR_YCBCR_BT601] = { ++ 0x0001B7B8, 0x000033D6, 0x00002E66, 0x00000040, ++ 0x00000000, 0x0001BF9A, 0xFFFFE538, 0xFE000200, ++ 0x00000000, 0xFFFFDA2F, 0x0001B732, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT709] = { ++ 0x0001B7B8, 0x000007FB, 0xFFFFD62B, 0x00000040, ++ 0x00000000, 0x0001C39D, 0x0000170F, 0xFE000200, ++ 0x00000000, 0xFFFFFAD1, 0x0001C04F, 0xFE000200, ++ }, ++ [DRM_COLOR_YCBCR_BT2020] = { ++ 0x0001B7B8, 0x00000000, 0x00000000, 0x00000040, ++ 0x00000000, 0x0001C1C2, 0x00000000, 0xFE000200, ++ 0x00000000, 0x00000000, 0x0001C1C2, 0xFE000200, ++ }, ++ }, ++ }, ++}; ++ + static void sun8i_csc_setup(struct regmap *map, u32 base, + enum format_type fmt_type, + enum drm_color_encoding encoding, +@@ -148,12 +279,27 @@ static void sun8i_csc_setup(struct regmap *map, u32 base, + regmap_write(map, SUN8I_CSC_CTRL(base), val); + } + ++static const u32 *sun8i_csc_get_de3_yuv_table(enum drm_color_encoding in_enc, ++ enum drm_color_range in_range, ++ u32 out_format, ++ enum drm_color_encoding out_enc) ++{ ++ if (out_format == MEDIA_BUS_FMT_RGB888_1X24) ++ return yuv2rgb_de3[in_range][in_enc]; ++ ++ /* check for identity transformation */ ++ if (in_range == DRM_COLOR_YCBCR_LIMITED_RANGE && out_enc == in_enc) ++ return NULL; ++ ++ return yuv2yuv_de3[in_range][in_enc][out_enc]; ++} ++ + static void sun8i_de3_ccsc_setup(struct sunxi_engine *engine, int layer, + enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range) + { +- u32 addr, val, mask; ++ u32 addr, val = 0, mask; + struct regmap *map; + const u32 *table; + int i; +@@ -164,14 +310,28 @@ static void sun8i_de3_ccsc_setup(struct sunxi_engine *engine, int layer, + + switch (fmt_type) { + case FORMAT_TYPE_RGB: +- val = 0; ++ if (engine->format == MEDIA_BUS_FMT_RGB888_1X24) ++ break; ++ val = mask; ++ addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); ++ regmap_bulk_write(map, addr, rgb2yuv_de3[engine->encoding], 12); + break; + case FORMAT_TYPE_YUV: ++ table = sun8i_csc_get_de3_yuv_table(encoding, range, ++ engine->format, ++ engine->encoding); ++ if (!table) ++ break; + val = mask; + addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); + regmap_bulk_write(map, addr, table, 12); + break; + case FORMAT_TYPE_YVU: ++ table = sun8i_csc_get_de3_yuv_table(encoding, range, ++ engine->format, ++ engine->encoding); ++ if (!table) ++ table = yuv2yuv_de3[range][encoding][encoding]; + val = mask; + for (i = 0; i < 12; i++) { + if ((i & 3) == 1) +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch new file mode 100644 index 000000000000..581242c382e9 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch @@ -0,0 +1,63 @@ +From 99d327853acbc5d6c6d4140f004f82fcd5c40ea1 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:38 +1300 +Subject: drm: sun4i: de3: add format enumeration function to engine + +The DE3 display engine supports YUV formats in addition to RGB. + +Add an optional format enumeration function to the engine. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sunxi_engine.h | 29 ++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h +index ec0c4932f15c..c48cbc1aceb8 100644 +--- a/drivers/gpu/drm/sun4i/sunxi_engine.h ++++ b/drivers/gpu/drm/sun4i/sunxi_engine.h +@@ -123,6 +123,17 @@ struct sunxi_engine_ops { + */ + void (*mode_set)(struct sunxi_engine *engine, + const struct drm_display_mode *mode); ++ ++ /** ++ * @get_supported_fmts ++ * ++ * This callback is used to enumerate all supported output ++ * formats by the engine. They are used for bridge format ++ * negotiation. ++ * ++ * This function is optional. ++ */ ++ u32 *(*get_supported_fmts)(struct sunxi_engine *engine, u32 *num); + }; + + /** +@@ -215,4 +226,22 @@ sunxi_engine_mode_set(struct sunxi_engine *engine, + if (engine->ops && engine->ops->mode_set) + engine->ops->mode_set(engine, mode); + } ++ ++/** ++ * sunxi_engine_get_supported_formats - Provide array of supported formats ++ * @engine: pointer to the engine ++ * @num: pointer to variable, which will hold number of formats ++ * ++ * This list can be used for format negotiation by bridge. ++ */ ++static inline u32 * ++sunxi_engine_get_supported_formats(struct sunxi_engine *engine, u32 *num) ++{ ++ if (engine->ops && engine->ops->get_supported_fmts) ++ return engine->ops->get_supported_fmts(engine, num); ++ ++ *num = 0; ++ ++ return NULL; ++} + #endif /* _SUNXI_ENGINE_H_ */ +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch new file mode 100644 index 000000000000..90f86befd415 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch @@ -0,0 +1,53 @@ +From f9a39553dcf5e87eba968d2aac4f5acf52baa392 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:39 +1300 +Subject: drm: sun4i: de3: add formatter flag to mixer config + +Only the DE3 (and newer) display engines have a formatter module. This +could be inferred from the is_de3 flag alone, however this will not +scale with addition of future DE versions in subsequent patches. + +Add a separate flag to signal this in the mixer configuration. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 1 + + drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c +index bd0fe2c6624e..252827715de1 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c +@@ -717,6 +717,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { + static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { + .ccsc = CCSC_MIXER0_LAYOUT, + .is_de3 = true, ++ .has_formatter = 1, + .mod_rate = 600000000, + .scaler_mask = 0xf, + .scanline_yuv = 4096, +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h +index d7898c9c9cc0..8417b8fef2e1 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h +@@ -163,6 +163,7 @@ enum { + * @mod_rate: module clock rate that needs to be set in order to have + * a functional block. + * @is_de3: true, if this is next gen display engine 3.0, false otherwise. ++ * @has_formatter: true, if mixer has formatter core, for 10-bit and YUV handling + * @scaline_yuv: size of a scanline for VI scaler for YUV formats. + */ + struct sun8i_mixer_cfg { +@@ -172,6 +173,7 @@ struct sun8i_mixer_cfg { + int ccsc; + unsigned long mod_rate; + unsigned int is_de3 : 1; ++ unsigned int has_formatter : 1; + unsigned int scanline_yuv; + }; + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch new file mode 100644 index 000000000000..41bd023772e6 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch @@ -0,0 +1,54 @@ +From 2d7c88fc2af6d07ccadc99b157753638b4940293 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:41 +1300 +Subject: drm: sun4i: de3: pass engine reference to ccsc setup function + +Configuration of the DE3 colorspace and dynamic range correction module +requires knowledge of the current video format and encoding. + +Pass the display engine by reference to the csc setup function, rather +than the register map alone, to allow access to this information. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index 68d955c63b05..8a336ccb27d3 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -148,17 +148,19 @@ static void sun8i_csc_setup(struct regmap *map, u32 base, + regmap_write(map, SUN8I_CSC_CTRL(base), val); + } + +-static void sun8i_de3_ccsc_setup(struct regmap *map, int layer, ++static void sun8i_de3_ccsc_setup(struct sunxi_engine *engine, int layer, + enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range) + { + u32 addr, val, mask; ++ struct regmap *map; + const u32 *table; + int i; + + mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); + table = yuv2rgb_de3[range][encoding]; ++ map = engine->regs; + + switch (fmt_type) { + case FORMAT_TYPE_RGB: +@@ -204,7 +206,7 @@ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, + u32 base; + + if (mixer->cfg->is_de3) { +- sun8i_de3_ccsc_setup(mixer->engine.regs, layer, ++ sun8i_de3_ccsc_setup(&mixer->engine, layer, + fmt_type, encoding, range); + return; + } +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch new file mode 100644 index 000000000000..3479d96ff100 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch @@ -0,0 +1,156 @@ +From 0d003a88bcacf5f405f3922b0c56b7eecdb68386 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:58 +1300 +Subject: drm: sun4i: de33: csc: add Display Engine 3.3 (DE33) support + +Like earlier DE versions, the DE33 has a CSC (Color Space Correction) +module. which provides color space conversion between BT2020/BT709, and +dynamic range conversion between SDR/ST2084/HLG. + +Add support for the DE33. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_csc.c | 96 +++++++++++++++++++++++++++++++ + drivers/gpu/drm/sun4i/sun8i_csc.h | 3 + + 2 files changed, 99 insertions(+) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c +index 2d5a2cf7cba2..45bd1ca06400 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.c ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c +@@ -238,6 +238,14 @@ static const u32 yuv2yuv_de3[2][3][3][12] = { + }, + }; + ++static u32 sun8i_csc_base(struct sun8i_mixer *mixer, int layer) ++{ ++ if (mixer->cfg->de_type == sun8i_mixer_de33) ++ return sun8i_channel_base(mixer, layer) - 0x800; ++ else ++ return ccsc_base[mixer->cfg->ccsc][layer]; ++} ++ + static void sun8i_csc_setup(struct regmap *map, u32 base, + enum format_type fmt_type, + enum drm_color_encoding encoding, +@@ -358,6 +366,90 @@ static void sun8i_de3_ccsc_setup(struct sunxi_engine *engine, int layer, + mask, val); + } + ++/* extract constant from high word and invert sign if necessary */ ++static u32 sun8i_de33_ccsc_get_constant(u32 value) ++{ ++ value >>= 16; ++ ++ if (value & BIT(15)) ++ return 0x400 - (value & 0x3ff); ++ ++ return value; ++} ++ ++static void sun8i_de33_convert_table(const u32 *src, u32 *dst) ++{ ++ dst[0] = sun8i_de33_ccsc_get_constant(src[3]); ++ dst[1] = sun8i_de33_ccsc_get_constant(src[7]); ++ dst[2] = sun8i_de33_ccsc_get_constant(src[11]); ++ memcpy(&dst[3], src, sizeof(u32) * 12); ++ dst[6] &= 0xffff; ++ dst[10] &= 0xffff; ++ dst[14] &= 0xffff; ++} ++ ++static void sun8i_de33_ccsc_setup(struct sun8i_mixer *mixer, int layer, ++ enum format_type fmt_type, ++ enum drm_color_encoding encoding, ++ enum drm_color_range range) ++{ ++ u32 addr, val = 0, base, csc[15]; ++ struct sunxi_engine *engine; ++ struct regmap *map; ++ const u32 *table; ++ int i; ++ ++ table = yuv2rgb_de3[range][encoding]; ++ base = sun8i_csc_base(mixer, layer); ++ engine = &mixer->engine; ++ map = engine->regs; ++ ++ switch (fmt_type) { ++ case FORMAT_TYPE_RGB: ++ if (engine->format == MEDIA_BUS_FMT_RGB888_1X24) ++ break; ++ val = SUN8I_CSC_CTRL_EN; ++ sun8i_de33_convert_table(rgb2yuv_de3[engine->encoding], csc); ++ regmap_bulk_write(map, SUN50I_CSC_COEFF(base, 0), csc, 15); ++ break; ++ case FORMAT_TYPE_YUV: ++ table = sun8i_csc_get_de3_yuv_table(encoding, range, ++ engine->format, ++ engine->encoding); ++ if (!table) ++ break; ++ val = SUN8I_CSC_CTRL_EN; ++ sun8i_de33_convert_table(table, csc); ++ regmap_bulk_write(map, SUN50I_CSC_COEFF(base, 0), csc, 15); ++ break; ++ case FORMAT_TYPE_YVU: ++ table = sun8i_csc_get_de3_yuv_table(encoding, range, ++ engine->format, ++ engine->encoding); ++ if (!table) ++ table = yuv2yuv_de3[range][encoding][encoding]; ++ val = SUN8I_CSC_CTRL_EN; ++ sun8i_de33_convert_table(table, csc); ++ for (i = 0; i < 15; i++) { ++ addr = SUN50I_CSC_COEFF(base, i); ++ if (i > 3) { ++ if (((i - 3) & 3) == 1) ++ addr = SUN50I_CSC_COEFF(base, i + 1); ++ else if (((i - 3) & 3) == 2) ++ addr = SUN50I_CSC_COEFF(base, i - 1); ++ } ++ regmap_write(map, addr, csc[i]); ++ } ++ break; ++ default: ++ val = 0; ++ DRM_WARN("Wrong CSC mode specified.\n"); ++ return; ++ } ++ ++ regmap_write(map, SUN8I_CSC_CTRL(base), val); ++} ++ + void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, + enum format_type fmt_type, + enum drm_color_encoding encoding, +@@ -369,6 +461,10 @@ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, + sun8i_de3_ccsc_setup(&mixer->engine, layer, + fmt_type, encoding, range); + return; ++ } else if (mixer->cfg->de_type == sun8i_mixer_de33) { ++ sun8i_de33_ccsc_setup(mixer, layer, fmt_type, ++ encoding, range); ++ return; + } + + if (layer < mixer->cfg->vi_num) { +diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h +index b7546e06e315..2b762cb79f02 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_csc.h ++++ b/drivers/gpu/drm/sun4i/sun8i_csc.h +@@ -20,6 +20,9 @@ struct sun8i_mixer; + #define SUN8I_CSC_CTRL(base) ((base) + 0x0) + #define SUN8I_CSC_COEFF(base, i) ((base) + 0x10 + 4 * (i)) + ++#define SUN50I_CSC_COEFF(base, i) ((base) + 0x04 + 4 * (i)) ++#define SUN50I_CSC_ALPHA(base) ((base) + 0x40) ++ + #define SUN8I_CSC_CTRL_EN BIT(0) + + enum format_type { +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch new file mode 100644 index 000000000000..cd060b36718e --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch @@ -0,0 +1,75 @@ +From 792b816c952bcf5dbf7c3ac7d90937bc71f0a7cd Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:57 +1300 +Subject: drm: sun4i: de33: fmt: add Display Engine 3.3 (DE33) support + +Like the DE3, the DE33 has a FMT (formatter) module, which +provides YUV444 to YUV422/YUV420 conversion, format re-mapping and color +depth conversion, although the DE33 module appears significantly more +capable, including up to 4K video support. + +Add support for the DE33. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun50i_fmt.c | 21 +++++++++++++++++++-- + drivers/gpu/drm/sun4i/sun50i_fmt.h | 1 + + 2 files changed, 20 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun50i_fmt.c b/drivers/gpu/drm/sun4i/sun50i_fmt.c +index 050a8716ae86..39682d4e6d20 100644 +--- a/drivers/gpu/drm/sun4i/sun50i_fmt.c ++++ b/drivers/gpu/drm/sun4i/sun50i_fmt.c +@@ -51,6 +51,19 @@ static void sun50i_fmt_de3_limits(u32 *limits, u32 colorspace, bool bit10) + } + } + ++static void sun50i_fmt_de33_limits(u32 *limits, u32 colorspace) ++{ ++ if (colorspace == SUN50I_FMT_CS_YUV444RGB) { ++ limits[0] = SUN50I_FMT_LIMIT(0, 4095); ++ limits[1] = SUN50I_FMT_LIMIT(0, 4095); ++ limits[2] = SUN50I_FMT_LIMIT(0, 4095); ++ } else { ++ limits[0] = SUN50I_FMT_LIMIT(256, 3840); ++ limits[1] = SUN50I_FMT_LIMIT(256, 3840); ++ limits[2] = SUN50I_FMT_LIMIT(256, 3840); ++ } ++} ++ + void sun50i_fmt_setup(struct sun8i_mixer *mixer, u16 width, + u16 height, u32 format) + { +@@ -60,10 +73,14 @@ void sun50i_fmt_setup(struct sun8i_mixer *mixer, u16 width, + + colorspace = sun50i_fmt_get_colorspace(format); + bit10 = sun50i_fmt_is_10bit(format); +- base = SUN50I_FMT_DE3; ++ base = mixer->cfg->de_type == sun8i_mixer_de3 ? ++ SUN50I_FMT_DE3 : SUN50I_FMT_DE33; + regs = sun8i_blender_regmap(mixer); + +- sun50i_fmt_de3_limits(limit, colorspace, bit10); ++ if (mixer->cfg->de_type == sun8i_mixer_de3) ++ sun50i_fmt_de3_limits(limit, colorspace, bit10); ++ else ++ sun50i_fmt_de33_limits(limit, colorspace); + + regmap_write(regs, SUN50I_FMT_CTRL(base), 0); + +diff --git a/drivers/gpu/drm/sun4i/sun50i_fmt.h b/drivers/gpu/drm/sun4i/sun50i_fmt.h +index 4127f7206aad..3e60d5c788b3 100644 +--- a/drivers/gpu/drm/sun4i/sun50i_fmt.h ++++ b/drivers/gpu/drm/sun4i/sun50i_fmt.h +@@ -9,6 +9,7 @@ + #include "sun8i_mixer.h" + + #define SUN50I_FMT_DE3 0xa8000 ++#define SUN50I_FMT_DE33 0x5000 + + #define SUN50I_FMT_CTRL(base) ((base) + 0x00) + #define SUN50I_FMT_SIZE(base) ((base) + 0x04) +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch new file mode 100644 index 000000000000..84e9458fb3fd --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch @@ -0,0 +1,302 @@ +From 66c111f3315d2c34c2f9bfb39de61bf3ec46a5f6 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:55 +1300 +Subject: drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support + +The DE33 is a newer version of the Allwinner Display Engine IP block, +found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already +supported by the mainline driver. + +Notable features (from the H616 datasheet and implemented): +- 4096 x 2048 (4K) output support +- AFBC ARM Frame Buffer Compression support +- YUV420 input support + +The DE2 and DE3 engines have a blender register range within the +mixer engine register map, whereas the DE33 separates this out into +a separate display group, and adds a top register map. + +Extend the mixer to support the DE33. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 109 ++++++++++++++++++++++++---- + drivers/gpu/drm/sun4i/sun8i_mixer.h | 16 +++- + 2 files changed, 108 insertions(+), 17 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c +index 600084286b39..204fc8055b32 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c +@@ -321,8 +321,12 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, + regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), + pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); + +- regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, +- SUN8I_MIXER_GLOBAL_DBUFF_ENABLE); ++ if (mixer->cfg->de_type == sun8i_mixer_de33) ++ regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_DBUFF, ++ SUN8I_MIXER_GLOBAL_DBUFF_ENABLE); ++ else ++ regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, ++ SUN8I_MIXER_GLOBAL_DBUFF_ENABLE); + } + + static struct drm_plane **sun8i_layers_init(struct drm_device *drm, +@@ -371,25 +375,33 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, + const struct drm_display_mode *mode) + { + struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); ++ struct regmap *bld_regs, *disp_regs; + u32 bld_base, size, val; + bool interlaced; + + bld_base = sun8i_blender_base(mixer); ++ bld_regs = sun8i_blender_regmap(mixer); + interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); + size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay); + + DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n", + mode->hdisplay, mode->vdisplay); + +- regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size); +- regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); ++ if (mixer->cfg->de_type == sun8i_mixer_de33) { ++ disp_regs = mixer->disp_regs; ++ regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_SIZE, size); ++ } else { ++ disp_regs = mixer->engine.regs; ++ regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size); ++ } ++ regmap_write(bld_regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); + + if (interlaced) + val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; + else + val = 0; + +- regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), ++ regmap_update_bits(bld_regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), + SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); + + DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", +@@ -400,10 +412,8 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, + else + val = 0xff108080; + +- regmap_write(mixer->engine.regs, +- SUN8I_MIXER_BLEND_BKCOLOR(bld_base), val); +- regmap_write(mixer->engine.regs, +- SUN8I_MIXER_BLEND_ATTR_FCOLOR(bld_base, 0), val); ++ regmap_write(disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(bld_base), val); ++ regmap_write(disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(bld_base, 0), val); + + if (mixer->cfg->has_formatter) + sun50i_fmt_setup(mixer, mode->hdisplay, +@@ -443,12 +453,29 @@ static const struct sunxi_engine_ops sun8i_engine_ops = { + }; + + static const struct regmap_config sun8i_mixer_regmap_config = { ++ .name = "layers", + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0xffffc, /* guessed */ + }; + ++static const struct regmap_config sun8i_top_regmap_config = { ++ .name = "top", ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = 0x3c, ++}; ++ ++static const struct regmap_config sun8i_disp_regmap_config = { ++ .name = "display", ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = 0x20000, ++}; ++ + static int sun8i_mixer_of_get_id(struct device_node *node) + { + struct device_node *ep, *remote; +@@ -471,33 +498,45 @@ static int sun8i_mixer_of_get_id(struct device_node *node) + + static void sun8i_mixer_init(struct sun8i_mixer *mixer) + { ++ struct regmap *top_regs, *disp_regs; + unsigned int base = sun8i_blender_base(mixer); + int plane_cnt, i; + ++ if (mixer->cfg->de_type == sun8i_mixer_de33) { ++ top_regs = mixer->top_regs; ++ disp_regs = mixer->disp_regs; ++ } else { ++ top_regs = mixer->engine.regs; ++ disp_regs = mixer->engine.regs; ++ } ++ + /* Enable the mixer */ +- regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, ++ regmap_write(top_regs, SUN8I_MIXER_GLOBAL_CTL, + SUN8I_MIXER_GLOBAL_CTL_RT_EN); + ++ if (mixer->cfg->de_type == sun8i_mixer_de33) ++ regmap_write(top_regs, SUN50I_MIXER_GLOBAL_CLK, 1); ++ + /* Set background color to black */ +- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), ++ regmap_write(disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(base), + SUN8I_MIXER_BLEND_COLOR_BLACK); + + /* + * Set fill color of bottom plane to black. Generally not needed + * except when VI plane is at bottom (zpos = 0) and enabled. + */ +- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), ++ regmap_write(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); +- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), ++ regmap_write(disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), + SUN8I_MIXER_BLEND_COLOR_BLACK); + + plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num; + for (i = 0; i < plane_cnt; i++) +- regmap_write(mixer->engine.regs, ++ regmap_write(disp_regs, + SUN8I_MIXER_BLEND_MODE(base, i), + SUN8I_MIXER_BLEND_MODE_DEF); + +- regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), ++ regmap_update_bits(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); + } + +@@ -573,6 +612,30 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, + return PTR_ERR(mixer->engine.regs); + } + ++ if (mixer->cfg->de_type == sun8i_mixer_de33) { ++ regs = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(regs)) ++ return PTR_ERR(regs); ++ ++ mixer->top_regs = devm_regmap_init_mmio(dev, regs, ++ &sun8i_top_regmap_config); ++ if (IS_ERR(mixer->top_regs)) { ++ dev_err(dev, "Couldn't create the top regmap\n"); ++ return PTR_ERR(mixer->top_regs); ++ } ++ ++ regs = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(regs)) ++ return PTR_ERR(regs); ++ ++ mixer->disp_regs = devm_regmap_init_mmio(dev, regs, ++ &sun8i_disp_regmap_config); ++ if (IS_ERR(mixer->disp_regs)) { ++ dev_err(dev, "Couldn't create the disp regmap\n"); ++ return PTR_ERR(mixer->disp_regs); ++ } ++ } ++ + mixer->reset = devm_reset_control_get(dev, NULL); + if (IS_ERR(mixer->reset)) { + dev_err(dev, "Couldn't get our reset line\n"); +@@ -787,6 +850,18 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { + .vi_num = 1, + }; + ++static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg = { ++ .ccsc = CCSC_MIXER0_LAYOUT, ++ .de_type = sun8i_mixer_de33, ++ .has_formatter = 1, ++ .mod_rate = 600000000, ++ .scaler_mask = 0xf, ++ .scanline_yuv = 4096, ++ .ui_num = 3, ++ .vi_num = 1, ++ .map = {0, 6, 7, 8}, ++}; ++ + static const struct of_device_id sun8i_mixer_of_table[] = { + { + .compatible = "allwinner,sun8i-a83t-de2-mixer-0", +@@ -832,6 +907,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = { + .compatible = "allwinner,sun50i-h6-de3-mixer-0", + .data = &sun50i_h6_mixer0_cfg, + }, ++ { ++ .compatible = "allwinner,sun50i-h616-de33-mixer-0", ++ .data = &sun50i_h616_mixer0_cfg, ++ }, + { } + }; + MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table); +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h +index 75facc7d1fa6..26b001164647 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h +@@ -21,6 +21,10 @@ + #define SUN8I_MIXER_GLOBAL_DBUFF 0x8 + #define SUN8I_MIXER_GLOBAL_SIZE 0xc + ++#define SUN50I_MIXER_GLOBAL_SIZE 0x8 ++#define SUN50I_MIXER_GLOBAL_CLK 0xc ++#define SUN50I_MIXER_GLOBAL_DBUFF 0x10 ++ + #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0) + + #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0) +@@ -154,6 +158,7 @@ enum { + enum sun8i_mixer_type { + sun8i_mixer_de2, + sun8i_mixer_de3, ++ sun8i_mixer_de33, + }; + + /** +@@ -180,6 +185,7 @@ struct sun8i_mixer_cfg { + unsigned int de_type; + unsigned int has_formatter : 1; + unsigned int scanline_yuv; ++ unsigned int map[6]; + }; + + struct sun8i_mixer { +@@ -191,6 +197,9 @@ struct sun8i_mixer { + + struct clk *bus_clk; + struct clk *mod_clk; ++ ++ struct regmap *top_regs; ++ struct regmap *disp_regs; + }; + + enum { +@@ -227,13 +236,16 @@ sun8i_blender_base(struct sun8i_mixer *mixer) + static inline struct regmap * + sun8i_blender_regmap(struct sun8i_mixer *mixer) + { +- return mixer->engine.regs; ++ return mixer->cfg->de_type == sun8i_mixer_de33 ? ++ mixer->disp_regs : mixer->engine.regs; + } + + static inline u32 + sun8i_channel_base(struct sun8i_mixer *mixer, int channel) + { +- if (mixer->cfg->de_type == sun8i_mixer_de3) ++ if (mixer->cfg->de_type == sun8i_mixer_de33) ++ return mixer->cfg->map[channel] * 0x20000 + DE2_CH_SIZE; ++ else if (mixer->cfg->de_type == sun8i_mixer_de3) + return DE3_CH_BASE + channel * DE3_CH_SIZE; + else + return DE2_CH_BASE + channel * DE2_CH_SIZE; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch new file mode 100644 index 000000000000..9028d40a3256 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch @@ -0,0 +1,77 @@ +From 412294545ec91452cc3eccff746a4243879b4cde Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:56 +1300 +Subject: drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support + +The vi_scaler appears to be used in preference to the ui_scaler module +for hardware video scaling in the DE33. + +Enable support for this scaler. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 19 +++++++++++++++---- + drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 7 ++++++- + 2 files changed, 21 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +index 7f1231cf0f01..180be9d67d9c 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +@@ -95,12 +95,23 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, + hscale = state->src_w / state->crtc_w; + vscale = state->src_h / state->crtc_h; + +- sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w, +- dst_h, hscale, vscale, hphase, vphase); +- sun8i_ui_scaler_enable(mixer, channel, true); ++ if (mixer->cfg->de_type == sun8i_mixer_de33) { ++ sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, ++ dst_w, dst_h, hscale, vscale, ++ hphase, vphase, ++ state->fb->format); ++ } else { ++ sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, ++ dst_w, dst_h, hscale, vscale, ++ hphase, vphase); ++ sun8i_ui_scaler_enable(mixer, channel, true); ++ } + } else { + DRM_DEBUG_DRIVER("HW scaling is not needed\n"); +- sun8i_ui_scaler_enable(mixer, channel, false); ++ if (mixer->cfg->de_type == sun8i_mixer_de33) ++ sun8i_vi_scaler_disable(mixer, channel); ++ else ++ sun8i_ui_scaler_enable(mixer, channel, false); + } + + /* Set base coordinates */ +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +index e7242301b312..9c7f6e7d71d5 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +@@ -835,7 +835,9 @@ static const u32 bicubic4coefftab32[480] = { + + static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel) + { +- if (mixer->cfg->de_type == sun8i_mixer_de3) ++ if (mixer->cfg->de_type == sun8i_mixer_de33) ++ return sun8i_channel_base(mixer, channel) + 0x3000; ++ else if (mixer->cfg->de_type == sun8i_mixer_de3) + return DE3_VI_SCALER_UNIT_BASE + + DE3_VI_SCALER_UNIT_SIZE * channel; + else +@@ -845,6 +847,9 @@ static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel) + + static bool sun8i_vi_scaler_is_vi_plane(struct sun8i_mixer *mixer, int channel) + { ++ if (mixer->cfg->de_type == sun8i_mixer_de33) ++ return mixer->cfg->map[channel] < mixer->cfg->vi_num; ++ + return true; + } + +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch new file mode 100644 index 000000000000..1aff0b4bcde5 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch @@ -0,0 +1,140 @@ +From e0de25f60a3535d345b33dcc541c814499151788 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:44 +1300 +Subject: drm: sun4i: support YUV formats in VI scaler + +Now that YUV formats are available, enable support in the VI scaler. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin + +Changelog v4..v5: +- Add commit description +--- + drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 85 +++++++++++++++++-------- + 1 file changed, 58 insertions(+), 27 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +index 7ba75011adf9..2e49a6e5f1f1 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +@@ -843,6 +843,11 @@ static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel) + DE2_VI_SCALER_UNIT_SIZE * channel; + } + ++static bool sun8i_vi_scaler_is_vi_plane(struct sun8i_mixer *mixer, int channel) ++{ ++ return true; ++} ++ + static int sun8i_vi_scaler_coef_index(unsigned int step) + { + unsigned int scale, int_part, float_part; +@@ -867,44 +872,65 @@ static int sun8i_vi_scaler_coef_index(unsigned int step) + } + } + +-static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base, +- u32 hstep, u32 vstep, +- const struct drm_format_info *format) ++static void sun8i_vi_scaler_set_coeff_vi(struct regmap *map, u32 base, ++ u32 hstep, u32 vstep, ++ const struct drm_format_info *format) + { + const u32 *ch_left, *ch_right, *cy; +- int offset, i; ++ int offset; + +- if (format->hsub == 1 && format->vsub == 1) { +- ch_left = lan3coefftab32_left; +- ch_right = lan3coefftab32_right; +- cy = lan2coefftab32; +- } else { ++ if (format->is_yuv) { + ch_left = bicubic8coefftab32_left; + ch_right = bicubic8coefftab32_right; + cy = bicubic4coefftab32; ++ } else { ++ ch_left = lan3coefftab32_left; ++ ch_right = lan3coefftab32_right; ++ cy = lan2coefftab32; + } + + offset = sun8i_vi_scaler_coef_index(hstep) * + SUN8I_VI_SCALER_COEFF_COUNT; +- for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) { +- regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i), +- lan3coefftab32_left[offset + i]); +- regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i), +- lan3coefftab32_right[offset + i]); +- regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i), +- ch_left[offset + i]); +- regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i), +- ch_right[offset + i]); +- } ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, 0), ++ &lan3coefftab32_left[offset], ++ SUN8I_VI_SCALER_COEFF_COUNT); ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, 0), ++ &lan3coefftab32_right[offset], ++ SUN8I_VI_SCALER_COEFF_COUNT); ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, 0), ++ &ch_left[offset], SUN8I_VI_SCALER_COEFF_COUNT); ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, 0), ++ &ch_right[offset], SUN8I_VI_SCALER_COEFF_COUNT); + + offset = sun8i_vi_scaler_coef_index(hstep) * + SUN8I_VI_SCALER_COEFF_COUNT; +- for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) { +- regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i), +- lan2coefftab32[offset + i]); +- regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i), +- cy[offset + i]); +- } ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, 0), ++ &lan2coefftab32[offset], SUN8I_VI_SCALER_COEFF_COUNT); ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, 0), ++ &cy[offset], SUN8I_VI_SCALER_COEFF_COUNT); ++} ++ ++static void sun8i_vi_scaler_set_coeff_ui(struct regmap *map, u32 base, ++ u32 hstep, u32 vstep, ++ const struct drm_format_info *format) ++{ ++ const u32 *table; ++ int offset; ++ ++ offset = sun8i_vi_scaler_coef_index(hstep) * ++ SUN8I_VI_SCALER_COEFF_COUNT; ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, 0), ++ &lan2coefftab32[offset], SUN8I_VI_SCALER_COEFF_COUNT); ++ offset = sun8i_vi_scaler_coef_index(vstep) * ++ SUN8I_VI_SCALER_COEFF_COUNT; ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, 0), ++ &lan2coefftab32[offset], SUN8I_VI_SCALER_COEFF_COUNT); ++ ++ table = format->is_yuv ? bicubic4coefftab32 : lan2coefftab32; ++ offset = sun8i_vi_scaler_coef_index(hstep) * ++ SUN8I_VI_SCALER_COEFF_COUNT; ++ regmap_bulk_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, 0), ++ &table[offset], SUN8I_VI_SCALER_COEFF_COUNT); + } + + void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) +@@ -994,6 +1020,11 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, + SUN8I_SCALER_VSU_CHPHASE(base), chphase); + regmap_write(mixer->engine.regs, + SUN8I_SCALER_VSU_CVPHASE(base), cvphase); +- sun8i_vi_scaler_set_coeff(mixer->engine.regs, base, +- hscale, vscale, format); ++ ++ if (sun8i_vi_scaler_is_vi_plane(mixer, layer)) ++ sun8i_vi_scaler_set_coeff_vi(mixer->engine.regs, base, ++ hscale, vscale, format); ++ else ++ sun8i_vi_scaler_set_coeff_ui(mixer->engine.regs, base, ++ hscale, vscale, format); + } +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch new file mode 100644 index 000000000000..59a56dd02497 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch @@ -0,0 +1,100 @@ +From 0c10a80b8e37d9a7fc57d8bf968c70419423065a Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 29 Sep 2024 22:04:47 +1300 +Subject: drm: sun4i: vi_scaler refactor vi_scaler enablement + +If the video scaler is required, then it is obligatory to set the +relevant register to enable it, so move this to the +sun8i_vi_scaler_setup() function. + +This simplifies the alternate case (scaler not required) so replace the +vi_scaler_enable() function with a vi_scaler_disable() function. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Ryan Walklin +--- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 3 +-- + drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 21 +++++++++++---------- + drivers/gpu/drm/sun4i/sun8i_vi_scaler.h | 2 +- + 3 files changed, 13 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index 4647e9bcccaa..e348fd0a3d81 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -156,10 +156,9 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w, + dst_h, hscale, vscale, hphase, vphase, + format); +- sun8i_vi_scaler_enable(mixer, channel, true); + } else { + DRM_DEBUG_DRIVER("HW scaling is not needed\n"); +- sun8i_vi_scaler_enable(mixer, channel, false); ++ sun8i_vi_scaler_disable(mixer, channel); + } + + regmap_write(mixer->engine.regs, +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +index aa346c3beb30..e7242301b312 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +@@ -933,20 +933,13 @@ static void sun8i_vi_scaler_set_coeff_ui(struct regmap *map, u32 base, + &table[offset], SUN8I_VI_SCALER_COEFF_COUNT); + } + +-void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) ++void sun8i_vi_scaler_disable(struct sun8i_mixer *mixer, int layer) + { +- u32 val, base; ++ u32 base; + + base = sun8i_vi_scaler_base(mixer, layer); + +- if (enable) +- val = SUN8I_SCALER_VSU_CTRL_EN | +- SUN8I_SCALER_VSU_CTRL_COEFF_RDY; +- else +- val = 0; +- +- regmap_write(mixer->engine.regs, +- SUN8I_SCALER_VSU_CTRL(base), val); ++ regmap_write(mixer->engine.regs, SUN8I_SCALER_VSU_CTRL(base), 0); + } + + void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, +@@ -982,6 +975,9 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, + cvphase = vphase; + } + ++ regmap_write(mixer->engine.regs, SUN8I_SCALER_VSU_CTRL(base), ++ SUN8I_SCALER_VSU_CTRL_EN); ++ + if (mixer->cfg->de_type >= sun8i_mixer_de3) { + u32 val; + +@@ -1027,4 +1023,9 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, + else + sun8i_vi_scaler_set_coeff_ui(mixer->engine.regs, base, + hscale, vscale, format); ++ ++ if (mixer->cfg->de_type <= sun8i_mixer_de3) ++ regmap_write(mixer->engine.regs, SUN8I_SCALER_VSU_CTRL(base), ++ SUN8I_SCALER_VSU_CTRL_EN | ++ SUN8I_SCALER_VSU_CTRL_COEFF_RDY); + } +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h +index 68f6593b369a..e801bc7a4189 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h +@@ -69,7 +69,7 @@ + #define SUN50I_SCALER_VSU_ANGLE_SHIFT(x) (((x) << 16) & 0xF) + #define SUN50I_SCALER_VSU_ANGLE_OFFSET(x) ((x) & 0xFF) + +-void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable); ++void sun8i_vi_scaler_disable(struct sun8i_mixer *mixer, int layer); + void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, + u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, + u32 hscale, u32 vscale, u32 hphase, u32 vphase, +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch new file mode 100644 index 000000000000..86b0c0cb30ca --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch @@ -0,0 +1,35 @@ +From b8344d8eb9d000bc2984a5fcafc25b527f361b5b Mon Sep 17 00:00:00 2001 +From: Ryan Walklin +Date: Sun, 29 Sep 2024 22:04:51 +1300 +Subject: dt-bindings: allwinner: add H616 DE33 bus binding + +The Allwinner H616 and variants have a new display engine revision +(DE33). + +Add a display engine bus binding for the DE33. + +Signed-off-by: Ryan Walklin +Acked-by: Conor Dooley +Reviewed-by: Chen-Yu Tsai +--- + .../devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml +index 9845a187bdf6..ea7ee89158c6 100644 +--- a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml ++++ b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml +@@ -24,7 +24,9 @@ properties: + oneOf: + - const: allwinner,sun50i-a64-de2 + - items: +- - const: allwinner,sun50i-h6-de3 ++ - enum: ++ - allwinner,sun50i-h6-de3 ++ - allwinner,sun50i-h616-de33 + - const: allwinner,sun50i-a64-de2 + + reg: +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch new file mode 100644 index 000000000000..65411eb517a8 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch @@ -0,0 +1,32 @@ +From 58a606c8136c57d23b4e35f0f50cb140f1d65d9b Mon Sep 17 00:00:00 2001 +From: Ryan Walklin +Date: Sun, 29 Sep 2024 22:04:52 +1300 +Subject: dt-bindings: allwinner: add H616 DE33 clock binding + +The Allwinner H616 and variants have a new display engine revision +(DE33). + +Add a clock binding for the DE33. + +Signed-off-by: Ryan Walklin +Acked-by: Conor Dooley +Reviewed-by: Chen-Yu Tsai +--- + .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +index 70369bd633e4..7fcd55d468d4 100644 +--- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml ++++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +@@ -25,6 +25,7 @@ properties: + - const: allwinner,sun50i-a64-de2-clk + - const: allwinner,sun50i-h5-de2-clk + - const: allwinner,sun50i-h6-de3-clk ++ - const: allwinner,sun50i-h616-de33-clk + - items: + - const: allwinner,sun8i-r40-de2-clk + - const: allwinner,sun8i-h3-de2-clk +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch b/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch new file mode 100644 index 000000000000..d3a92736cc03 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch @@ -0,0 +1,36 @@ +From 12d7983166ed867dd72c023af036b1397aec66ba Mon Sep 17 00:00:00 2001 +From: Ryan Walklin +Date: Sun, 29 Sep 2024 22:04:53 +1300 +Subject: dt-bindings: allwinner: add H616 DE33 mixer binding + +The Allwinner H616 and variants have a new display engine revision +(DE33). + +The mixer configuration registers are significantly different to the DE3 +and DE2 revisions, being split into separate top and display blocks, +therefore a fallback for the mixer compatible is not provided. + +Add a display engine mixer binding for the DE33. + +Signed-off-by: Ryan Walklin +Acked-by: Conor Dooley +Reviewed-by: Chen-Yu Tsai +--- + .../bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +index b75c1ec686ad..c37eb8ae1b8e 100644 +--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml ++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +@@ -24,6 +24,7 @@ properties: + - allwinner,sun50i-a64-de2-mixer-0 + - allwinner,sun50i-a64-de2-mixer-1 + - allwinner,sun50i-h6-de3-mixer-0 ++ - allwinner,sun50i-h616-de33-mixer-0 + + reg: + maxItems: 1 +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.12/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch b/patch/kernel/archive/sunxi-6.12/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch index 1924af607db0..059b64cbc307 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.megous/ASoC-codec-es8316-DAC-Soft-Ramp-Rate-is-just-a-2-bit-control.patch @@ -1,4 +1,4 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 62e3909bb6e8e32f6260b0877f54dacfafa3c9f1 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 29 Jul 2022 01:08:29 +0200 Subject: ASoC: codec: es8316: "DAC Soft Ramp Rate" is just a 2 bit control @@ -12,10 +12,10 @@ Signed-off-by: Ondrej Jirman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c -index 111111111111..222222222222 100644 +index f508df01145b..e7bd561a8f40 100644 --- a/sound/soc/codecs/es8316.c +++ b/sound/soc/codecs/es8316.c -@@ -99,7 +99,7 @@ static const struct snd_kcontrol_new es8316_snd_controls[] = { +@@ -101,7 +101,7 @@ static const struct snd_kcontrol_new es8316_snd_controls[] = { SOC_DOUBLE_R_TLV("DAC Playback Volume", ES8316_DAC_VOLL, ES8316_DAC_VOLR, 0, 0xc0, 1, dac_vol_tlv), SOC_SINGLE("DAC Soft Ramp Switch", ES8316_DAC_SET1, 4, 1, 1), @@ -25,5 +25,5 @@ index 111111111111..222222222222 100644 SOC_SINGLE("DAC Double Fs Switch", ES8316_DAC_SET2, 7, 1, 0), SOC_SINGLE("DAC Stereo Enhancement", ES8316_DAC_SET3, 0, 7, 0), -- -Armbian +2.35.3 diff --git a/patch/kernel/archive/sunxi-6.12/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch b/patch/kernel/archive/sunxi-6.12/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch index 3f3eb38e7c60..8720048a64f6 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch @@ -25,23 +25,24 @@ index 111111111111..222222222222 100644 static int sun50i_a64_ccu_probe(struct platform_device *pdev) { void __iomem *reg; -@@ -981,9 +983,15 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) +@@ -980,7 +982,16 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) + /* Decrease the PLL AUDIO bias current to reduce noise. */ writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG); - ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val); -- if (ret) +- writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); ++ ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val); + if (ret) { - writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); - ++ writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); ++ + /* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */ + val = readl(reg + CCU_MIPI_DSI_CLK); + val &= 0x30f; + val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */ + writel(val, reg + CCU_MIPI_DSI_CLK); + } - /* Set PLL MIPI as parent for TCON0 */ - val = readl(reg + SUN50I_A64_TCON0_CLK_REG); - val &= ~GENMASK(26, 24); + + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc); + if (ret) -- Armbian diff --git a/patch/kernel/archive/sunxi-6.12/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch b/patch/kernel/archive/sunxi-6.12/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch index dd3e1066801b..a1c1730a5237 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch @@ -1,4 +1,4 @@ -From 84f9ed3a19d718bf4f35e45d4b553f2fe51ca7c7 Mon Sep 17 00:00:00 2001 +From c4b98967269c353f88e5544988bad6468febd286 Mon Sep 17 00:00:00 2001 From: Thomas Thorne Date: Tue, 20 Sep 2022 20:34:57 -0400 Subject: usb: serial: option: add 'reset_resume' callback for WWAN devices @@ -17,10 +17,10 @@ However the rest of the patch is not needed/already upstreamed. 1 file changed, 1 insertion(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c -index 64317b390d22..3056d0f99ff8 100644 +index 1e2ae0c6c41c..8ab87dfae501 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c -@@ -2444,6 +2444,7 @@ static struct usb_serial_driver option_1port_device = { +@@ -2446,6 +2446,7 @@ static struct usb_serial_driver option_1port_device = { #ifdef CONFIG_PM .suspend = usb_wwan_suspend, .resume = usb_wwan_resume, diff --git a/patch/kernel/archive/sunxi-6.12/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch b/patch/kernel/archive/sunxi-6.12/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch index c10141ce51ab..65d6df07fa94 100644 --- a/patch/kernel/archive/sunxi-6.12/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch +++ b/patch/kernel/archive/sunxi-6.12/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch @@ -90,15 +90,29 @@ index 111111111111..222222222222 100644 static int pwm_backlight_probe(struct platform_device *pdev) { struct platform_pwm_backlight_data *data = dev_get_platdata(&pdev->dev); -@@ -445,6 +500,7 @@ static int pwm_backlight_probe(struct platform_device *pdev) +@@ -444,7 +499,8 @@ static int pwm_backlight_probe(struct platform_device *pdev) + struct backlight_properties props; struct backlight_device *bl; struct pwm_bl_data *pb; - struct pwm_state state, state_real; +- struct pwm_state state; ++ struct pwm_state state, state_real; + u32 lth_brightness; unsigned int i; int ret; -@@ -584,8 +640,20 @@ static int pwm_backlight_probe(struct platform_device *pdev) +@@ -509,6 +565,11 @@ static int pwm_backlight_probe(struct platform_device *pdev) + /* Sync up PWM state. */ + pwm_init_state(pb->pwm, &state); + ++ /* Read real state, but only if the PWM is enabled. */ ++ pwm_get_state(pb->pwm, &state_real); ++ if (state_real.enabled) ++ state = state_real; ++ + /* + * The DT case will set the pwm_period_ns field to 0 and store the + * period, parsed from the DT, in the PWM device. For the non-DT case, +@@ -579,8 +640,20 @@ static int pwm_backlight_probe(struct platform_device *pdev) pb->scale = data->max_brightness; } @@ -121,6 +135,31 @@ index 111111111111..222222222222 100644 props.type = BACKLIGHT_RAW; props.max_brightness = data->max_brightness; +@@ -601,6 +674,24 @@ static int pwm_backlight_probe(struct platform_device *pdev) + + bl->props.brightness = data->dft_brightness; + bl->props.power = pwm_backlight_initial_power_state(pb); ++ if (bl->props.power == FB_BLANK_UNBLANK && pb->levels) { ++ u64 level; ++ ++ /* If the backlight is already on, determine the default ++ * brightness from PWM duty cycle instead of forcing ++ * the brightness determined by the driver ++ */ ++ pwm_get_state(pb->pwm, &state); ++ level = (u64)state.duty_cycle * pb->scale; ++ do_div(level, (u64)state.period); ++ ++ for (i = 0; i <= data->max_brightness; i++) { ++ if (data->levels[i] > level) { ++ bl->props.brightness = i; ++ break; ++ } ++ } ++ } + backlight_update_status(bl); + + platform_set_drvdata(pdev, bl); -- Armbian diff --git a/patch/kernel/archive/sunxi-6.12/series.addon b/patch/kernel/archive/sunxi-6.12/series.addon deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/patch/kernel/archive/sunxi-6.12/series.armbian b/patch/kernel/archive/sunxi-6.12/series.armbian index 42f71204d357..59841b9e258c 100644 --- a/patch/kernel/archive/sunxi-6.12/series.armbian +++ b/patch/kernel/archive/sunxi-6.12/series.armbian @@ -17,7 +17,6 @@ patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch - patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch @@ -79,13 +78,14 @@ patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch - patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch + patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch + patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch @@ -165,7 +165,8 @@ patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch - patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch + patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch + patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-234-ph-pg-uart-25-ph-pg.patch patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch patches.armbian/add-dtb-overlay-for-zero2w.patch patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch @@ -177,4 +178,4 @@ patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch - patches.armbian/bigtereetech-cb1-i2c-gpio-and-ws2812.patch + patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch diff --git a/patch/kernel/archive/sunxi-6.12/series.conf b/patch/kernel/archive/sunxi-6.12/series.conf index ca791015a3ec..c0bc934b2e62 100644 --- a/patch/kernel/archive/sunxi-6.12/series.conf +++ b/patch/kernel/archive/sunxi-6.12/series.conf @@ -187,10 +187,10 @@ patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch - patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch - patches.megous/drm-sun4i-Implement-gamma-correction.patch +- patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch +- patches.megous/drm-sun4i-Implement-gamma-correction.patch patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch - patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch +- patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch @@ -254,6 +254,39 @@ - patches.megous/Add-README.md-with-information-and-u-boot-patches.patch patches.megous/Defconfigs-for-all-my-devices.patch +################################################################################ +# +# drivers/gpu/drm/sun4i/ +# +################################################################################ + patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch + patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch + patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch + patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch + patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch + patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch + patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch + patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch + patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch + patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch + patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch + patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch + patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch + patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch + patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch + patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch + ################################################################################ # # Armbian patches @@ -273,7 +306,6 @@ patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch - patches.armbian/sound-soc-sunxi-sun4i-spdif-add-mclk_multiplier.patch patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch @@ -335,13 +367,14 @@ patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch - patches.armbian/arm64-dts-allwiner-sun50i-h616.dtsi-add-usb-ehci-ohci.patch + patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-GPU-node.patch patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch + patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch @@ -410,7 +443,7 @@ patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch - patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch +- patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch @@ -421,7 +454,8 @@ patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch - patches.armbian/arm64-dts-H616-Add-overlays-that-are-also-compatible-with-orang.patch + patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch + patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-234-ph-pg-uart-25-ph-pg.patch patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch patches.armbian/add-dtb-overlay-for-zero2w.patch patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch @@ -433,7 +467,4 @@ patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch - patches.armbian/bigtereetech-cb1-i2c-gpio-and-ws2812.patch -# The patches.addon folder where new patches are added before they get into -# one of the two main series. -# + patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch diff --git a/patch/kernel/archive/sunxi-6.12/series.drm b/patch/kernel/archive/sunxi-6.12/series.drm new file mode 100644 index 000000000000..f0781ed96215 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.12/series.drm @@ -0,0 +1,32 @@ +################################################################################ +# +# drivers/gpu/drm/sun4i/ +# +################################################################################ + patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch + patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch + patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch + patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch + patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch + patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch + patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch + patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch + patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch + patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch + patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch + patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch + patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch + patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch + patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch + patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch