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Commit 49a95dd

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depth r8, 32-wide in vex
1 parent dc6bc97 commit 49a95dd

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-9
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3 files changed

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-9
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deps/litex

Submodule litex updated from 1dccf57 to 7af1e5f

firmware/litex-fw/src/main.rs

+7-7
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,8 @@ riscv::plic_context!(PLIC0, 0xf0c00000, 0, VexInterrupt, VexPriority);
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5353
const FB_SIZE_X: usize = 720;
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const FB_SIZE_Y: usize = 720;
55-
static mut FB: Aligned<A4, [u32; FB_SIZE_X*FB_SIZE_Y]> = Aligned([0u32; FB_SIZE_X*FB_SIZE_Y]);
55+
const FB_XOFFS: usize = 80;
56+
static mut FB: Aligned<A4, [u32; FB_SIZE_X*FB_SIZE_Y/4]> = Aligned([0u32; FB_SIZE_X*FB_SIZE_Y/4]);
5657

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// Create the HAL bindings for the remaining LiteX peripherals.
5859

@@ -97,7 +98,7 @@ unsafe fn irq_handler() {
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let ix = ((ch0raw as i32 * (FB_SIZE_X) as i32) >> 16) as usize;
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let iy = ((ch1raw as i32 * (FB_SIZE_Y) as i32) >> 16) as usize;
100-
FB[(FB_SIZE_Y*(iy+FB_SIZE_Y/2)) + (ix+FB_SIZE_X/4)] = 0xFF;
101+
FB[((FB_SIZE_Y*(iy+FB_SIZE_Y/2)) + (ix+FB_SIZE_X/2-FB_XOFFS))/4] = 0xFF << (ix % 4)*8;
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}
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peripherals.EURORACK_PMOD0.ev_pending().write(|w| w.bits(pending_subtype));
@@ -161,13 +162,12 @@ fn main() -> ! {
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}
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*/
163164

164-
/*
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for p in 0..(FB_SIZE_X*FB_SIZE_Y) {
166-
FB[p] = 0;//(FB[p] >> 1);
165+
for p in 0..(FB_SIZE_X*FB_SIZE_Y/4) {
166+
FB[p] = (FB[p] >> 1) & 0x7f7f7f7f;
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}
168-
*/
168+
169+
timer.delay_ms(50u32);
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}
170171

171-
timer.delay_ms(500u32);
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}
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}

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