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RandyAGA.txt
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________ ____________ ____________________
\_ ____/ \______ \__ \/ \_____ \ | /
/ \ /\/ Ž/ \ \ Ž/ \_ _/
/ \/ \ / \/ / \ \
\_________/\______/ Ž____Œ___€____/ Ž____
····(G¡Ve$ ¥a':)·\____·········Œ_____··bZr
--------- RANDY of COMAX presents the AGA doc (V2.5) for AGA CODERS ----------
Programming AGA hardware
===========================
Future Amigas will *NOT* support *ANY* of the new AGA registers.
If you want your product to work on the next generation
of Amigas then detect aga before of run, and if is not present exit
or use ECS, that will be supported as emulation in the new C= low-end
and high-end machines. That machines will have probably a totally new
ChipSet, without any $dffXXX register, and probably not bitplane system.
Even the processor isn't necessarily final. It is strongly
rumoured that the Motorola MC68060 is the final member of the
68000 series, and may not even come out. Expect Amigas in 2-3
years to come with RISC chip processors running 680x0 emulation.
This is my AGA detect routine 101%... (thanx to DDT/HBT for the last 1%)
It will detect AGA on the future updated AGA machines.
Instead making a CMPI.B #$f8,$dff07c on that new AGA machines only old chipset
will be detected!!!!
LEA $DFF000,A5
MOVE.W $7C(A5),D0 ; DeniseID or LisaID in AGA
MOVEQ #30,D2 ; Check 30 times ( prevents old denise random)
ANDI.W #%000000011111111,d0 ; low byte only
DENLOOP:
MOVE.W $7C(A5),D1 ; Denise ID (LisaID on AGA)
ANDI.W #%000000011111111,d1 ; low byte only
CMP.B d0,d1 ; same value?
BNE.S NOTAGA ; Not the same value, then OCS Denise!
DBRA D2,DENLOOP ; (THANX TO DDT/HBT FOR MULTICHECK HINT)
ORI.B #%11110000,D0 ; MASK AGA REVISION (will work on new aga)
CMPI.B #%11111000,D0 ; BIT 3=AGA (this bit will be=0 in AAA!)
BNE.S NOTAGA ; IS THE AGA CHIPSET PRESENT?
ST.B AGA ; Set the AGA flag that will be tested later
NOTAGA: ; NOT AGA, BUT IS POSSIBLE AN AAA MACHINE!!
I have an A4000 at home and I needed to fix 3 or more AGA demos to work on
it, because them said: YOU NEED AN AGA MACHINE (!!)... that demos are:
NOP 1/muffbusters, RedNexRevivalIntro (for a bad processor test) and others..
New AGA features:
More Bitplanes - The maximum number of bitplanes has increased to 8 in all
resolution modes. This translates to a 256 entry color table for each
available mode.
Enhanced Dual Playfield Support - Each playfield may now have up to 4
bitplanes. The bank of 16 colors in the 256 color table is independently
selectable for each playfield.
Larger Palette - Each entry in the color table may now be 25 bits wide (8
bits each for Red, Blue, and Green data -- plus 1 bit for genlock
information). This translates to a palette of 16,777,216 colors.
Enhanced Sprite Support - Sprite resolution can be set to lores, hires, or
super-hires, independent of screen resolution. Attached sprites are now
available in all modes. However, some new higher bandwidth modes may
only allow one sprite. Odd and even sprites may use their own independent
16 color bank from the 256 color table. Old format sprites may still be 16
bits wide, and new format sprites may be 32 or 64 bits wide. Sprites may
now optionally appear in the border region. The horizontal positioning
resolution of sprites has increased to 35ns (equivalent to super-hires
pixel widths.)
Enhanced hardware scrolling support - Two extra bits in $dff102
allow seamless scrolling of up to 64 bit wide bitplanes in all resolutions.
The resolution of bitplane scrolling has been increased to 35ns.
Hardware scan doubling support - 15khz bitplanes and sprites may now be
scan doubled for flicker free display on 31khz monitors, and for enhanced
display sharing with 31khz bitplanes.
ECS compatibility - New chips will power-up in an ECS compatibility mode,
which will allow many older self-booting programs to be run on new machines.
This is done with $dff1fc (FMODE): $0003 = FULL AGA 64 bit Fetch
$0000 = ECS COMPATIBILITY (16 bits)
When using 4 or 8-bit R/G/B values, scale your values to 32 bits by
duplicating your 8 bit value in all 4 bytes of the 32 bit value.
When scaling up a 4 bit value, duplicate it in all nibbles.
e.g.: 8-bit red value $1F becomes $1F1F1F1F;
4-bit red value $3 becomes $33333333;
ECSENA bit (formerly ENBPLCN3) is used to disable those register bits in
BPLCON3 that are never accessed by old copper lists, and in addition are
required by old style copper lists to be in their default
settings.Specifically ECSENA forces the following bits to their default low
settings: BRDRBLNK,BRDNTRAN,ZDCLKEN,EXTBLKEN, and BRDRSPRT.
CLXCON2 is reset by a write to CLXCON, so that old game programs will be
able to correctly detect collisions.
DIWHIGH is reset by writes to DIWSTRT or DIWSTOP. This is interlock is
inhertied from ECS Denise.
Important note about NUMBER OF COLORS: Older IFF code (even earlier
newiff code) would not load more than 32 color registers. The
new code has been updated to base its upper limit for color loading
on the ColorMap->Count of the ViewPort of the destination display.
Remove old limitations of 32 registers in your code, and replace
by limiting to ColorMap->Count registers.
Horizontal Comparators (from C-18 AGA Doc)
----------------------
All programmable comparators with the exception of VHPOSW have 35nSec
resolution.: DIWHIGH,HBSTOP,SPRCTL,BPLCON1. BPLCON1 has additional
high-order bits as well. Note that horizontal bit position representing
140nSec resolution has been changed to 3rd least significant bit,where
before it used to be a field`s LSB, For example, bit 00 in BPLCON1 used to
be named PF1H0 and now it`s called PF1H2.
Coercion of 15KHz to 31KHz:
---------------------------
We have added new hardware features to LISA to aid in properly displaying
15KHz and 31KHz viewports together on the same 31KHz display. LISA can
globally set sprite resolution to LORES,HIRES, or SHRES.
LISA will ignore SH10 compare bits in SPRxPOS when scan-doubling, thereby
allowing ALICE to use these bits individually set scan-doubling.
Note: There is no longer any need to "scramble" SHRES color table entries.
This artifice is no longer required and pepole who bypass ECS graphics
library calls to do their own 28MHz graphics are to be pointed at and
publicly humiliated.
***************************************************************************
To make a standard Amiga demo run on AGA chipset:
Please insert the followings lines in your copperlist:
dc.w $106,$c00 ;AGA sprites, palette and dual playfield reset
dc.w $1FC,0 ;AGA sprites and burst reset
And remember to set $108, $10a, $8e and $90 or you will get the WB values!
***************************************************************************
Previously impossible deeper modes:
Table 1: New ALICE Modes (In Addition to Modes Supported by ECS)
Mode Planes Colors Bandwidth (See note 1)
---- ------ ------ ----------------------
LORES (320x200) 6 64 (non HAM, non EHB) 1 (set KillEHB!)
7 128 1
8 256 1
8 HAM 256,000+(see note 2)1
Dual playfield, Max 4 bitplane per playfield 16 colours per playfield.
The bank of 16 colours in the 256 colour palette is selectabel per playfield.
-------------------------------------------------------------------------------
HIRES (640x200) 5 32 2
6 EHB 64 (see note 3) 2
6 HAM 4096 (see note 4) 2
6 64 (set killEHB) 2
7 128 2
8 256 2
8 HAM 256,000+(see note 2)2
Dual playfield, Max 4 bitplane per playfield 16 colours per playfield.
The bank of 16 colours in the 256 colour palette is selectabel per playfield.
-------------------------------------------------------------------------------
SUPERHIRES (1280x200)
1 2 (see note 5) 1
2 4 (see note 5) 1
3 8 2
4 16 2
5 32 4
6 EHB 64 (see note 3) 4
6 HAM 4096 (see note 4) 4
6 64 (set KillEHB) 4
7 128 4
8 256 4
8 HAM 256,000+(see note 2)4
Dual playfield, Max 4 bitplane per playfield 16 colours per playfield.
The bank of 16 colours in the 256 colour palette is selectabel per playfield.
-------------------------------------------------------------------------------
VGA (160,320,640x480 non-int. 31Khz - multiscan or VGA monitor needed)
1 2 (see note 5) 1
2 4 (see note 5) 1
3 8 2
4 16 2
5 32 4
6 EHB 64 (see note 3) 4
6 HAM 4096 (see note 4) 4
6 64 (set KillEHB) 4
7 128 4
8 256 4
8 HAM 256,000+(see note 2)4
Dual playfield, Max 4 bitplane per playfield 16 colours per playfield.
The bank of 16 colours in the 256 colour palette is selectabel per playfield.
-------------------------------------------------------------------------------
Super 72 (848x614 interlaced, 70 Hz frame rate) BANDWIDTH
----------------------------------------------- -----------
1 or 2 bitplanes, as ECS, but no colour fudging 1X
3 Bitplanes 8 colours 2X
4 Bitplanes 16 colours 2X
5 Bitplanes 32 colours 4X
6 Bitplanes 64 colours (Set KillEHB) 4X
7 Bitplanes 128 colours 4X
8 Bitplanes 256 colours 4X
6 Bitplanes EHB 32 * 2 colours 4X
6 Bitplanes HAM 4O96 colours 4X
8 Bitplanes HAM any of 2~24 colours 4X
Dual playfield,Max 4 bitplanes per playfield 2X or 4X
16 colours per playfield . The bank of 16 colours
in the 256 colour palette is selectable per playfield
Notes:
1 - The "Bandwidth" number describes the amount of fetch bandwidth required
by a particular screen mode. For example, a 5 bit deep VGA screen requires
the 4x bandwidth fetch mode while a 1 bit VGA screen requires only the 1x
mode.. This translates to the hardware having to move data 4 times faster.
To be able to move data at these higher rates, the higher bandwidth modes
require data to be properly aligned in CHIP memory that is fast enough to
support the bandwidth. Specifically, bandwidth fetch mode factors of 1
require data to be on 16 bit boundaries, factors of 2 require 32 bit
boundaries, and factors of 4 require 64 bit boundaries. Restrictions like
these are the best reason to use the system allocation functions whenever
data is being prepared for the custom hardware. It is not guaranteed that
all machines that have the new chipset will also have memory fast enough
for the 4x modes. Therefore, the ONLY way to know whether or not the
machine will support the mode you want is to check the Display Database.
* BANDWIDTH 1: MOVE.W #0,$DFF1FC
* BANDWIDTH 2: MOVE.W #2,$DFF1FC ;THEN BITMAPS 32 BIT ALIGNED AND
;MODULO = MODULO-4
* BANDWIDTH 4: MOVE.W #3,$DFF1FC ;THEN BITMAPS 64 BIT ALIGNED AND
;MODULO = MODULO-8
This table only shows the minimum required fetchmode (bandwidth) for each
screen mode.
You should always try and set the fetchmode as high as possible (if
you are 64-bit aligned and wide, then $11, if 32-bit aligned and wide
$01, etc...)
2 - New 8 bit HAM mode uses the upper 6 bits for 64 24-bit base register
colors or as a 6 bit modify value, plus the lower 2 bits for 18 bit hold or
modify mode control. This mode could conceivably allow simultaneous
display of more than 256,000 colors (up to 16.8 million, presuming a
monitor / screenmode with enough pixels.) Please note that while the
register planes and control planes are internally reversed in 8 bit HAM
(the control bits are the two LSBs instead of the two MSBs), programs
using graphics.library and intuition.library will not have to deal with
this reversal, as it will be handled automatically for them.
3 - This is like the original EHB mode, but in new resolutions. It uses 5
bits to yield 32 register colors, plus a sixth bit for 32 colors that are
1/2 as bright.
4 - This is like the original 6 bit Ham mode, but in new resolutions. It
uses the lower 4 bits for 16 register colors, plus the upper 2 bits for
modify mode control. This mode allows simultaneous display of 4096
colors.
5 - These modes are unlike the old VGA and SUPERHIRES modes in that they
are not restricted to a nonstandard 64 color palette.
*******************************************************************************
What is HAM-8 Format? (from howtocode6)
---------------------
Ham-8 uses *lower* two bits as the command (either
new register (%00), or alter Red, Green or Blue component, as in
standard HAM), and the *upper* 6 bits (planes 2 to 7) as the
register(0 to 63), or as an 6 bit hold-and-modify value to modify
the top 6 bits of an 8-bit colour component.
The lower two bits of the colour component are not altered, so
initial palettes have to be chosen carefuly (or use Art
Department Professional! or anything that selects colours better)
*******************************************************************************
From the OFFICIAL Advanced Amiga Chip Set (AA) Info.
AMIGA 1200
1. SUMMARY OF FEATURES FOR AA
-----------------------------
* 32 bit wide data bus supports input of 32-bit wide bitplane data and
allows doubling of memory bandwidth. Additional doubling of bandwidth
can be achieved by using Fast Page mode Ram. The same bandwidth
enhancements are available for sprites. Also the maximum number of
bitplanes useable in all modes was increased to eight(8).
* The Colour Palette has been expanded to 256 colors deep and 25 bits wide
(8-RED, 8-GREEN, 8-BLUE, 1-GENLOCK). This permits display of 256
simultaneous colors in all resolutions. A palette of 16,777,216 colours
is available in all resolutions.
* 28Mhz clock input allows for cleaner definition of HIRES and SHRES pixels.
ALICE's clock generator is sychronized by means of LISA's 14MHz SCLK
outputs. Genlock XCLK and XCLKEN* pins have been eliminated (external
MUX is now required).
* A new register bit allows sprites to appear in the screen border regions
(BRDRSPRT). So you can move sprites also out the display window defined
by DIWSTART and DIWSTOP, but remember to set also the bit 0 of $dff100
(bit 1 of $dff106)
* A bitplane mask field of 8-bits allows an address offset into the colour
palette. Two 4-bit mask fields do the same for odd and even sprites.
* In Dual-Playfield modes, 2-4 bitplane playfields are now possible in all
resolutions.
* Two Extra high-order playfield scroll bits allow seamless scrolling of
up to 64 bit wide bitplanes in all resolutions. Resolution of bitplane
scroll, display window, and horizontal sprite position has been improved
to 35ns in all resolutions.
* A new 8 bitplane HAM mode has been created, 6 for colours and 2 for
control bits. All HAM modes are available in all resolutions (not just
LORES as before).
* A RST_input pin has been added, which resets all the bits contained in
registers that were new for ECS or LISA:
BPLCON3, BPLCON4, CLXCON2, DIWHIGH, FMODE
* Sprite resolution can be set to LORES, HIRES, SHRES, independant of
bitplane resolution.
* Attached Sprites are now available in all resolutions.
* Hardware Scan Doubling support has been added for bitplanes and sprites.
This is intended to allow 15KHz screens to be intelligently displayed
on a 31KHz monitor, and share the display with 31KHz screens.
2. EXPLANATION OF NEW FEATURES
------------------------------
Bitplanes:
----------
There are now 8 bitplanes instead of 6. In single playfield modes they
can address 256 colours instead of just 64. As long as the memory
architecture supports the bandwidth, all 8 bitplanes are available in all
3 resolutions. In the same vein, 4+4 bitplane dual playfield is available
in all 3 resolutions, unless bitplane scan-doubling is enabled, in which
case both playfields share the same bitplane modulus register. Bits 15 thru
8 of BPLCON4 comprise an 8-bit mask for the 8 bitplane address, XOR'ing the
individual bits. This allows the copper to exchange colour maps with a
single instruction. BPLCON1 now contains an 8-bit scroll value for each of
the playfields. Granularity of scroll now extends down to 35nSec. (1 SHRES
pixel), and scroll can delay playfield thru 32 bus cycles. Bits BPAGEM and
BPL32 in new register FMODE control size of bitplane data in BPLDAT thru
BPL8DAT.
The old 6 bitplane HAM mode, unlike before, works in HIRES and SHRES
resolutions. As before bitplanes 5 and 6 control its function as follows:
BP6 BP5 RED GREEN BLUE
----------------------------------------------------------
0 0 select new base register (1 of 16)
0 1 hold hold modify
1 0 modify hold hold
1 1 hold modify hold
There is a new 8 bitplane HAM (Hold and Modify) mode. This mode is invoked
when BPU field in BPLCON0 is set to 8, and HAMEN is set. Bitplanes 1 and 2
are used as control bits analagous to the function of bitplanes 5 and 6 in 6
bitplane HAM mode:
BP2 BP1 RED GREEN BLUE
----------------------------------------------------------
0 0 select new base register (1 of 64)
0 1 hold hold modify
1 0 modify hold hold
1 1 hold modify hold
Since only 6 bitplanes are available for modify data, the data is placed
in the 6 MSB. The 2 LSB are left unmodified, which allows creation of all
16,777,216 colours simultaneously, assuming one had a large enough screen
and picked one's base registers judiciously. This HAM mode also works in
HIRES and SHRES modes.
For compatibility reasons EHB mode remains intact. Its existence is rather
moot in that we have more than enough colours in the colour table to replace
its functionality. As before, EHB is invoked whenever SHRES= HIRES= HAMEN=
DPF=0, and BPU=6. Please note that starting with ECS DENISE there is a bit
in BPLCON2 which disables this mode (KILLEHB).
Sprites:
--------
Bits SPAGEM and SPR32 in FMODE whether size of sprite load data in SPR0DATA(B)
thru SPR7DATA(B) is 16,32 or 64 bits, analagous to bitplanes. BPLCON3 contains
several bits relating to sprite behavior, SPRES1 and SPRES0 control sprite
resolution, whether they conform to the ECS standard, or overide to LORES,
HIRES or SHRES. BRDRSPRT, when high, allows sprites to be visible in border
areas. ESPRM7 thru ESPRM4 allow relocation of the even sprite colour map.
OSPRM7 thru OSPRM4 allow relocation of the odd sprite colour map. In the case
of attached sprites OSPRM bits are used.
Colour Lookup Table:
--------------------
The colour table has grown from 32 13-bit registers to 256 25-bit registers.
Several new register bits have been added to BPLCON3 to facilitate loading
the table with only 32 register addresses. LOCT, selects either the 16 MSB
or LSB for loading. Loading the MSB always loads the LSB as well for
compatibility, so when 24-bit colours are desired load LSB after MSB.
BANK2,1,0 select 1 of 8 32 address banks for loading as follows:
BANK2 BANK1 BANK0 Colour Address Range
--------------------------------------------------------
0 0 0 COLOUR00 - COLOUR1F
0 0 1 COLOUR20 - COLOUR3F
0 1 0 COLOUR40 - COLOUR5F
0 1 1 COLOUR60 - COLOUR7f
1 0 0 COLOUR80 - COLOUR9F
1 0 1 COLOURA0 - COLOURBF
1 1 0 COLOURC0 - COLOURDF
1 1 1 COLOURE0 - COLOURFF
RDRAM bit in BPLCON2 causes LISA to interpret all colour table accesses as
reads.
Note: There is no longer any need to "Scramble" SHRES colour table entries.
This artifice is no longer required and people who bypass ECS graphics
library calls to do their own 28MHz graphics are to be pointed at and
publicly humiliated.
Collision:
----------
A new register CLXCON2 contains 4 new bits. ENBP7 and ENBP6 are the enable
bits for bitplanes 7 and 8, respectively. Similarly, MVBP7 and MVBP8 are
their match value bits. CLXDAT is unchanged.
Horizontal Comparators:
-----------------------
All programmable comparators with the exception of VHPOSW have 35nSec
resolutions; DIWHIGH, HBSTRT, HBSTOP, SPRCTL, BPLCON1. BPLCON1 has additional
high-order bits as well. Note that horizontal bit position representing
140nSec resoloution has been changed to 3rd least significant bit, where
before it used to be a field's LSB. For example, bit-0 in BPLCON1 used to
be named PF1H0 and now it's called PF1H2.
Coercion of 15KHz to 31KHz:
---------------------------
We have added new hardware features to LISA to aid in properly displaying
15KHz and 31KHz viewports together on the same 31KHz display. LISA can
globally set sprite resolution to LORES, HIRES, or SHRES. LISA will ignore
SH10 compare bit in SPRxPOS when scan-doubling, therby allowing ALICE to
use these bits to individually set scan-doubling.
NEW AGA-ECS REGISTERS: (thanx to DDT/HBT for ECS help)
;CUSTOM = $DFF000
vposr EQU $004 ; Read vertical most significant bits (and frame flop)
Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Use LOF I6 I5 I4 I3 I2 I1 I0 LOL -- -- -- -- v10 v9 V8
LOF=Long frame(auto toggle control bit in BPLCON0)
I0-I6 Chip identitication:
8361 (Regular) or 8370 (Fat) (Agnus-ntsc)=10
8367 (Pal) or 8371 (Fat-Pal) (Agnus-pal)=00
8372 (Fat-hr) (agnushr),thru rev4 = 20 Pal,30 NTSC
8372 (Fat-hr) (agnushr),rev 5 = 22 Pal, 31 NTSC
8374 (Alice) thru rev 2 = 22 Pal, 32 NTSC
8374 (Alice) rev 3 thru rev 4 = 23 Pal, 33 NTSC
LOL = Long line bit. When low, it indicates short raster line.
v9,10 -- hires chips only (20,30 identifiers)
*******************************************************************************
cdang EQU $02e ; Copper control register
This is a 1-bit register that when set true, allows the copper to
access the blitter hardware. This bit is cleared by power-on reset,
so that the copper cannot access the blitter hardware.
01 CDANG (STD) Copper danger mode. Allows Copper access to
blitter if set ($DFF03E to $DFF07E).
(ECS) If clear copper can only access addresses
($DFF03E to $DFF07E). If set copper can
access all chip registers.
*******************************************************************************
STREQU EQU $038 ;Strobe for horiz sync with VB (vert blank) and EQU
STRVBL EQU $038 ;Strobe for horiz sync with VB
STRHOR EQU $03C ;Strobe for horiz sync
STRLONG EQU $03E ;Strobe for identification of long horiz line (228cc)
One of the first 3 strobe addresses above, it is placed on the RGA bus during
the first refresh time slot of every other line, to identify lines with long
counts (228- NTSC, HTOTAL+2- VARBEAMEN=1 hires chips only).There are 4 refresh
time slots and any not used for strobes will leave a null (1FE) address on the
RGA bus.
*******************************************************************************
pad2d EQU $05A ; note: byte access only
; function unknown
*******************************************************************************
bltcon0l EQU $05B ; note: byte access only - write only
; Blitter control 0, lower 8 bits (minterms)
The BLTCON0L register writes the low bits of BLTCON0, thereby expediting
the set up of some blits and generally speeding up the software, since the
upper bits are often the same.
*******************************************************************************
bltcon1 EQU $042 ; Blitter control register 1
Bit 7 (DOFF) of the BLTCON1 register, when set, disables the output of the
Blitter hardware on channel D.
This allows inputs to channels A, B and C and certain address modification
if necessary, without the Blitter outputting over channel D.
*******************************************************************************
bltsizv EQU $05C ; Blitter Size Vertical
0 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 H0
H=Height (32768 lines Max)
*******************************************************************************
bltsizh EQU $05E
; Blitter Size Horizontal
0 0 0 0 0 W10 W9 W8 W7 W6 W5 W4 W3 W2 W1 W0
W=Width in words (2048 words = 32768 pixels Max)
Writing this register starts the Blitter
With these two registers, blits up to 32K by 32K are now possible - much
larger than the original chip set could accept. The original commands are
retained for compatibility. BLTSIZV should be written first, followed by
BLTSIZH, which starts the blitter.
*******************************************************************************
pad34 EQU $068-$06a-$06c-$06e ;UNUSED
*******************************************************************************
pad3b EQU $076 ;UNUSED
*******************************************************************************
BPLHDAT EQU $07A ;Ext logic UHRES bit plane identifier
*******************************************************************************
SPRHDAT EQU $078 ;Ext logic UltraHiRes sprite pointer and data identif.
This identifies the cycle when this pointer address is on the bus accessing
the memory.
*******************************************************************************
deniseid EQU $07C ; (or Lisaid) Denise chip ID (to check the chipset)
Lower 8 bits: - Random value if standard Denise is present
- $FC if ECS Denise is present
- $F8 if AGA chipset is present
The original Denise (8362) does not have this register, so whatever value is
left over on the bus from the last cycle will be there. ECS Denise (8373)
returns hex (fc) in the lower 8 bits.Lisa returns hex (f8). The upper 8 bits
of this register are loaded from the serial mouse bus, and are reserved for
future hardware implentation.
The 8 low-order bits are encoded as follows: (from C-18 AGA doc)
BIT# Description
---- --------------------------------------------------
7-4 Lisa/Denise/ECS Denise Revision level(decrement to
bump revision level, hex F represents 0th rev. level).
3 Maintain as a 1 for future generation
2 When low indicates AA feature set (LISA)
1 When low indicates ECS feature set (LISA or ECS DENISE)
0 Maintain as a 1 for future generation
*******************************************************************************
bplcon0 EQU $100 ; 15 = HIRES
; 14 = BPU2 \
; 13 = BPU1 |select num of bitplanes, from 0 thru 7
; 12 = BPU0 /
; 11 = HAM - old HAM, and HAM8 AGA (if bit 4 is set)
; 10 = DBLPF - double playfield
; 9 = COLOR - Composite video (Genlock)
; 8 = GAUD - Composite audio
; 7 = UHRES - 1024*1024 (set also bit 9 in DMACON)
; 6 = superhires 1280x 35ns
; 5 = BPLHWRM - screen black and white, no copcolors
;BYPASS = 0
; 4 = 8 planes (then bits 12-14 must be 0)
; 3 = LPEN - Light pen
; 2 = LACE - Interlace mode
; 1 = ERSY - External resync
; 0 = ECSENA Enable bplcon3 register (ECS-AGA)
bit 7 of $dff100 is the UHRES bit (ultra hires is think)...i don't know
how this works exactly but my suspicions is that it is 1024*1024 and i
only 1 bitplane deep... the bitplane pointer for UHRES is $dff1ec and
$dff1ee!!!! so its a new bitplanepointer!!!! it only works in vram (what
the hell is that anyway??) you have also a vram spritepointer extra...
(also uhres!!)..(also needs bits in DMACON).
Disables hard stops for vert, horiz display windows
BYPASS = Bitplanes are scrolled and prioritized normally, but bypass color
table and 8 bit wide data appear on R(7:0).
RST_pin resets all bits in all registers new to AA. These registers include:
BPLCON3, BPLCON4, CLXCON2, DIWHIGH, FMODE.
ECSENA bit (formerly ENBPLCN3) is used to disable those register bits in
BPLCON3 that are never accessed by old copper lists, and in addition are
required by old-style copper lists to be in their default settings.
Specifically, ECSENA forces the following bits to their default low settings:
BRDRBLNK, BRDNTRAN, ZDCLKEN, EXTBLKEN, and BRDRSPRT. When ECSENA is set high
again, the former settings for these bits are restored.
CLXCON2 is reset by a write to CLXCON, so that old game programs will be
able to correctly detect collisions.
*******************************************************************************
bplcon1 EQU $102 ; bits 8 to 14 used for 1/4 pixel scroll
; 2 bits are for displacing the pixels in
; steps of 1/4 for the odd planes and 2 for
; the even planes. the other 2 pairs of bits
; are for scrolling in steps of 16 pixels a
; time (one pair for odd planes and one pair
; for even). This means that you can move any
; playfield 64 pixels to any side with
; intervals of 1/4 pixel!!!
; you have 256 possible scrollvalues=8bits...
15 PF2H7 - 64 PIXEL SCROLL PF2 (AGA)
14 PF2H6 - 64 PIXEL SCROLL PF2 (AGA)
13 PF2H1 - FINE SCROLL PF2 (AGA SCROLL 35ns 1/4 of pixel)
12 PF2H0 - FINE SCROLL PF2
11 PF1H7 - 64 PIXEL SCROLL PF1 (AGA)
10 PF1H6 - 64 PIXEL SCROLL PF1 (AGA)
09 PF1H1 - FINE SCROLL PF1 (AGA SCROLL 35ns 1/4 of pixel)
08 PF1H0 - FINE SCROLL PF1
07 PF2H3
06 PF2H2
05 PF2H1
04 PF2H0
03 PF1H3
02 PF1H2
01 PF1H1
00 PF1H0
PF2H=Playfield 2 scroll code PFlH=Playfield 1 scroll code
PF2Hx = Playfield 2 horizontal scroll code, x=0-7
PF1Hx = Playfield 1 horizontal scroll code, x=0-7 where PFyH0=LSB=35ns
SHRES pixel (bits have been renamed, old PFyH0 now PFyH2, ect). Now that the
scroll range has been quadrupled to allow for wider (32 or 64 bits) bitplanes.
Smooth Hardware Scrolling (from howtocode 6)
-------------------------
Extra bits have been added to BPLCON1 to allow smoother hardware
scrolling and scrolling over a larger area.
Bits 8 (PF1H0) and 9 (PF1H1) are the new hi-resolution scroll bits for
playfield 0 and bits 12 (PF2H0) and 13 (PF2H1) are the new bits for
playfield 1.
Another two bits have been added for each bitplane at bits 10 (PF1H6)
and 11 (PF1H7) for playfield 1 and bits 14 (PF2H6) and 15 (PF2H7) to
increase the maximum scroll range from 16 lo-res pixels to 64 lo-res
pixels (or 256 superhires pixels).
Normal 0-16 positions therefore are normal, but it you want to
position your screen at a (super) hires position you need to set
the new bits, or if you require smooth hardware scrolling with either
2x or 4x Fetch Mode.
*******************************************************************************
bplcon2 EQU $104 ; Bit Plane Control Register 2 (video priority control)
15 -
14 ECS ZDBPSEL2 \ Select one of the 8 BitPlanes
13 ECS ZDBPSEL1 } in ZDBPEN genlock mod
12 ECS ZDBPSEL0 /
11 ECS ZDBPEN Use BITPLANEKEY - use bitplane as genlock bits
10 ECS ZDCTEN Use COLORKEY - colormapped genlock bit
09 ECS KILLEHB Kill ExtraHalfBrite (for a normal 6bpl pic)
08 AGA RDRAM All color tabs are reads
07 AGA SOGEN (ZDCLKEN) Enable 14Mhz clock
06 PF2PRI PField 2 priority over PField 1
05 PF2P2 \
04 PF2P1 } PField 2 sprite priority
03 PF2P0 /
02 PF1P2 \
01 PF1P1 } PField 1 sprite priority
00 PF1P0 /
Using 64-colour mode (NOT extra halfbrite) requires setting the
KILLEHB (bit 9) in BPLCON2.
ZDBPSELx =3 bit field which selects which bitplane is to be used for ZD when
ZDBBPEN is set;000 selects BB1 and 111 selects BP8.
ZDBPEN = Causes ZD pin to mirror bitplane selected by ZDBPSELx bits. This does
not disable the ZD mode defined by ZDCTEN, but rather is "ored" with it.
ZDCTEN = Causes ZD pin to mirror bit #15 of the active entry in high color
table. When ZDCTEN is reset ZD reverts to mirroring color (0).
SOGEN = When set causes SOG output pin to go high
RDRAM bit in BPLCON2 causes LISA to interpret all colour table accesses as
reads instead of writing to it.
Lots of new genlock features were added to ECS denise and are carried over
to LISA. ZDBPEN in BPLCON2 allows any bitplane, delected by ZDBPSEL2,1,0,
to be used as a tansparency mask (ZD pin mirrors contents of selected
bitplane). ZDCTEN disables the old COLOUR00 is transparent mode, and allows
the bit-31 position of each colour in the colour table to control transparency
. ZDCLKEN generates a 14MHz clock synchronized with the video data that can
be used by video post-processors.
*******************************************************************************
bplcon3 EQU $106 ; 0 = EXTBLNKEN - external blank enable
; 1 = BRDSPRT - EXTBLKZD - external blank ored
; into trnsprncy- sprites on BORDERS!
; 2 = ZDCLKEN - zd pin outputs a 14mhz cloc
; 3 = NO FUNCTIONS - SET TO ZERO
; 4 = ECS BRDRTRAN Border opaque
; 5 = ECS BRDRBLNK Border blank
; 6 = AGA SPRES1 \sprite hires,lores,superhires
; 7 = AGA SPRES0 /
; 8 = NO FUNCTIONS - SET TO ZERO
; 9 = LOCT - palette high or low nibble colour
; 10 = PF2OF2 \
; 11 = PF2OF1 } second playfield's offset in coltab
; 12 = PF2OF0 /
; 13 = BANK0 \
; 14 = BANK1 } LOCT palette select 256
; 15 = BANK2 /
;
BANKx = Selects one of eight color banks, x=0-2.
Bits PF2OF2,1,0 in BPLCON3 determine second playfield's offset into the
colour table. This is now necessary since playfields in DPF mode can have
up to 4 bitplanes. Offset values are as defined in register map.
The bits 10 and 11 must be set as default to made the old 16 colours dual
playfiled, so remember that ($106,$c00) (Thanx to MUCSI/Muffbusters)
PF20Fx = Determine bit plane color table offset whe playfield 2 has priority
in dual playfield mode:
PF20F || AFFECTED BITPLANE ||OFFSET (From C-18 AGA doc)
-------------------------------------------------------
| 2 | 1 | 0 || 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 ||(decimal)
-------------------------------------------------------
| 0 | 0 | 0 || - | - | - | - | - | - | - | - || none
| 0 | 0 | 1 || - | - | - | - | - | - | 1 | - || 2
| 0 | 1 | 0 || - | - | - | - | - | 1 | - | - || 4
| 0 | 1 | 1 || - | - | - | - | - | 1 | - | - || 8 (default)
| 1 | 0 | 0 || - | - | - | 1 | - | - | - | - || 16
| 1 | 0 | 1 || - | - | 1 | - | - | - | - | - || 32
| 1 | 1 | 0 || - | 1 | - | - | - | - | - | - || 64
| 1 | 1 | 1 || 1 | - | - | - | - | - | - | - || 128
LOCT = Dictates that subsequent color palette values will be written to a
second 12- bit color palette, constituting the RGB low minus order bits.
Writes to the normal hi monus order color palette automattically copied to
the low order for backwards compatibility.
(selects either the 16 MSB or LSB for loading)
BRDNTRAN in BPLCON3 generates an opaque border region which can be used to
frame live video. (Genlock)
BRDRBLNK = "Border area" is blanked instead of color (0).
Disabled when ECSENA low.
BRDRSPRT, when high, allows sprites to be visible out the display window.
but if you want it to work you have to enable ECSENA. This is bit 0 from
$dff100! (this is for compatibilty reasons!)
ZDCLKEN = ZD pin outputs a 14MHz clock whose falling edge coincides with hires
(7MHz) video data. this bit when set disables all other ZD functions.
Disabled when ESCENA low.
EXTBLKEN = causes BLANK output to be programmable instead of reflecting
internal fixed decodes. Disabled when ESCENA low.
*******************************************************************************
bplcon4 EQU $10C ; 0 ESPRM7 \
; 1 ESPRM6 \ CHOOSE EVEN SPRITE PALETTE
; 2 ESPRM5 /
; 3 ESPRM4 /
; 4 OSPRM4 \
; 5 OSPRM4 \ CHOOSE ODD SPRITE PALETTE
; 6 OSPRM4 /
; 7 OSPRM4 /
; 8 BPLAM0 \
; 9 BPLAM1 \
; 10 BPLAM2 |
; 11 BPLAM3 | Switch colours without
; 12 BPLAM4 | change the palette
; 13 BPLAM5 |
; 14 BPLAM6 /
; 15 BPLAM7 /
BPLAMx = This 8 bit field is XOR`ed with the 8 bit plane color address,thereby
altering the color address sent to the color table (x=1-8)
Bits 15 thru 8 of BPLCON4 comprise an 8-bit mask for the 8 bitplane address,
XOR'ing the individual bits. This allows the copper to exchange colour maps
with a single instruction.
ESPRMx = 4 Bit field provides the 4 high order color table address bits for
even sprites: SPR0,SPR2,SPR4,SPR6. Default value is 0001 binary. (x=7-4)
OSPRMx = 4 Bit field provides the 4 high order color table address bits for
odd sprites: SPR1,SPR3,SPR5,SPR7. Default value is 0001 binary. (x=7-4)
*******************************************************************************
clxcon2 EQU $10E ; 0 match value for bitplane 7 collision
; 1 match value for bitplane 8 collision
; 2-5: UNUSED
; 6 ENBP8 enable bitplane 7 (match reqd coll)
; 7 ENBP8 enable bitplane 8 (match reqd coll)
; 8-15: UNUSED
A new register CLXCON2 contains 4 new bits. ENBP7 and ENBP6 are the enable
bits for bitplanes 7 and 8, respectively. Similarly, MVBP7 and MVBP8 are
their match value bits. CLXDAT is unchanged.
*******************************************************************************
BPL7DAT EQU $11c W ;Bit plane 7 data (parallel to serial convert)
BPL8DAT EQU $11e W ;Bit plane 8 data (parallel to serial convert)
*******************************************************************************
SPRxPOS EQU $140/... ;Sprite x vert-horiz start position data.
BIT# SYM FUNCTION
---- ---- -----------------------------------------
15-08 SV7-SV0 Start vertical value.High bit (SV8) is
in SPRxCTL register below.
07-00 SH10-SH3 Sprite horizontal start value. Low order
3 bits are in SPRxCTL register below. If
SSCAN2 bit in FMODE is set, then disable
SH10 horizontal coincidence detect.This bit
is then free to be used by ALICE as an
individual scan double enable.
*******************************************************************************
sprxctl EQU $142/14A/152/15A/162/16A/172/17A
Sprite x vert stop and control data
BIT# SYM FUNCTION
---- ---- ----------------------------------------
15-08 EV7-EV0 End (stop) vert. value. Low 8 bits
07 ATT Sprite attach control bit (odd sprites only)
06 AGA SV9 Start vert value 10th bit.
05 AGA EV9 End (stop) vert. value 10th bit
04 ECS SH1=0 Start horiz. value, 70nS increment
03 AGA SH0=0 Start horiz. value 35nS increment
02 SV8 Start vert. value 9th bit
01 EV8 End (stop) vert. value 9th bit
00 SH2 Start horiz.value,140nS increment
These 2 registers work together as position, size and
feature sprite control registers.They are usually loaded
by the sprite DMA channel, during horizontal blank,
however they may be loaded by either processor any time.
Writing to SPRxCTL disables the corresponding sprite.
*******************************************************************************
144/146/14C/14E/154/156/15C/15E/164/166/16C/16E/174/176/17C/17E
Sprite image Data (From C-18 AGA doc)
These registers buffer the sprite image data.They are usually loaded by the
sprite DMA channel but may be loaded by either processor at any time. When a
horizontal coincidence occurs the buffers are dumped into shift registers and
serially outputed to the display, MSB first on the left.
NOTE: Writing to the A buffer enables (arms) the sprite.
Writing to the SPRxCTL registers disables the sprite.
If enabled, data in the A and B buffers will be output whenever the beam
counter equals the sprite horizontal position value in the SPRxPOS register.
In lowres mode, 1 sprite pixel is 1 bitplane pixel wide.In HRES and SHRES
mode, 1 sprite pixel is 2 bitplane pixels.
The DATB bits are the 2SBs (worth 2) for the color registers, and MSB for
SHRES. DATA bits are LSBs of the pixels.
*******************************************************************************
COLORxx 180-1BE W COLOR table xx (From C-18 AGA DOC)
There 32 of these registers (xx=00-31) and together with the banking bits they
address the 256 locations in the color palette. There are actually two sets of
color regs, selection of which is controlled by the LOCT reg bit.
When LOCT = 0 the 4 MSB of red, green and blue video data are selected along
with the T bit for genlocks the low order set of registers is also selected as
well, so that the 4 bi valuesare automatically extended to 8 bits.
This provides compatibility with old software. If the full range of palette
values are desired, then LOCT can be set high and independant values for the 4
LSB of red, green and blue can be written. The low order color registers do
not contain a transparency (T) bit.
The table below shows the color register bit usage.
BIT# 15,14,13,12 11,10,09,08 07,06,05,04 03,02,01,00
---- ----------- ----------- ----------- -----------
LOCT=0 T X X X R7 R6 R5 R4 G7 G6 G5 G4 B7 B6 B5 B4
LOCT=1 X X X X R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0
T = TRANSPARENCY R = RED G = GREEN B = BLUE X = UNUSED
T bit of COLOR00 thru COLOR31 sets ZD_pin HI, When that color is selected in
all video modes.
*******************************************************************************
htotal EQU $1c0 ; Highest number count, horiz line
; (VARBEAMEN bit in BEAMCON0 must be set)
HTOTAL W A Highest number count in horizontal line
Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 10 00
Use 0 0 0 0 0 0 0 0 h8 h7 h6 h5 h4 h3 h2 h1
Horiz line has theis many + 1 280nS increments. If the pal bit & LOLDIS are
not high, long line/skort line toggle will occur, and there will be this many
+2 every other line. Active if VARBEAMEN=1 or DUAL+1.
*******************************************************************************
hsstop EQU $1c2 ; Horizontal line position for HSYNC stop
Sets # of colour clocks for sync stop (HTOTAL for bits)
*******************************************************************************
hbstrt EQU $1c4 ; Horizontal line position for HBLANK start
hbstop EQU $1c6 ; Horizontal line position for HBLANK stop
Bits 7-0 contain the stop and start positions, respectively, for programed
horizontal blanking in 280nS increments.Bits 10-8 provide a fine position
control in 35nS increments.
BIT# FUNCTION DESCRIPTION (from C-18 AGA doc)
---- -------- -----------
15-11 x (unused)
10 H1 140nS
09 H1 70nS
08 H0 35nS
07 H10 35840nS
06 H9 17920nS
05 H8 8960nS
04 H7 4480nS
03 H6 2240nS
02 H5 1120nS
01 H4 560nS
00 H3 280nS
*******************************************************************************
vtotal EQU $1c8 ; Highest numbered vertical line
; (VARBEAMEN bit in BEAMCON0 must be set)
VTOTAL W A Highest numbered vertical line
VTOTAL contains the line number at which to reset the vertical position
counter. This value represents the number of lines in a field(+1). The
exception is if the INTERLACE bit is set (BPLCON0). In this case this
value represents the number of lines in the long field (+2) and the number
of lines in the short field (+1).
*******************************************************************************
vsstop EQU $1ca ; Vertical line position for VSYNC stop
*******************************************************************************
vbstrt EQU $1cc ; Vertical line for VBLANK start
vbstop EQU $1ce ; Vertical line for VBLANK stop
(V10-0 <- D10-0) Affects CSY pin if BLAKEN=1 and VSY pin if CSCBEN=1 (BEAMCON0)