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| 1 | +// SPDX-License-Identifier: (GPL-2.0+) |
| 2 | + |
| 3 | +/dts-v1/; |
| 4 | + |
| 5 | +#include "ipq6018.dtsi" |
| 6 | +#include "ipq6018-upstreamable.dtsi" |
| 7 | +#include "ipq6018-ess.dtsi" |
| 8 | + |
| 9 | +#include <dt-bindings/input/input.h> |
| 10 | +#include <dt-bindings/gpio/gpio.h> |
| 11 | + |
| 12 | +/ { |
| 13 | + model = "Qihoo 360 V6"; |
| 14 | + compatible = "qihoo,v6", "qcom,ipq6018"; |
| 15 | + |
| 16 | + aliases { |
| 17 | + serial0 = &blsp1_uart3; |
| 18 | +// led-boot = &led_power; |
| 19 | +// led-failsafe = &led_power; |
| 20 | +// led-running = &led_power; |
| 21 | +// led-upgrade = &led_power; |
| 22 | + }; |
| 23 | + |
| 24 | + chosen { |
| 25 | + stdout-path = "serial0:115200n8"; |
| 26 | + }; |
| 27 | + |
| 28 | + keys { |
| 29 | + compatible = "gpio-keys"; |
| 30 | + |
| 31 | + reset { |
| 32 | + label = "reset"; |
| 33 | + gpios = <&tlmm 68 GPIO_ACTIVE_LOW>; |
| 34 | + linux,code = <KEY_RESTART>; |
| 35 | + }; |
| 36 | + |
| 37 | + wps { |
| 38 | + label = "reset"; |
| 39 | + gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; |
| 40 | + linux,code = <KEY_WPS_BUTTON>; |
| 41 | + }; |
| 42 | + }; |
| 43 | +}; |
| 44 | + |
| 45 | +&blsp1_uart3 { |
| 46 | + pinctrl-0 = <&serial_3_pins>; |
| 47 | + pinctrl-names = "default"; |
| 48 | + status = "okay"; |
| 49 | +}; |
| 50 | + |
| 51 | +&tlmm { |
| 52 | + |
| 53 | + mdio_pins: mdio-pins { |
| 54 | + mdc { |
| 55 | + pins = "gpio64"; |
| 56 | + function = "mdc"; |
| 57 | + drive-strength = <8>; |
| 58 | + bias-pull-up; |
| 59 | + }; |
| 60 | + |
| 61 | + mdio { |
| 62 | + pins = "gpio65"; |
| 63 | + function = "mdio"; |
| 64 | + drive-strength = <8>; |
| 65 | + bias-pull-up; |
| 66 | + }; |
| 67 | + }; |
| 68 | +}; |
| 69 | + |
| 70 | +&soc { |
| 71 | + dp1: dp@1 { |
| 72 | + compatible = "qcom,nss-dp"; |
| 73 | + reg = <0x0 0x3a001000 0x0 0x200>; |
| 74 | + qcom,mactype = <0>; |
| 75 | + qcom,id = <1>; |
| 76 | + |
| 77 | + phy-handle = <&phy_0>; |
| 78 | + phy-mode = "sgmii"; |
| 79 | + }; |
| 80 | + |
| 81 | + dp2 { |
| 82 | + compatible = "qcom,nss-dp"; |
| 83 | + reg = <0x0 0x3a001200 0x0 0x200>; |
| 84 | + qcom,mactype = <0>; |
| 85 | + qcom,id = <2>; |
| 86 | + |
| 87 | + phy-handle = <&phy_1>; |
| 88 | + phy-mode = "sgmii"; |
| 89 | + }; |
| 90 | + |
| 91 | + dp3 { |
| 92 | + compatible = "qcom,nss-dp"; |
| 93 | + reg = <0x0 0x3a001400 0x0 0x200>; |
| 94 | + qcom,mactype = <0>; |
| 95 | + qcom,id = <3>; |
| 96 | + |
| 97 | + phy-handle = <&phy_2>; |
| 98 | + phy-mode = "sgmii"; |
| 99 | + }; |
| 100 | + |
| 101 | + dp4 { |
| 102 | + compatible = "qcom,nss-dp"; |
| 103 | + reg = <0x0 0x3a001600 0x0 0x200>; |
| 104 | + qcom,mactype = <0>; |
| 105 | + qcom,id = <4>; |
| 106 | + |
| 107 | + phy-handle = <&phy_3>; |
| 108 | + phy-mode = "sgmii"; |
| 109 | + }; |
| 110 | + |
| 111 | + dp5 { |
| 112 | + compatible = "qcom,nss-dp"; |
| 113 | + reg = <0x0 0x3a001800 0x0 0x200>; |
| 114 | + qcom,mactype = <0>; |
| 115 | + qcom,id = <5>; |
| 116 | + |
| 117 | + phy-handle = <&phy_4>; |
| 118 | + phy-mode = "sgmii"; |
| 119 | + }; |
| 120 | +}; |
| 121 | + |
| 122 | +&edma { |
| 123 | + status = "okay"; |
| 124 | +}; |
| 125 | + |
| 126 | +&mdio { |
| 127 | + status = "okay"; |
| 128 | + pinctrl-0 = <&mdio_pins>; |
| 129 | + pinctrl-names = "default"; |
| 130 | + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; |
| 131 | + |
| 132 | + phy_0: ethernet-phy@0 { |
| 133 | + reg = <0>; |
| 134 | +// reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; |
| 135 | + }; |
| 136 | + |
| 137 | + phy_1: ethernet-phy@1 { |
| 138 | + reg = <1>; |
| 139 | + }; |
| 140 | + |
| 141 | + phy_2: ethernet-phy@2 { |
| 142 | + reg = <2>; |
| 143 | + }; |
| 144 | + |
| 145 | + phy_3: ethernet-phy@3 { |
| 146 | + reg = <3>; |
| 147 | + }; |
| 148 | + |
| 149 | + phy_4: ethernet-phy@4 { |
| 150 | + reg = <4>; |
| 151 | + }; |
| 152 | + |
| 153 | +}; |
| 154 | + |
| 155 | +&switch { |
| 156 | + status = "okay"; |
| 157 | + |
| 158 | + switch_lan_bmp = <0x1e>; |
| 159 | + switch_wan_bmp = <0x20>; |
| 160 | + switch_mac_mode = <0x00>; |
| 161 | + switch_mac_mode1 = <0xff>; |
| 162 | + switch_mac_mode2 = <0xff>; |
| 163 | + |
| 164 | + qcom,port_phyinfo { |
| 165 | + port@0 { |
| 166 | + port_id = <0x01>; |
| 167 | + phy_address = <0x00>; |
| 168 | + }; |
| 169 | + port@1 { |
| 170 | + port_id = <0x02>; |
| 171 | + phy_address = <0x01>; |
| 172 | + }; |
| 173 | + port@2 { |
| 174 | + port_id = <0x03>; |
| 175 | + phy_address = <0x02>; |
| 176 | + }; |
| 177 | + port@3 { |
| 178 | + port_id = <0x04>; |
| 179 | + phy_address = <0x03>; |
| 180 | + }; |
| 181 | + port@4 { |
| 182 | + port_id = <0x05>; |
| 183 | + phy_address = <0x04>; |
| 184 | + }; |
| 185 | + }; |
| 186 | +}; |
| 187 | + |
| 188 | +&qpic_bam { |
| 189 | + status = "okay"; |
| 190 | +}; |
| 191 | + |
| 192 | +&qpic_nand { |
| 193 | + status = "okay"; |
| 194 | + |
| 195 | + nand@0 { |
| 196 | + reg = <0>; |
| 197 | + |
| 198 | + nand-ecc-strength = <4>; |
| 199 | + nand-ecc-step-size = <512>; |
| 200 | + nand-bus-width = <8>; |
| 201 | + }; |
| 202 | +}; |
| 203 | + |
| 204 | +&wifi { |
| 205 | + status = "okay"; |
| 206 | +}; |
| 207 | + |
| 208 | + |
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