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Copy pathsun50i-a64-pine64+rg186-m2.dts
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sun50i-a64-pine64+rg186-m2.dts
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/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
/*
* Copyright (c) 2017-2018 Andreas Färber
*/
/dts-v1/;
/plugin/;
/ {
#address-cells = <1>;
#size-cells = <0>;
fragment@0 {
reg = <0>;
target-path = "/";
__overlay__ {
gpio_spi0: spi {
compatible = "spi-gpio";
mosi-gpios = <&pio 1 3 0>;
miso-gpios = <&pio 1 5 0>;
sck-gpios = <&pio 1 7 0>;
cs-gpios = <&pio 1 4 0>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
fragment@1 {
reg = <1>;
target-path = "/";
__overlay__ {
rg186_clk32m: rg186-clk32m {
compatible = "fixed-clock";
clock-frequency = <32000000>;
clock-output-names = "rg186-clk32m";
#clock-cells = <0>;
};
};
};
fragment@2 {
reg = <2>;
target = <&gpio_spi0>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
lora@0 {
compatible = "semtech,sx1301";
reg = <0>;
spi-max-frequency = <10000000>;
reset-gpios = <&r_pio 0 11 0>;
clocks = <&rg186_radio1>;
clock-names = "clk32m";
radio-spi {
#address-cells = <1>;
#size-cells = <0>;
lora@0 {
compatible = "semtech,sx1257";
reg = <0>;
clocks = <&rg186_clk32m>;
clock-names = "tcxo";
};
rg186_radio1: lora@1 {
compatible = "semtech,sx1257";
reg = <1>;
clocks = <&rg186_clk32m>;
clock-names = "tcxo";
clock-output-names = "rg186_clk32m";
#clock-cells = <0>;
};
};
};
};
};
};