Yosys 0.30

Yosys 0.29 .. Yosys 0.30

• New commands and options

  • Added "recover_names" pass to recover names post-mapping.

• Gowin support

  • Added remaining primitives blackboxes.

• Various

  • "show -colorattr" will now color the cells, wires, and
    connection arrows.
  • "show -viewer none" will not execute viewer.

Yosys 0.29

Yosys 0.28 .. Yosys 0.29

• New commands and options

  • Added "synthprop" pass for synthesizable properties.

• Verific support

  • Handle conditions on clocked concurrent assertions in unclocked
    procedural contexts.

• Verilog

  • Fix const eval of unbased unsized constants.
  • Handling of attributes for struct / union variables.

Yosys 0.28

Yosys 0.27 .. Yosys 0.28

• Verilog

  • Out of bounds checking for struct/union members.

• Verific support

  • Fix enum_values support and signed attribute values.

• ECP5 support

  • Added "synth_ecp5 -iopad"

• MachXO2 support

  • Added "synth_machxo2 -ccu2"

Yosys 0.27

Yosys 0.26 .. Yosys 0.27

• New commands and options

  • Added option "-make_assert" to "equiv_make" pass.
  • Added option "-coverenable" to "chformal" pass.

• Verilog

  • Resolve package types in interfaces.
  • Handle range offsets in packed arrays within packed structs.
  • Support for data and array queries on struct/union item expressions.

• GateMate support

  • Enable register initialization.

Yosys 0.26

Yosys 0.25 .. Yosys 0.26

• New commands and options

  • Added "bwmuxmap" pass to replace $bwmux cells with equivalent logic.
  • Added "xprop" experimental pass for formal x propagation.
  • Added "splitcells" pass to split up multi-bit cells.
  • Added "viz" pass to visualize data flow graph.
  • Added option "-make_cover" to "miter" pass.
  • Added option "-noparallelcase" to "write_verilog" pass.
  • Added option "-chain" to "insbuf" pass.
  • Added options "-hierarchy" and "-assume" to "formalff" pass.
  • Added options "-append" and "-summary" to "sim" pass.
  • Added option "-ywmap" to "write_btor" pass.
  • Added option "-ignore-self-reset" to "fsm_detect" pass.

• Verilog

  • Support for struct members of union type.
  • Support for struct member package types.

• Various

  • Added Yosys witness (.yw) cosimulation.
  • GCC 4.8 is deprecated, compiler with full C++11 support is

Yosys 0.25

Yosys 0.24 .. Yosys 0.25

• Verific support

  • Respect "noblackbox" attribute for modules.

• Various

  • Documentation is hosted at https://yosyshq.readthedocs.io/projects/yosys/en/latest/

Yosys 0.24

Yosys 0.23 .. Yosys 0.24

• New commands and options

  • Added option "-set-def-formal" to "sat" pass.
  • Added option "-s" to "tee" command.

• Verilog

  • Support for module-scoped identifiers referring to tasks and functions.
  • Support for arrays with swapped ranges within structs.

• Verific support

  • Support for importing verilog configurations per name.
  • "verific -set-XXXXX" commands are now able to set severity to all messages
    of certain type (errors, warnings, infos and comments)

• Various

  • TCL shell support (use "yosys -C")
  • Added FABulous eFPGA frontend

Yosys 0.23

Yosys 0.22 .. Yosys 0.23

• New commands and options

  • Added option "-cross" to "miter" pass.
  • Added option "-nocheck" to "equiv_opt" pass.

• Formal Verification

  • yosys-smtbmc: Added "--detect-loops" option for checking if states are
    unique in temporal induction counter examples.

• Verific support

  • Added support for reading Liberty files using Verific library.
    (Optinally enabled with ENABLE_VERIFIC_LIBERTY)
  • Added option "-cells" to "verific -import" enabling import of
    all cells from verific design.

• Various

  • MinGW build (Windows) plugin support.
  • Added YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging.
    Setting it to 1 causes abort() to be called when Yosys terminates with an
    error message.

Yosys 0.22

Yosys 0.21 .. Yosys 0.22

• Verific support

  • Added support for here-document for "verific" command (for reading
    source files).
  • Added support for reading EDIF files using Verific library.
    (Optinally enabled with ENABLE_VERIFIC_EDIF)

• Various

  • Added tech specific utilization to "stat" json.

Yosys 0.21

Yosys 0.20 .. Yosys 0.21

• New commands and options

  • Added "formalff" pass - transforms FFs for formal verification
  • Added option "-formal" to "memory_map" pass
  • Added option "-witness" to "rename" - give public names to all signals
    present in yosys witness traces
  • Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
    simulation output for a flattened design
  • Addded option "-scramble-name" to "rename" pass

• Formal Verification

  • Added $anyinit cell to directly represent FFs with an unconstrained
    initialization value. These can be generated by the new formalff pass.
  • New JSON based yosys witness format for formal verification traces.
  • yosys-smtbmc: Reading and writing of yosys witness traces.
  • write_smt2: Emit inline metadata to support yosys witness trace.
  • yosys-witness is a new tool to inspect and convert yosys witness traces.
  • write_aiger: Option to write a map file for yosys witness trace
    conversion.
  • yosys-witness: Conversion from and to AIGER witness traces.

• Verific support

  • Filename re-writing support for "verific" pass.

• Various

  • ABC performance improvements
  • Filename re-writing added for "show -lib".

• SmartFusion2 support

  • Added $alu support
  • Added SYSRESET and XTLOSC cells
  • Compatible now with LiberoSoc flow