@@ -149,7 +149,8 @@ void Mem::emit() {
149
149
wr_port_xlat.push_back (i);
150
150
for (auto &port : rd_ports) {
151
151
for (auto attr: port.attributes )
152
- cell->attributes .insert (attr);
152
+ if (!cell->has_attribute (attr.first ))
153
+ cell->attributes .insert (attr);
153
154
if (port.cell ) {
154
155
module->remove (port.cell );
155
156
port.cell = nullptr ;
@@ -213,7 +214,8 @@ void Mem::emit() {
213
214
cell->setPort (ID::RD_DATA, rd_data);
214
215
for (auto &port : wr_ports) {
215
216
for (auto attr: port.attributes )
216
- cell->attributes .insert (attr);
217
+ if (!cell->has_attribute (attr.first ))
218
+ cell->attributes .insert (attr);
217
219
if (port.cell ) {
218
220
module->remove (port.cell );
219
221
port.cell = nullptr ;
@@ -251,7 +253,8 @@ void Mem::emit() {
251
253
cell->setPort (ID::WR_DATA, wr_data);
252
254
for (auto &init : inits) {
253
255
for (auto attr: init.attributes )
254
- cell->attributes .insert (attr);
256
+ if (!cell->has_attribute (attr.first ))
257
+ cell->attributes .insert (attr);
255
258
if (init.cell ) {
256
259
module->remove (init.cell );
257
260
init.cell = nullptr ;
0 commit comments