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Merge pull request #4026 from uis246/fix-format
Fix printf formats
2 parents fac843f + 5902b28 commit 149bcd8

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3 files changed

+7
-6
lines changed

3 files changed

+7
-6
lines changed

frontends/ast/simplify.cc

+2-2
Original file line numberDiff line numberDiff line change
@@ -220,8 +220,8 @@ void AstNode::annotateTypedEnums(AstNode *template_node)
220220
log_assert(enum_item->children[1]->type == AST_RANGE);
221221
is_signed = enum_item->children[1]->is_signed;
222222
} else {
223-
log_error("enum_item children size==%lu, expected 1 or 2 for %s (%s)\n",
224-
enum_item->children.size(),
223+
log_error("enum_item children size==%zu, expected 1 or 2 for %s (%s)\n",
224+
(size_t) enum_item->children.size(),
225225
enum_item->str.c_str(), enum_node->str.c_str()
226226
);
227227
}

passes/memory/memory_libmap.cc

+3-3
Original file line numberDiff line numberDiff line change
@@ -690,7 +690,7 @@ bool apply_clock(MemConfig &cfg, const PortVariant &def, SigBit clk, bool clk_po
690690

691691
// Perform write port assignment, validating clock options as we go.
692692
void MemMapping::assign_wr_ports() {
693-
log_reject(stringf("Assigning write ports... (candidate configs: %lu)", cfgs.size()));
693+
log_reject(stringf("Assigning write ports... (candidate configs: %zu)", (size_t) cfgs.size()));
694694
for (auto &port: mem.wr_ports) {
695695
if (!port.clk_enable) {
696696
// Async write ports not supported.
@@ -739,7 +739,7 @@ void MemMapping::assign_wr_ports() {
739739

740740
// Perform read port assignment, validating clock and rden options as we go.
741741
void MemMapping::assign_rd_ports() {
742-
log_reject(stringf("Assigning read ports... (candidate configs: %lu)", cfgs.size()));
742+
log_reject(stringf("Assigning read ports... (candidate configs: %zu)", (size_t) cfgs.size()));
743743
for (int pidx = 0; pidx < GetSize(mem.rd_ports); pidx++) {
744744
auto &port = mem.rd_ports[pidx];
745745
MemConfigs new_cfgs;
@@ -900,7 +900,7 @@ void MemMapping::assign_rd_ports() {
900900

901901
// Validate transparency restrictions, determine where to add soft transparency logic.
902902
void MemMapping::handle_trans() {
903-
log_reject(stringf("Handling transparency... (candidate configs: %lu)", cfgs.size()));
903+
log_reject(stringf("Handling transparency... (candidate configs: %zu)", (size_t) cfgs.size()));
904904
if (mem.emulate_read_first_ok()) {
905905
MemConfigs new_cfgs;
906906
for (auto &cfg: cfgs) {

passes/sat/recover_names.cc

+2-1
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626

2727
#include <algorithm>
2828
#include <queue>
29+
#include <cinttypes>
2930

3031
USING_YOSYS_NAMESPACE
3132

@@ -623,7 +624,7 @@ struct RecoverNamesWorker {
623624
if (pop == 1 || pop == (8*sizeof(equiv_cls_t) - 1))
624625
continue;
625626

626-
log_debug("equivalence class: %016lx\n", cls.first);
627+
log_debug("equivalence class: %016" PRIx64 "\n", cls.first);
627628
const pool<IdBit> &gold_bits = cls2bits.at(cls.first).first;
628629
const pool<InvBit> &gate_bits = cls2bits.at(cls.first).second;
629630
if (gold_bits.empty() || gate_bits.empty())

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