@@ -690,7 +690,7 @@ bool apply_clock(MemConfig &cfg, const PortVariant &def, SigBit clk, bool clk_po
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// Perform write port assignment, validating clock options as we go.
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void MemMapping::assign_wr_ports () {
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- log_reject (stringf (" Assigning write ports... (candidate configs: %lu )" , cfgs.size ()));
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+ log_reject (stringf (" Assigning write ports... (candidate configs: %zu )" , ( size_t ) cfgs.size ()));
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for (auto &port: mem.wr_ports ) {
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if (!port.clk_enable ) {
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// Async write ports not supported.
@@ -739,7 +739,7 @@ void MemMapping::assign_wr_ports() {
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// Perform read port assignment, validating clock and rden options as we go.
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void MemMapping::assign_rd_ports () {
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- log_reject (stringf (" Assigning read ports... (candidate configs: %lu )" , cfgs.size ()));
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+ log_reject (stringf (" Assigning read ports... (candidate configs: %zu )" , ( size_t ) cfgs.size ()));
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for (int pidx = 0 ; pidx < GetSize (mem.rd_ports ); pidx++) {
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auto &port = mem.rd_ports [pidx];
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MemConfigs new_cfgs;
@@ -900,7 +900,7 @@ void MemMapping::assign_rd_ports() {
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// Validate transparency restrictions, determine where to add soft transparency logic.
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void MemMapping::handle_trans () {
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- log_reject (stringf (" Handling transparency... (candidate configs: %lu )" , cfgs.size ()));
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+ log_reject (stringf (" Handling transparency... (candidate configs: %zu )" , ( size_t ) cfgs.size ()));
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if (mem.emulate_read_first_ok ()) {
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MemConfigs new_cfgs;
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for (auto &cfg: cfgs) {
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