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SingleCycleProcessor.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
# Date created = 01:02:46 September 23, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# SingleCycleProcessor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE40F29C6
set_global_assignment -name TOP_LEVEL_ENTITY execute
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:02:46 SEPTEMBER 23, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name SYSTEMVERILOG_FILE flopr.sv
set_global_assignment -name SYSTEMVERILOG_FILE flopr_tb.sv
set_global_assignment -name SOURCE_FILE testvectors/10x64bit_numbers_hex.tv
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH maindec_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME flopr_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id flopr_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME flopr_tb -section_id flopr_tb
set_global_assignment -name SYSTEMVERILOG_FILE signext.sv
set_global_assignment -name SYSTEMVERILOG_FILE signext_tb.sv
set_global_assignment -name EDA_TEST_BENCH_NAME signext_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id signext_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME signext_tb -section_id signext_tb
set_global_assignment -name SYSTEMVERILOG_FILE alu.sv
set_global_assignment -name SYSTEMVERILOG_FILE alu_tb.sv
set_global_assignment -name EDA_TEST_BENCH_NAME alu_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id alu_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME alu_tb -section_id alu_tb
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 780
set_global_assignment -name SYSTEMVERILOG_FILE imem.sv
set_global_assignment -name SYSTEMVERILOG_FILE imem_tb.sv
set_global_assignment -name EDA_TEST_BENCH_NAME imem_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id imem_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME imem_tb -section_id imem_tb
set_global_assignment -name SYSTEMVERILOG_FILE regfile_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE regfile.sv
set_global_assignment -name EDA_TEST_BENCH_NAME regfile_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id regfile_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME regfile_tb -section_id regfile_tb
set_global_assignment -name SYSTEMVERILOG_FILE maindec.sv
set_global_assignment -name SYSTEMVERILOG_FILE maindec_tb.sv
set_global_assignment -name EDA_TEST_BENCH_FILE flopr_tb.sv -section_id flopr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE signext_tb.sv -section_id signext_tb
set_global_assignment -name EDA_TEST_BENCH_FILE alu_tb.sv -section_id alu_tb
set_global_assignment -name EDA_TEST_BENCH_FILE imem_tb.sv -section_id imem_tb
set_global_assignment -name EDA_TEST_BENCH_FILE regfile_tb.sv -section_id regfile_tb
set_global_assignment -name EDA_TEST_BENCH_NAME maindec_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id maindec_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME maindec_tb -section_id maindec_tb
set_global_assignment -name EDA_TEST_BENCH_FILE maindec_tb.sv -section_id maindec_tb
set_global_assignment -name SYSTEMVERILOG_FILE adder.sv
set_global_assignment -name SYSTEMVERILOG_FILE mux2.sv
set_global_assignment -name SYSTEMVERILOG_FILE sl2.sv
set_global_assignment -name SYSTEMVERILOG_FILE fetch.sv
set_global_assignment -name SYSTEMVERILOG_FILE execute.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top