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main.c
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#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <string.h>
#include <signal.h>
#include <time.h>
#include <SDL2/SDL.h>
#include <stdarg.h>
#ifdef __EMSCRIPTEN__
#include <emscripten.h>
#endif
#include "ssu.h"
#include "eeprom.h"
#include "lcd.h"
#include "accel.h"
#include "rtc.h"
#include "interrupts.h"
#include "main.h"
// TODO: internal states for:
// MOV.W Rs,@–ERd
// POP.W Rn
#define STATES(si, sj, sk, sl, sm, sn) ctx->i = si; ctx->j = sj; ctx->k = sk; ctx->l = sl; ctx->m = sm; ctx->n = sn;
#ifdef PKW_DEBUG
__attribute__ ((unused)) static void debug_internal(const char *format, ...) {
if (1) {
va_list args;
va_start(args, format);
vfprintf(stdout, format, args);
va_end(args);
fflush(stdout);
}
}
#endif
//#define PKW_DEBUG
#ifdef PKW_DEBUG
#define debug(...) debug_internal(__VA_ARGS__)
#else
#define debug(...)
#endif
#define UNIMPL(...)
//debug_internal(__VA_ARGS__)
#ifdef _MSC_VER
#define likely(x) (x)
#define unlikely(x) (x)
#else
#define likely(x) __builtin_expect((x),1)
#define unlikely(x) __builtin_expect((x),0)
#endif
#define SCREEN_WIDTH 96
#define SCREEN_HEIGHT 64
#define GFX_SCALE 5
#define WINDOW_WIDTH (SCREEN_WIDTH*GFX_SCALE)
#define WINDOW_HEIGHT (SCREEN_HEIGHT*GFX_SCALE)
#define WINDOW_TITLE "Powar - Pokéwalker emulator"
static SDL_Window* gWindow = NULL;
static SDL_Renderer* renderer;
static SDL_Texture* sdlTexture;
enum REGISTER_TYPE {
REGTYPE_DBW8_ACCS2,
REGTYPE_DBW8_ACCS3,
REGTYPE_DBW16_ACCS2
};
typedef struct mm_reg {
char *name;
char *desc;
uint16_t addr;
enum REGISTER_TYPE type;
union {
uint8_t (*read8)(uintptr_t);
uint16_t (*read16)(uintptr_t);
};
union {
void (*write8)(uintptr_t, uint8_t);
void (*write16)(uintptr_t, uint16_t);
};
int ctx_offset;
} mm_reg_t;
#define MM_REG8( _name, _addr, _type, _read, _write, _desc, _ctx_off) { .name = _name, .desc = _desc, .addr = _addr, .type = _type, .read8 = (uint8_t (*)(uintptr_t)) _read, .write8 = (void (*)(uintptr_t, uint8_t)) _write, .ctx_offset = _ctx_off}
#define MM_REG16(_name, _addr, _type, _read, _write, _desc, _ctx_off) { .name = _name, .desc = _desc, .addr = _addr, .type = _type, .read16 = (uint16_t (*)(uintptr_t)) _read, .write16 = (void (*)(uintptr_t, uint16_t)) _write, .ctx_offset = _ctx_off}
//MM_REG("UNK_REG", 0xF088, REGTYPE_DBW8_ACCS2, NULL, NULL, "Unknown IO Reg (TODO?)", 0),
static uint8_t io2_get_pdr1(pw_context_t *ctx);
static void io2_set_pdr1(pw_context_t *ctx, uint8_t val);
static uint8_t io2_get_pdr9(pw_context_t *ctx);
static void io2_set_pdr9(pw_context_t *ctx, uint8_t val);
static uint8_t sci_get_rdr(pw_context_t *ctx) {
return 0xFC ^ 0xAA;// ctx->rdr;
}
static void sci_set_tdr(pw_context_t *ctx, uint8_t val) {
ctx->tdr = val;
}
static uint8_t sci_get_tdr(pw_context_t *ctx) {
return ctx->tdr;
}
#define SCI_SMR_COM_BIT 7
static void sci_set_smr(pw_context_t *ctx, uint8_t val) {
ctx->smr = val;
printf("[SCI SMR] COM:%d\n",
!!(ctx->smr & (1 << SCI_SMR_COM_BIT))
);
}
static uint8_t sci_get_smr(pw_context_t *ctx) {
return ctx->smr;
}
#define SCI_SCR_TIE_BIT 7
#define SCI_SCR_RIE_BIT 6
#define SCI_SCR_TE_BIT 5
#define SCI_SCR_RE_BIT 4
#define SCI_SCR_MPIE_BIT 3
#define SCI_SCR_TEIE_BIT 2
#define SCI_SCR_CKE_MASK 3
static void sci_set_scr(pw_context_t *ctx, uint8_t val) {
ctx->scr = val;
printf("[SCI SCR] TIE:%d RIE:%d TE:%d RE:%d MPIE:%d TEIE:%d CKE:%d\n",
!!(ctx->scr & (1 << SCI_SCR_TIE_BIT)),
!!(ctx->scr & (1 << SCI_SCR_RIE_BIT)),
!!(ctx->scr & (1 << SCI_SCR_TE_BIT)),
!!(ctx->scr & (1 << SCI_SCR_RE_BIT)),
!!(ctx->scr & (1 << SCI_SCR_MPIE_BIT)),
!!(ctx->scr & (1 << SCI_SCR_TEIE_BIT)),
(ctx->scr & SCI_SCR_CKE_MASK)
);
}
static uint8_t sci_get_scr(pw_context_t *ctx) {
return ctx->scr;
}
static void sci_set_ssr(pw_context_t *ctx, uint8_t val) {
ctx->ssr &= val;
//printf("[SCI SSR] %x\n", val);
}
static uint8_t sci_get_ssr(pw_context_t *ctx) {
return 0xBF; //ctx->ssr;
}
#define SCI_IRCR_IRE_BIT 7
#define SCI_IRCR_IRCKS_MASK 0x70
#define SCI_IRCR_IRCKS_SHIFT 4
#define SCI_IRCR_MASK 0xF0
static uint8_t sci_get_ircr(pw_context_t *ctx) {
return ctx->ircr;
}
static void sci_set_ircr(pw_context_t *ctx, uint8_t val) {
ctx->ircr = val & SCI_IRCR_MASK;
printf("[SCI IRCR] IRE:%d IRCKS:%d\n",
!!(ctx->ircr & (1 << SCI_IRCR_IRE_BIT)),
((ctx->ircr & SCI_IRCR_IRCKS_MASK) >> SCI_IRCR_IRCKS_SHIFT)
);
}
static uint8_t sci_get_semr(pw_context_t *ctx) {
return ctx->semr;
}
#define SCI_SEMR_MASK 8
#define SCI_SEMR_ABCS_BIT 3
static void sci_set_semr(pw_context_t *ctx, uint8_t val) {
ctx->semr = val & SCI_SEMR_MASK;
printf("[SCI SEMR] ABCS:%d\n",
!!(ctx->semr & (1 << SCI_SEMR_ABCS_BIT))
);
}
static uint16_t adc_get_addr(pw_context_t *ctx) {
return 0xFFC0;
}
static uint8_t sys_get_osccr(pw_context_t *ctx) {
// OSCF is determined by E7_2 pin
//printf("[SYS OSCCR] READ\n");
return ctx->osccr;
}
static void sys_set_osccr(pw_context_t *ctx, uint8_t val) {
ctx->osccr = val;
// printf("[SYS OSCCR] SUBSTP:%d RFCUT:%d SUBSEL:%d\n",
// !!(ctx->osccr & (1 << 7)),
// !!(ctx->osccr & (1 << 6)),
// !!(ctx->osccr & (1 << 5))
// );
}
static uint8_t sys_get_pfcr(pw_context_t *ctx) {
return ctx->pfcr;
}
static void sys_set_pfcr(pw_context_t *ctx, uint8_t val) {
ctx->pfcr = val;
// printf("[SYS PFCR] SSUS:%d IRQ1:%d IRQ0:%d\n",
// !!(ctx->pfcr & (1 << 4)),
// ((ctx->pfcr >> 2) & 3),
// (ctx->pfcr & 3)
// );
}
#define SYS_SYSCR1_SSBY_BIT 7
#define SYS_SYSCR1_STS_SHIFT 4
#define SYS_SYSCR1_STS_MASK 7
#define SYS_SYSCR1_LSON_BIT 3
#define SYS_SYSCR1_TMA3_BIT 2
#define SYS_SYSCR1_MA_MASK 3
static uint8_t sys_get_syscr1(pw_context_t *ctx) {
return ctx->syscr1;
}
static void sys_set_syscr1(pw_context_t *ctx, uint8_t val) {
ctx->syscr1 = val;
// printf("[SYS SYSCR1] SSBY:%d STS:%d LSON:%d TMA3:%d MA:%d\n",
// !!(ctx->syscr1 & (1 << SYS_SYSCR1_SSBY_BIT)),
// ((ctx->syscr1 >> SYS_SYSCR1_STS_SHIFT) & SYS_SYSCR1_STS_MASK),
// !!(ctx->syscr1 & (1 << SYS_SYSCR1_LSON_BIT)),
// !!(ctx->syscr1 & (1 << SYS_SYSCR1_TMA3_BIT)),
// (ctx->syscr1 & SYS_SYSCR1_MA_MASK)
// );
}
#define SYS_SYSCR2_NESEL_BIT 4
#define SYS_SYSCR2_DTON_BIT 3
#define SYS_SYSCR2_MSON_BIT 2
#define SYS_SYSCR2_SA_MASK 3
static uint8_t sys_get_syscr2(pw_context_t *ctx) {
return ctx->syscr2;
}
static void sys_set_syscr2(pw_context_t *ctx, uint8_t val) {
ctx->syscr2 = val;
// printf("[SYS SYSCR2] NESEL:%d DTON:%d MSON:%d SA:%d\n",
// !!(ctx->syscr2 & (1 << SYS_SYSCR2_NESEL_BIT)),
// !!(ctx->syscr2 & (1 << SYS_SYSCR2_DTON_BIT)),
// !!(ctx->syscr2 & (1 << SYS_SYSCR2_MSON_BIT)),
// (ctx->syscr2 & SYS_SYSCR2_SA_MASK)
// );
}
static uint8_t sys_get_ckstpr1(pw_context_t *ctx) {
return ctx->ckstpr1;
}
static void sys_set_ckstpr1(pw_context_t *ctx, uint8_t val) {
ctx->ckstpr1 = val;
// printf("[SYS CKSTPR1] S3CKSTP:%d ADCKSTP:%d TB1CKSTP:%d FROMCKSTP:%d RTCCKSTP:%d\n",
// !!(ctx->ckstpr1 & (1 << 6)),
// !!(ctx->ckstpr1 & (1 << 4)),
// !!(ctx->ckstpr1 & (1 << 2)),
// !!(ctx->ckstpr1 & (1 << 1)),
// !!(ctx->ckstpr1 & 1)
// );
}
static uint8_t sys_get_ckstpr2(pw_context_t *ctx) {
return ctx->ckstpr2;
}
static void sys_set_ckstpr2(pw_context_t *ctx, uint8_t val) {
ctx->ckstpr2 = val;
// printf("[SYS CKSTPR2] TWCKSTP:%d IICCKSTP:%d SSUCKSTP:%d AECCKSTP:%d WDCKSTP:%d COMPCKSTP:%d\n",
// !!(ctx->ckstpr2 & (1 << 6)),
// !!(ctx->ckstpr2 & (1 << 5)),
// !!(ctx->ckstpr2 & (1 << 4)),
// !!(ctx->ckstpr2 & (1 << 3)),
// !!(ctx->ckstpr2 & (1 << 2)),
// !!(ctx->ckstpr2 & (1 << 1))
// );
}
const char *exec_modes[] = {
"Active (high-speed) mode",
"Active (medium-speed) mode",
"Subactive mode",
"Sleep (high-speed) mode",
"Sleep (medium-speed) mode",
"Subsleep mode",
"Standby mode",
"Watch mode"
};
void sleep(pw_context_t *ctx) {
return;
//exec_mode_t next = -1;
//int lson = ctx->syscr1 & (1 << SYS_SYSCR1_LSON_BIT);
// int mson = ctx->syscr2 & (1 << SYS_SYSCR2_MSON_BIT);
// int ssby = ctx->syscr1 & (1 << SYS_SYSCR1_SSBY_BIT);
// int tma3 = ctx->syscr1 & (1 << SYS_SYSCR1_TMA3_BIT);
// int dton = ctx->syscr2 & (1 << SYS_SYSCR2_DTON_BIT);
// LSON (SYSCR1:3)
// Selects the system clock (φ) or subclock (φSUB) as the
// CPU operating clock when watch mode is cleared.
// 0: The CPU operates on the system clock (φ)
// 1: The CPU operates on the subclock (φSUB)
// MSON (SYSCR2:2)
// After standby, watch, or sleep mode is cleared, this bit
// selects active (high-speed) or active (medium-speed) mode.
// 0: Operation in active (high-speed) mode
// 1: Operation in active (medium-speed) mode
// SSBY (SYSCR1:7)
// Selects the mode to transit after the execution of the
// SLEEP instruction.
// 0: A transition is made to sleep mode or subsleep mode.
// 1: A transition is made to standby mode or watch mode.
// TMA3 (SYSCR1:2)
// Selects the mode to which the transition is made after
// the SLEEP instruction is executed with bits SSBY and
// LSON in SYSCR1 and bits DTON and MSON in SYSCR2.
// DTON (SYSCR2:3)
// Selects the mode to which the transition is made after
// the SLEEP instruction is executed with bits SSBY,
// TMA3, and LSON in SYSCR1 and bit MSON in SYSCR2.
// ACTIVE HIGH =(a)==> SLEEP HIGH
// ACTIVE MED =(a)==> SLEEP HIGH
// ACTIVE HIGH =(b)==> SLEEP MED
// ACTIVE MED =(b)==> SLEEP MED
// SUBACTIVE =(c)==> SUBSLEEP
// ACTIVE HIGH =(d)==> STANDBY
// ACTIVE MED =(d)==> STANDBY
// ACTIVE HIGH =(e)==> WATCH
// ACTIVE MED =(e)==> WATCH
// SUBACTIVE =(e)==> WATCH
// ACTIVE MED =(f)==> ACTIVE HIGH
// ACTIVE HIGH =(g)==> ACTIVE MED
// SUBACTIVE =(h)==> ACTIVE MED
// ACTIVE HIGH =(i1)=> SUBACTIVE
// ACTIVE MED =(i2)=> SUBACTIVE
// SUBACTIVE =(j)==> ACTIVE HIGH
// LSON MSON SSBY TMA3 DTON
// a : 0 0 0 x 0
// b : 0 1 0 x 0
// c : 1 x 0 1 0
// d : 0 x 1 0 0
// e : x x 1 1 0
// f : 0 0 0 x 1
// g : 0 1 0 x 1
// h : 0 1 1 1 1
// i1: 1 x 1 1 1
// i2: 1 1 1 1 1
// j : 0 0 1 1 1
// switch (ctx->mode) {
// case MODE_ACTIVE_HIGH: // a,b,d,e,g,i1
// if (ssby) { // d,e,i1
// if (tma3) { // e, i1
// if (dton) { // i1
// next = MODE_SUBACTIVE;
// } else { // e
// next = MODE_WATCH;
// }
// } else { // d
// next = MODE_STANDBY;
// }
// } else { // a,b,g
// if (mson) { // b,g
// if (dton) { // g
// next = MODE_ACTIVE_MED;
// } else { // b
// next = MODE_SLEEP_MED;
// }
// } else { // a
// next = MODE_SLEEP_HIGH;
// }
// }
// break;
// case MODE_ACTIVE_MED: // a,b,d,e,f,i2
// if (ssby) { // d,e,i1
// if (tma3) { // e, i1
// if (dton) { // i1
// next = MODE_SUBACTIVE;
// } else { // e
// next = MODE_WATCH;
// }
// } else { // d
// next = MODE_STANDBY;
// }
// } else { // a,b,f
// if (mson) { // b
// next = MODE_SLEEP_MED;
// } else { // a,f
// if (dton) { // f
// next = MODE_ACTIVE_HIGH;
// } else { // a
// next = MODE_SLEEP_HIGH;
// }
// }
// }
// break;
// case MODE_SUBACTIVE: // c,e,h,j
// if (dton) { // h,j
// if (mson) { // h
// next = MODE_ACTIVE_MED;
// } else { // j
// next = MODE_ACTIVE_HIGH;
// }
// } else { // c,e
// if (ssby) { // e
// next = MODE_WATCH;
// } else { // c
// next = MODE_SUBSLEEP;
// }
// }
// break;
// default:
// }
// printf("SLEEP %x LSON:%d MSON:%d SSBY:%d TMA3:%d DTON:%d\n[%s] => [%s]\n",
// ctx->ip,
// !!lson, !!mson, !!ssby, !!tma3, !!dton,
// exec_modes[ctx->mode], exec_modes[next]);
}
static uint8_t int_get_iegr(pw_context_t *ctx) {
return ctx->iegr;
}
static void int_set_iegr(pw_context_t *ctx, uint8_t val) {
ctx->iegr = val;
}
static uint8_t int_get_ienr1(pw_context_t *ctx) {
return ctx->ienr1;
}
static void int_set_ienr1(pw_context_t *ctx, uint8_t val) {
ctx->ienr1 = val;
}
static uint8_t int_get_ienr2(pw_context_t *ctx) {
return ctx->ienr2;
}
static void int_set_ienr2(pw_context_t *ctx, uint8_t val) {
ctx->ienr2 = val;
}
static uint8_t int_get_irr1(pw_context_t *ctx) {
return ctx->irr1;
}
static void int_set_irr1(pw_context_t *ctx, uint8_t val) {
ctx->irr1 = val;
}
static uint8_t int_get_irr2(pw_context_t *ctx) {
return ctx->irr2;
}
static void int_set_irr2(pw_context_t *ctx, uint8_t val) {
ctx->irr2 = val;
}
// Timer B1
static void tb1_set_tmb1(pw_context_t *ctx, uint8_t val) {
ctx->tmb1 = val;
}
static uint8_t tb1_get_tmb1(pw_context_t *ctx) {
return ctx->tmb1;
}
static uint8_t tb1_get_tcb1(pw_context_t *ctx) {
return ctx->tmb1;
}
static void tb1_set_tlb1(pw_context_t *ctx, uint8_t val) {
ctx->tlb1 = val;
}
// Timer W
#define TMRW_TMRW_CTS_BIT 7
#define TMRW_TMRW_BUFEB_BIT 5
#define TMRW_TMRW_BUFEA_BIT 4
#define TMRW_TMRW_PWMD_BIT 2
#define TMRW_TMRW_PWMC_BIT 1
#define TMRW_TMRW_PWMB_BIT 0
#define TMRW_TMRW_MASK 0xB7
static uint8_t tmrw_get_tmrw(pw_context_t *ctx) {
return ctx->tmrw;
}
static void tmrw_set_tmrw(pw_context_t *ctx, uint8_t val) {
ctx->tmrw = val & TMRW_TMRW_MASK;
// printf("[TMRW TMRW] CTS:%d BUFEB:%d BUFEA:%d PWMD:%d PWMC:%d PWMB:%d\n",
// !!(ctx->tmrw & (1 << TMRW_TMRW_CTS_BIT)),
// !!(ctx->tmrw & (1 << TMRW_TMRW_BUFEB_BIT)),
// !!(ctx->tmrw & (1 << TMRW_TMRW_BUFEA_BIT)),
// !!(ctx->tmrw & (1 << TMRW_TMRW_PWMD_BIT)),
// !!(ctx->tmrw & (1 << TMRW_TMRW_PWMC_BIT)),
// (ctx->tmrw & (1 << TMRW_TMRW_PWMB_BIT))
// );
}
#define TMRW_TCRW_CCLR_BIT 7
#define TMRW_TCRW_CKS_MASK 0x70
#define TMRW_TCRW_CKS_SHIFT 4
#define TMRW_TCRW_TOD_BIT 3
#define TMRW_TCRW_TOC_BIT 2
#define TMRW_TCRW_TOB_BIT 1
#define TMRW_TCRW_TOA_BIT 0
static uint8_t tmrw_get_tcrw(pw_context_t *ctx) {
return ctx->tcrw;
}
static void tmrw_set_tcrw(pw_context_t *ctx, uint8_t val) {
ctx->tcrw = val;
// printf("[TMRW TCRW] CCLR:%d CKS:%d TOD:%d TOC:%d TOB:%d TOA:%d\n",
// !!(ctx->tcrw & (1 << TMRW_TCRW_CCLR_BIT)),
// (ctx->tcrw & TMRW_TCRW_CKS_MASK) >> TMRW_TCRW_CKS_SHIFT,
// !!(ctx->tcrw & (1 << TMRW_TCRW_TOD_BIT)),
// !!(ctx->tcrw & (1 << TMRW_TCRW_TOC_BIT)),
// !!(ctx->tcrw & (1 << TMRW_TCRW_TOB_BIT)),
// (ctx->tcrw & (1 << TMRW_TCRW_TOA_BIT))
// );
}
#define TMRW_TIERW_OVIE_BIT 7
#define TMRW_TIERW_IMIED_BIT 3
#define TMRW_TIERW_IMIEC_BIT 2
#define TMRW_TIERW_IMIEB_BIT 1
#define TMRW_TIERW_IMIEA_BIT 0
#define TMRW_TIERW_MASK 0x8F
static uint8_t tmrw_get_tierw(pw_context_t *ctx) {
return ctx->tierw;
}
static void tmrw_set_tierw(pw_context_t *ctx, uint8_t val) {
ctx->tierw = val & TMRW_TIERW_MASK;
// printf("[TMRW TIERW] OVIE:%d IMIED:%d IMIEC:%d IMIEB:%d IMIEA:%d\n",
// !!(ctx->tierw & (1 << TMRW_TIERW_OVIE_BIT)),
// !!(ctx->tierw & (1 << TMRW_TIERW_IMIED_BIT)),
// !!(ctx->tierw & (1 << TMRW_TIERW_IMIEC_BIT)),
// !!(ctx->tierw & (1 << TMRW_TIERW_IMIEB_BIT)),
// (ctx->tierw & (1 << TMRW_TIERW_IMIEA_BIT))
// );
}
#define TMRW_TSRW_OVF_BIT 7
#define TMRW_TSRW_IMFD_BIT 3
#define TMRW_TSRW_IMFC_BIT 2
#define TMRW_TSRW_IMFB_BIT 1
#define TMRW_TSRW_IMFA_BIT 0
#define TMRW_TSRW_MASK 0x8F
static uint8_t tmrw_get_tsrw(pw_context_t *ctx) {
return ctx->tsrw;
}
static void tmrw_set_tsrw(pw_context_t *ctx, uint8_t val) {
ctx->tsrw &= val | ~TMRW_TSRW_MASK;
// printf("[TMRW TSRW] OVF:%d IMFD:%d IMFC:%d IMFB:%d IMFA:%d\n",
// !!(ctx->tsrw & (1 << TMRW_TSRW_OVF_BIT)),
// !!(ctx->tsrw & (1 << TMRW_TSRW_IMFD_BIT)),
// !!(ctx->tsrw & (1 << TMRW_TSRW_IMFC_BIT)),
// !!(ctx->tsrw & (1 << TMRW_TSRW_IMFB_BIT)),
// (ctx->tsrw & (1 << TMRW_TSRW_IMFA_BIT))
// );
}
#define TMRW_TIOR0_IOB_MASK 0x70
#define TMRW_TIOR0_IOB_SHIFT 4
#define TMRW_TIOR0_IOA_MASK 7
#define TMRW_TIOR0_IOA_SHIFT 0
#define TMRW_TIOR0_MASK 0x77
static uint8_t tmrw_get_tior0(pw_context_t *ctx) {
return ctx->tior0;
}
static void tmrw_set_tior0(pw_context_t *ctx, uint8_t val) {
ctx->tior0 = val & TMRW_TIOR0_MASK;
// printf("[TMRW TIOR0] IOB:%d IOA:%d\n",
// (ctx->tior0 & TMRW_TIOR0_IOB_MASK) >> TMRW_TIOR0_IOB_SHIFT,
// (ctx->tior0 & TMRW_TIOR0_IOA_MASK) >> TMRW_TIOR0_IOA_SHIFT
// );
}
#define TMRW_TIOR1_IOD_MASK 0x70
#define TMRW_TIOR1_IOD_SHIFT 4
#define TMRW_TIOR1_IOC_MASK 7
#define TMRW_TIOR1_IOC_SHIFT 0
#define TMRW_TIOR1_MASK 0x77
static uint8_t tmrw_get_tior1(pw_context_t *ctx) {
return ctx->tior1;
}
static void tmrw_set_tior1(pw_context_t *ctx, uint8_t val) {
ctx->tior1 = val & TMRW_TIOR1_MASK;
// printf("[TMRW TIOR1] IOD:%d IOC:%d\n",
// (ctx->tior1 & TMRW_TIOR1_IOD_MASK) >> TMRW_TIOR1_IOD_SHIFT,
// (ctx->tior1 & TMRW_TIOR1_IOC_MASK) >> TMRW_TIOR1_IOC_SHIFT
// );
}
static uint16_t tmrw_get_tcnt(pw_context_t *ctx) {
return ctx->tcnt;
}
static void tmrw_set_tcnt(pw_context_t *ctx, uint16_t val) {
ctx->tcnt = val;
// printf("[TMRW TCNT] %x\n", val);
}
static uint16_t tmrw_get_gra(pw_context_t *ctx) {
return ctx->gra;
}
static void tmrw_set_gra(pw_context_t *ctx, uint16_t val) {
ctx->gra = val;
// printf("[TMRW GRA] %x @ %x\n", val, ctx->ip);
}
static uint16_t tmrw_get_grb(pw_context_t *ctx) {
return ctx->grb;
}
static void tmrw_set_grb(pw_context_t *ctx, uint16_t val) {
ctx->grb = val;
// printf("[TMRW GRB] %x\n", val);
}
static uint16_t tmrw_get_grc(pw_context_t *ctx) {
return ctx->grc;
}
static void tmrw_set_grc(pw_context_t *ctx, uint16_t val) {
ctx->grc = val;
// printf("[TMRW GRC] %x\n", val);
}
static uint16_t tmrw_get_grd(pw_context_t *ctx) {
return ctx->grd;
}
static void tmrw_set_grd(pw_context_t *ctx, uint16_t val) {
ctx->grd = val;
// printf("[TMRW GRD] %x\n", val);
}
mm_reg_t mm_registers[] = {
MM_REG8("FLMCR1", 0xF020, REGTYPE_DBW8_ACCS2, NULL, NULL, "Flash memory control register 1", 0),
MM_REG8("FLMCR2", 0xF021, REGTYPE_DBW8_ACCS2, NULL, NULL, "Flash memory control register 2", 0),
MM_REG8("FLPWCR", 0xF022, REGTYPE_DBW8_ACCS2, NULL, NULL, "Flash memory power control register", 0),
MM_REG8("EBR1", 0xF023, REGTYPE_DBW8_ACCS2, NULL, NULL, "Erase block register 1", 0),
MM_REG8("FENR", 0xF02B, REGTYPE_DBW8_ACCS2, NULL, NULL, "Flash memory enable register", 0),
MM_REG8("RTCFLG", 0xF067, REGTYPE_DBW8_ACCS2, rtc_get_flg, rtc_set_flg, "RTC interrupt flag register", offsetof(pw_context_t, rtc)),
MM_REG8("RSECDR", 0xF068, REGTYPE_DBW8_ACCS2, rtc_get_secdr, rtc_set_secdr, "Second data register/free running counter data register", offsetof(pw_context_t, rtc)),
MM_REG8("RMINDR", 0xF069, REGTYPE_DBW8_ACCS2, rtc_get_mindr, rtc_set_mindr, "Minute data register", offsetof(pw_context_t, rtc)),
MM_REG8("RHRDR", 0xF06A, REGTYPE_DBW8_ACCS2, rtc_get_hrdr, rtc_set_hrdr, "Hour data register", offsetof(pw_context_t, rtc)),
MM_REG8("RWKDR", 0xF06B, REGTYPE_DBW8_ACCS2, NULL, NULL, "Day-of-week data register", offsetof(pw_context_t, rtc)),
MM_REG8("RTCCR1", 0xF06C, REGTYPE_DBW8_ACCS2, rtc_get_cr1, rtc_set_cr1, "RTC control register 1", offsetof(pw_context_t, rtc)),
MM_REG8("RTCCR2", 0xF06D, REGTYPE_DBW8_ACCS2, rtc_get_cr2, rtc_set_cr2, "RTC control register 2", offsetof(pw_context_t, rtc)),
MM_REG8("RTCCSR", 0xF06F, REGTYPE_DBW8_ACCS2, NULL, NULL, "Clock source select register", offsetof(pw_context_t, rtc)),
MM_REG8("ICCR1", 0xF078, REGTYPE_DBW8_ACCS2, NULL, NULL, "I2C bus control register 1", 0),
MM_REG8("ICCR2", 0xF079, REGTYPE_DBW8_ACCS2, NULL, NULL, "I2C bus control register 2", 0),
MM_REG8("ICMR", 0xF07A, REGTYPE_DBW8_ACCS2, NULL, NULL, "I2C bus mode register", 0),
MM_REG8("ICIER", 0xF07B, REGTYPE_DBW8_ACCS2, NULL, NULL, "I2C bus interrupt enable register", 0),
MM_REG8("ICSR", 0xF07C, REGTYPE_DBW8_ACCS2, NULL, NULL, "I2C bus status register", 0),
MM_REG8("SAR", 0xF07D, REGTYPE_DBW8_ACCS2, NULL, NULL, "Slave address register", 0),
MM_REG8("ICDRT", 0xF07E, REGTYPE_DBW8_ACCS2, NULL, NULL, "I2C bus transmit data register", 0),
MM_REG8("ICDRR", 0xF07F, REGTYPE_DBW8_ACCS2, NULL, NULL, "I2C bus receive data register", 0),
MM_REG8("PFCR", 0xF085, REGTYPE_DBW8_ACCS2, sys_get_pfcr, sys_set_pfcr, "Port function control register", 0),
MM_REG8("PUCR8", 0xF086, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port pull-up control register 8", 0),
MM_REG8("PUCR9", 0xF087, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port pull-up control register 9", 0),
MM_REG8("UNK_REG", 0xF088, REGTYPE_DBW8_ACCS2, NULL, NULL, "Unknown IO Reg (TODO?)", 0),
MM_REG8("PODR9", 0xF08C, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port open-drain control register 9", 0),
MM_REG8("TMB1", 0xF0D0, REGTYPE_DBW8_ACCS2, tb1_get_tmb1, tb1_set_tmb1, "Timer mode register B1", 0),
MM_REG8("TCB1 (R)/TLB1 (W)", 0xF0D1, REGTYPE_DBW8_ACCS2, tb1_get_tcb1, tb1_set_tlb1, "Timer counter B1/Timer load register B1", 0),
MM_REG8("CMCR0", 0xF0DC, REGTYPE_DBW8_ACCS2, NULL, NULL, "Compare control register 0", 0),
MM_REG8("CMCR1", 0xF0DD, REGTYPE_DBW8_ACCS2, NULL, NULL, "Compare control register 1", 0),
MM_REG8("CMDR", 0xF0DE, REGTYPE_DBW8_ACCS2, NULL, NULL, "Compare data register", 0),
MM_REG8("SSCRH", 0xF0E0, REGTYPE_DBW8_ACCS3, ssu_get_sscrh, ssu_set_sscrh, "SS control register H", offsetof(pw_context_t, ssu)),
MM_REG8("SSCRL", 0xF0E1, REGTYPE_DBW8_ACCS3, ssu_get_sscrl, ssu_set_sscrl, "SS control register L", offsetof(pw_context_t, ssu)),
MM_REG8("SSMR", 0xF0E2, REGTYPE_DBW8_ACCS3, ssu_get_ssmr, ssu_set_ssmr, "SS mode register", offsetof(pw_context_t, ssu)),
MM_REG8("SSER", 0xF0E3, REGTYPE_DBW8_ACCS3, ssu_get_sser, ssu_set_sser, "SS enable register", offsetof(pw_context_t, ssu)),
MM_REG8("SSSR", 0xF0E4, REGTYPE_DBW8_ACCS3, ssu_get_sssr, ssu_set_sssr, "SS status register", offsetof(pw_context_t, ssu)),
MM_REG8("SSRDR", 0xF0E9, REGTYPE_DBW8_ACCS3, ssu_get_ssrdr, NULL, "SS receive data register", offsetof(pw_context_t, ssu)),
MM_REG8("SSTDR", 0xF0EB, REGTYPE_DBW8_ACCS3, ssu_get_sstdr, ssu_set_sstdr, "SS transmit data register", offsetof(pw_context_t, ssu)),
MM_REG8("TMRW", 0xF0F0, REGTYPE_DBW8_ACCS2, tmrw_get_tmrw, tmrw_set_tmrw, "Timer mode register W", 0),
MM_REG8("TCRW", 0xF0F1, REGTYPE_DBW8_ACCS2, tmrw_get_tcrw, tmrw_set_tcrw, "Timer control register W", 0),
MM_REG8("TIERW", 0xF0F2, REGTYPE_DBW8_ACCS2, tmrw_get_tierw, tmrw_set_tierw, "Timer interrupt enable register W", 0),
MM_REG8("TSRW", 0xF0F3, REGTYPE_DBW8_ACCS2, tmrw_get_tsrw, tmrw_set_tsrw, "Timer status register W", 0),
MM_REG8("TIOR0", 0xF0F4, REGTYPE_DBW8_ACCS2, tmrw_get_tior0, tmrw_set_tior0, "Timer I/O control register 0", 0),
MM_REG8("TIOR1", 0xF0F5, REGTYPE_DBW8_ACCS2, tmrw_get_tior1, tmrw_set_tior1, "Timer I/O control register 1", 0),
MM_REG16("TCNT", 0xF0F6, REGTYPE_DBW16_ACCS2, tmrw_get_tcnt, tmrw_set_tcnt, "Timer counter", 0),
MM_REG16("GRA", 0xF0F8, REGTYPE_DBW16_ACCS2, tmrw_get_gra, tmrw_set_gra, "General register A", 0),
MM_REG16("GRB", 0xF0FA, REGTYPE_DBW16_ACCS2, tmrw_get_grb, tmrw_set_grb, "General register B", 0),
MM_REG16("GRC", 0xF0FC, REGTYPE_DBW16_ACCS2, tmrw_get_grc, tmrw_set_grc, "General register C", 0),
MM_REG16("GRD", 0xF0FE, REGTYPE_DBW16_ACCS2, tmrw_get_grd, tmrw_set_grd, "General register D", 0),
MM_REG16("ECPWCR", 0xFF8C, REGTYPE_DBW16_ACCS2, NULL, NULL, "Event counter PWM compare register", 0),
MM_REG16("ECPWDR", 0xFF8E, REGTYPE_DBW16_ACCS2, NULL, NULL, "Event counter PWM data register", 0),
MM_REG8("SPCR", 0xFF91, REGTYPE_DBW8_ACCS2, NULL, NULL, "Serial port control register", 0),
MM_REG8("AEGSR", 0xFF92, REGTYPE_DBW8_ACCS2, NULL, NULL, "Input pin edge select register", 0),
MM_REG8("ECCR", 0xFF94, REGTYPE_DBW8_ACCS2, NULL, NULL, "Event counter control register", 0),
MM_REG8("ECCSR", 0xFF95, REGTYPE_DBW8_ACCS2, NULL, NULL, "Event counter control/status register", 0),
MM_REG8("ECH", 0xFF96, REGTYPE_DBW8_ACCS2, NULL, NULL, "Event counter H", 0),
MM_REG8("ECL", 0xFF97, REGTYPE_DBW8_ACCS2, NULL, NULL, "Event counter L", 0),
MM_REG8("SMR3", 0xFF98, REGTYPE_DBW8_ACCS3, sci_get_smr, sci_set_smr, "Serial mode register 3", 0),
MM_REG8("BRR3", 0xFF99, REGTYPE_DBW8_ACCS3, NULL, NULL, "Bit rate register 3", 0),
MM_REG8("SCR3", 0xFF9A, REGTYPE_DBW8_ACCS3, sci_get_scr, sci_set_scr, "Serial control register 3", 0),
MM_REG8("TDR3", 0xFF9B, REGTYPE_DBW8_ACCS3, sci_get_tdr, sci_set_tdr, "Transmit data register 3", 0),
MM_REG8("SSR3", 0xFF9C, REGTYPE_DBW8_ACCS3, sci_get_ssr, sci_set_ssr, "Serial status register 3", 0),
MM_REG8("RDR3", 0xFF9D, REGTYPE_DBW8_ACCS3, sci_get_rdr, NULL, "Receive data register 3", 0),
MM_REG8("SEMR", 0xFFA6, REGTYPE_DBW8_ACCS3, sci_get_semr, sci_set_semr, "Serial extended mode register", 0),
MM_REG8("IrCR", 0xFFA7, REGTYPE_DBW8_ACCS2, sci_get_ircr, sci_set_ircr, "IrDA control register", 0),
MM_REG8("TMWD", 0xFFB0, REGTYPE_DBW8_ACCS2, NULL, NULL, "Timer mode register WD", 0),
MM_REG8("TCSRWD1", 0xFFB1, REGTYPE_DBW8_ACCS2, NULL, NULL, "Timer control/status register WD1", 0),
MM_REG8("TCSRWD2", 0xFFB2, REGTYPE_DBW8_ACCS2, NULL, NULL, "Timer control/status register WD2", 0),
MM_REG8("TCWD", 0xFFB3, REGTYPE_DBW8_ACCS2, NULL, NULL, "Timer counter WD", 0),
MM_REG16("ADRR", 0xFFBC, REGTYPE_DBW16_ACCS2, adc_get_addr, NULL, "A/D result register", 0),
MM_REG8("AMR", 0xFFBE, REGTYPE_DBW8_ACCS2, NULL, NULL, "A/D mode register", 0),
MM_REG8("ADSR", 0xFFBF, REGTYPE_DBW8_ACCS2, NULL, NULL, "A/D start register", 0),
MM_REG8("PMR1", 0xFFC0, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port mode register 1", 0),
MM_REG8("PMR3", 0xFFC2, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port mode register 3", 0),
MM_REG8("PMRB", 0xFFCA, REGTYPE_DBW8_ACCS2, portb_get_pmrb, portb_set_pmrb, "Port mode register B", offsetof(pw_context_t, portb)),
MM_REG8("PDR1", 0xFFD4, REGTYPE_DBW8_ACCS2, io2_get_pdr1, io2_set_pdr1, "Port data register 1", 0),
MM_REG8("PDR3", 0xFFD6, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port data register 3", 0),
MM_REG8("PDR8", 0xFFDB, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port data register 8", 0),
MM_REG8("PDR9", 0xFFDC, REGTYPE_DBW8_ACCS2, io2_get_pdr9, io2_set_pdr9, "Port data register 9", 0),
MM_REG8("PDRB", 0xFFDE, REGTYPE_DBW8_ACCS2, portb_get_pdrb, NULL, "Port data register B", offsetof(pw_context_t, portb)),
MM_REG8("PUCR1", 0xFFE0, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port pull-up control register 1", 0),
MM_REG8("PUCR3", 0xFFE1, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port pull-up control register 3", 0),
MM_REG8("PCR1", 0xFFE4, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port control register 1", 0),
MM_REG8("PCR3", 0xFFE6, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port control register 3", 0),
MM_REG8("PCR8", 0xFFEB, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port control register 8", 0),
MM_REG8("PCR9", 0xFFEC, REGTYPE_DBW8_ACCS2, NULL, NULL, "Port control register 9", 0),
MM_REG8("SYSCR1", 0xFFF0, REGTYPE_DBW8_ACCS2, sys_get_syscr1, sys_set_syscr1, "System control register 1", 0),
MM_REG8("SYSCR2", 0xFFF1, REGTYPE_DBW8_ACCS2, sys_get_syscr2, sys_set_syscr2, "System control register 2", 0),
MM_REG8("IEGR", 0xFFF2, REGTYPE_DBW8_ACCS2, int_get_iegr, int_set_iegr, "Interrupt edge select register", 0),
MM_REG8("IENR1", 0xFFF3, REGTYPE_DBW8_ACCS2, int_get_ienr1, int_set_ienr1, "Interrupt enable register 1", 0),
MM_REG8("IENR2", 0xFFF4, REGTYPE_DBW8_ACCS2, int_get_ienr2, int_set_ienr2, "Interrupt enable register 2", 0),
MM_REG8("OSCCR", 0xFFF5, REGTYPE_DBW8_ACCS2, sys_get_osccr, sys_set_osccr, "Oscillator control register", 0),
MM_REG8("IRR1", 0xFFF6, REGTYPE_DBW8_ACCS2, int_get_irr1, int_set_irr1, "Interrupt flag register 1", 0),
MM_REG8("IRR2", 0xFFF7, REGTYPE_DBW8_ACCS2, int_get_irr2, int_set_irr2, "Interrupt flag register 2", 0),
MM_REG8("CKSTPR1", 0xFFFA, REGTYPE_DBW8_ACCS2, sys_get_ckstpr1, sys_set_ckstpr1, "Clock stop register 1", 0),
MM_REG8("CKSTPR2", 0xFFFB, REGTYPE_DBW8_ACCS2, sys_get_ckstpr2, sys_set_ckstpr2, "Clock stop register 2", 0),
};
mm_reg_t *find_mm_reg(uint16_t addr, int include_unaligned) {
include_unaligned = 1;
static uint16_t cached_addr = 0;
static mm_reg_t *cached_reg = NULL;
if (cached_addr == addr) {
return cached_reg;
}
int a = 0;
int b = sizeof(mm_registers) / sizeof(mm_registers[0]);
while (a <= b) {
int g = a + (b - a) / 2;
mm_reg_t *reg = &mm_registers[g];
if (reg->addr == addr) {
cached_addr = addr;
cached_reg = reg;
return reg;
} else if (addr < reg->addr) {
b = g - 1;
} else {
a = g + 1;
}
}
if (include_unaligned && likely(a > 0)) {
mm_reg_t *prev_reg = &mm_registers[a-1];
if (likely(prev_reg->type == REGTYPE_DBW16_ACCS2 && prev_reg->addr == addr-1)) {
return prev_reg;
}
}
return NULL;
}
enum grayscale {
WHITE, LIGHT_GRAY, DARK_GRAY, BLACK
};
enum keys {
KEY_ENTER = 2,
KEY_LEFT = 4,
KEY_RIGHT = 8
};
#define RGBA(r,g,b,a) (((a) << 24) | ((r) << 16) | ((g) << 8) | (b))
int32_t colors[] = {
RGBA(172, 174, 163, 255),
RGBA(128, 130, 116, 255),
RGBA(92, 92, 82, 255),
RGBA(30, 25, 22, 255)
};
void fill_audio(void* userdata, uint8_t* stream, int len) {
for (int i = 0; i < len; i++) {
stream[i] = i % 50;
}
}
static int sdl_init() {
SDL_SetHint(SDL_HINT_VIDEO_X11_NET_WM_BYPASS_COMPOSITOR, "0");
#ifdef __EMSCRIPTEN__
SDL_SetHint(SDL_HINT_EMSCRIPTEN_KEYBOARD_ELEMENT, "#canvas");
#endif
if (SDL_Init(SDL_INIT_VIDEO | SDL_INIT_AUDIO) < 0) {
fprintf(stderr, "SDL could not initialize! SDL_Error: %s\n", SDL_GetError());
return 0;
}
gWindow = SDL_CreateWindow(WINDOW_TITLE, SDL_WINDOWPOS_UNDEFINED, SDL_WINDOWPOS_UNDEFINED, WINDOW_WIDTH, WINDOW_HEIGHT, SDL_WINDOW_SHOWN );
if (gWindow == NULL) {
fprintf(stderr, "Window could not be created! SDL_Error: %s\n", SDL_GetError());
return 0;
}
// Create renderer
renderer = SDL_CreateRenderer(gWindow, -1, 0);
SDL_RenderSetLogicalSize(renderer, SCREEN_WIDTH, SCREEN_HEIGHT);
// Create texture that stores frame buffer
sdlTexture = SDL_CreateTexture(renderer,
SDL_PIXELFORMAT_ARGB8888,
SDL_TEXTUREACCESS_STREAMING,
SCREEN_WIDTH, SCREEN_HEIGHT);
return 1;
}
static void sdl_quit() {
SDL_DestroyWindow(gWindow);
gWindow = NULL;
SDL_Quit();
}
static void sdl_draw(lcd_t *lcd) {
// int32_t palette[4];
// {
// int32_t white = colors[0];
// int wr = (white >> 16) & 0xFF;
// int wg = (white >> 8) & 0xFF;
// int wb = white & 0xFF;
// palette[0] = white;
// for (int i = 1; i < 4; i++) {
// int32_t col = colors[i];
// int r = (col >> 16) & 0xFF;
// int g = (col >> 8) & 0xFF;
// int b = col & 0xFF;
// palette[i] = RGBA(
// wr + (int) ((r - wr) * (lcd.contrast / 32.0)),
// wg + (int) ((g - wg) * (lcd.contrast / 32.0)),
// wb + (int) ((b - wb) * (lcd.contrast / 32.0)),
// 255
// );
// }
// }
int pitch = SCREEN_WIDTH * sizeof(uint32_t);
uint32_t *screen;
SDL_LockTexture(sdlTexture, NULL, (void**) &screen, &pitch);
for (int y = 0; y < SCREEN_HEIGHT; y++) {
for (int x = 0; x < SCREEN_WIDTH; x++) {
int yo = y + lcd->display_start_line;
int pg = (yo / 8) % LCD_NUM_PAGES;
int b = yo % 8;
int col = x;
uint16_t byte = (lcd->ram[pg][col*2] << 8) | lcd->ram[pg][col*2+1];
byte >>= b;
uint8_t color = ((byte & 0x100) >> 7) | (byte & 1);
screen[y*SCREEN_WIDTH+x] = colors[color];
}
}
// for (int pg = 0; pg < LCD_NUM_PAGES; pg++) {
// for (int col = 0; col < SCREEN_WIDTH; col++) {
// uint16_t byte = (lcd.ram[pg][col*2] << 8) | lcd.ram[pg][col*2+1];
// for (int b = 0; b < 8; b++) {
// uint8_t color = ((byte & 0x100) >> 7) | (byte & 1);
// int offset = (pg*8+b) * SCREEN_WIDTH+col;
// if (offset > 0 && offset < SCREEN_HEIGHT * SCREEN_WIDTH) {
// screen[offset] = colors[color];
// }
// byte >>= 1;
// }
// }
// }
SDL_UnlockTexture(sdlTexture);
SDL_RenderCopy(renderer, sdlTexture, NULL, NULL);
SDL_RenderPresent(renderer);
}
char branch_mnemonics[16][4] = {
"bra", "brn", "bhi", "bls", "bcc", "bcs", "bne", "beq",
"bvc", "bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble"
};
static uint32_t sign16_32(uint16_t val) {
if (val & (1 << 15)) {
return val | 0xFFFF0000;
} else {
return val;
}
}
static uint32_t sign8_32(uint8_t val) {
if (val & (1 << 7)) {
return val | 0xFFFFFF00;
} else {
return val;
}
}
static uint16_t sign8_16(uint8_t val) {
if (val & (1 << 7)) {
return val | 0xFF00;
} else {
return val;
}
}
#define ABS8(x) (0xFFFF00 | x)
#define ABS16(x) x
//#define ABS16(x) sign16_32(x)
#define ABS24(x) x
#define DISPI32(disp, reg) (read_reg32(ctx, reg) + (int32_t)disp)
#define DISPI16(disp, reg) (read_reg32(ctx, reg) + (int32_t)sign16_32(disp))
enum ccr_bit {
CCR_C, CCR_V, CCR_Z, CCR_N, CCR_U1,
CCR_H, CCR_U2, CCR_I
};
enum reg32 {
ER0, ER1, ER2, ER3, ER4, ER5, ER6, ER7
};
#define ER_SP ER7
enum reg16 {
R0, R1, R2, R3, R4, R5, R6, R7,
E0, E1, E2, E3, E4, E5, E6, E7
};
enum reg8 {
R0H, R1H, R2H, R3H, R4H, R5H, R6H, R7H,
R0L, R1L, R2L, R3L, R4L, R5L, R6L, R7L
};
static uint32_t read_reg32(pw_context_t *ctx, uint32_t reg) {
assert(reg < 8);
return (ctx->regs[reg+8] << 16) | ctx->regs[reg];
}
static uint16_t read_reg16(pw_context_t *ctx, uint32_t reg) {
assert(reg < 16);
return ctx->regs[reg];
}
static uint8_t read_reg8(pw_context_t *ctx, uint32_t reg) {
assert(reg < 16);
return ctx->regs[reg & 0b111] >> ((reg & 8) ? 0 : 8);
}
static void write_reg32(pw_context_t *ctx, uint32_t reg, uint32_t value) {
assert(reg < 8);
ctx->regs[reg+8] = value >> 16;
ctx->regs[reg] = value;
}
static void write_reg16(pw_context_t *ctx, uint32_t reg, uint16_t value) {
assert(reg < 16);
ctx->regs[reg] = value;
}
static void write_reg8(pw_context_t *ctx, uint32_t reg, uint8_t value) {
assert(reg < 16);
int shift = (reg & 8) ? 0 : 8;