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tc358840.c
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/*
* tc358840.c - Toshiba UH2C/D HDMI-CSI bridge driver
*
* Copyright (c) 2015, Armin Weiss <[email protected]>
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is based on the tc358840 - Toshiba HDMI to CSI-2 bridge driver
* from Cisco Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/interrupt.h>
#include <linux/videodev2.h>
#include <linux/workqueue.h>
#include <linux/delay.h>
#include <linux/hdmi.h>
#include <linux/v4l2-dv-timings.h>
#include <media/v4l2-dv-timings.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-event.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-of.h>
#include <media/cec.h>
#include <media/i2c/tc358840.h>
#include "tc358840_regs.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "debug level (0-3)");
#define TEST_PATTERN_DISABLED 0
#define TEST_PATTERN_COLOR_BAR 1
#define TEST_PATTERN_COLOR_CHECKER 2
#define EDID_NUM_BLOCKS_MAX 8
#define EDID_BLOCK_SIZE 128
#define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
#define TC358840_LINK_FREQ_310MHZ 310000000
#define TC358840_PIXEL_RATE ((TC358840_LINK_FREQ_310MHZ/2)*4) // 4 line
static const s64 link_freq_menu_items[] = {
TC358840_LINK_FREQ_310MHZ,
};
static u8 EDID_1920x1080_60[] = {
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
0x52, 0x62, 0x01, 0x88, 0x00, 0x88, 0x88, 0x88,
0x1C, 0x15, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x7B,
};
static struct v4l2_subdev_edid tc358840_edid = {
.pad = 0,
.start_block = 0,
.blocks = 1,
.edid = EDID_1920x1080_60,
};
static const struct v4l2_dv_timings_cap tc358840_timings_cap_1080p60 = {
.type = V4L2_DV_BT_656_1120,
/* keep this initialization for compatibility with GCC < 4.4.6 */
.reserved = { 0 },
/* Pixel clock from REF_01 p. 20. */
V4L2_INIT_BT_TIMINGS(
160, 1920, 120, 1200, 25000000, 165000000,
V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_CAP_PROGRESSIVE |
V4L2_DV_BT_CAP_REDUCED_BLANKING |
V4L2_DV_BT_CAP_CUSTOM)
};
static const struct v4l2_dv_timings_cap tc358840_timings_cap_4kp30 = {
.type = V4L2_DV_BT_656_1120,
/* keep this initialization for compatibility with GCC < 4.4.6 */
.reserved = { 0 },
/* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
V4L2_INIT_BT_TIMINGS(
160, 3840, 120, 2160, 25000000, 300000000,
V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_CAP_PROGRESSIVE |
V4L2_DV_BT_CAP_REDUCED_BLANKING |
V4L2_DV_BT_CAP_CUSTOM)
};
struct tc358840_state {
struct tc358840_platform_data pdata;
struct v4l2_subdev sd;
struct media_pad pad[2];
struct v4l2_ctrl_handler hdl;
struct i2c_client *i2c_client;
/* CONFCTL is modified in ops and tc358840_hdmi_sys_int_handler */
struct mutex confctl_mutex;
struct cec_adapter *cec_adap;
bool enabled;
bool found_signal;
bool found_stable_signal;
unsigned int new_fmt_cnt;
u32 format_changed;
int test_pattern;
/* controls */
struct v4l2_ctrl *detect_tx_5v_ctrl;
struct v4l2_ctrl *audio_sampling_rate_ctrl;
struct v4l2_ctrl *audio_present_ctrl;
struct v4l2_ctrl *rgb_quantization_range_ctrl;
struct v4l2_ctrl *splitter_width_ctrl;
struct v4l2_ctrl *test_pattern_ctrl;
struct delayed_work delayed_work_enable_hotplug;
struct delayed_work delayed_work_enable_format;
/* edid */
u8 edid_blocks_written;
/* timing / mbus */
struct v4l2_dv_timings timings;
struct v4l2_dv_timings detected_timings;
u32 mbus_fmt_code;
u32 rgb_quantization_range;
u32 module_index;
const char *module_facing;
const char *module_name;
const char *len_name;
};
static inline struct tc358840_state *to_state(struct v4l2_subdev *sd)
{
return container_of(sd, struct tc358840_state, sd);
}
static void tc358840_enable_interrupts(
struct v4l2_subdev *sd, bool cable_connected);
static int tc358840_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
static void tc358840_init_interrupts(struct v4l2_subdev *sd);
static int tc358840_s_dv_timings(
struct v4l2_subdev *sd, struct v4l2_dv_timings *timings);
static void tc358840_set_csi(struct v4l2_subdev *sd);
static void tc358840_set_splitter(struct v4l2_subdev *sd);
static int tc358840_set_test_pattern_timing(struct v4l2_subdev *sd,
struct v4l2_dv_timings *timings);
static int get_test_pattern_timing(struct v4l2_subdev *sd,
struct v4l2_dv_timings *timings);
static int tc358840_s_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid);
/* --------------- I2C --------------- */
static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
{
struct tc358840_state *state = to_state(sd);
struct i2c_client *client = state->i2c_client;
int err;
u8 buf[2] = { reg >> 8, reg & 0xff };
struct i2c_msg msgs[] = {
{
.addr = client->addr,
.flags = 0,
.len = 2,
.buf = buf,
},
{
.addr = client->addr,
.flags = I2C_M_RD,
.len = n,
.buf = values,
},
};
err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (err != ARRAY_SIZE(msgs)) {
v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
__func__, reg, client->addr);
}
if (debug < 3)
return;
switch (n) {
case 1:
v4l2_info(sd, "I2C read 0x%04X = 0x%02X\n", reg, values[0]);
break;
case 2:
v4l2_info(sd, "I2C read 0x%04X = 0x%02X%02X\n",
reg, values[1], values[0]);
break;
case 4:
v4l2_info(sd, "I2C read 0x%04X = 0x%02X%02X%02X%02X\n",
reg, values[3], values[2], values[1], values[0]);
break;
default:
v4l2_info(sd, "I2C read %d bytes from address 0x%04X\n",
n, reg);
break;
}
}
static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
{
struct tc358840_state *state = to_state(sd);
struct i2c_client *client = state->i2c_client;
int err, i;
struct i2c_msg msg;
u8 data[I2C_MAX_XFER_SIZE];
if ((2 + n) > I2C_MAX_XFER_SIZE) {
v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
reg, 2 + n);
n = I2C_MAX_XFER_SIZE - 2;
}
msg.addr = client->addr;
msg.buf = data;
msg.len = 2 + n;
msg.flags = 0;
data[0] = reg >> 8;
data[1] = reg & 0xff;
for (i = 0; i < n; i++)
data[2 + i] = values[i];
err = i2c_transfer(client->adapter, &msg, 1);
if (err != 1) {
v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
__func__, reg, client->addr);
return;
}
if (debug < 3)
return;
switch (n) {
case 1:
v4l2_info(sd, "I2C write 0x%04X = 0x%02X\n", reg, data[2]);
break;
case 2:
v4l2_info(sd, "I2C write 0x%04X = 0x%02X%02X\n",
reg, data[3], data[2]);
break;
case 4:
v4l2_info(sd, "I2C write 0x%04X = 0x%02X%02X%02X%02X\n",
reg, data[5], data[4], data[3], data[2]);
break;
default:
v4l2_info(sd, "I2C write %d bytes from address 0x%04X\n",
n, reg);
}
}
static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
{
u8 val;
i2c_rd(sd, reg, &val, 1);
return val;
}
static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
{
i2c_wr(sd, reg, &val, 1);
}
static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
u8 mask, u8 val)
{
i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
}
static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
{
u16 val;
i2c_rd(sd, reg, (u8 *)&val, 2);
return val;
}
static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
{
i2c_wr(sd, reg, (u8 *)&val, 2);
}
static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
{
i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
}
static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
{
u32 val;
i2c_rd(sd, reg, (u8 *)&val, 4);
return val;
}
static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
{
i2c_wr(sd, reg, (u8 *)&val, 4);
}
static void i2c_wr32_and_or(struct v4l2_subdev *sd, u32 reg, u32 mask, u32 val)
{
i2c_wr32(sd, reg, (i2c_rd32(sd, reg) & mask) | val);
}
/* --------------- STATUS --------------- */
static inline bool is_hdmi(struct v4l2_subdev *sd)
{
return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
}
static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
{
return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
}
static inline bool no_signal(struct v4l2_subdev *sd)
{
return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
}
static inline bool no_sync(struct v4l2_subdev *sd)
{
return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
}
static inline bool audio_present(struct v4l2_subdev *sd)
{
return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
}
static int get_audio_sampling_rate(struct v4l2_subdev *sd)
{
static const int code_to_rate[] = {
44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
88200, 768000, 96000, 705600, 176400, 0, 192000, 0
};
/* Register FS_SET is not cleared when the cable is disconnected */
if (no_signal(sd))
return 0;
return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
}
static unsigned int tc358840_num_csi_lanes_in_use(struct v4l2_subdev *sd)
{
/* FIXME: Read # of lanes from both, TX0 and TX1 */
return i2c_rd32(sd, CSITX0_BASE_ADDR+LANEEN) & MASK_LANES;
}
/* --------------- TIMINGS --------------- */
static inline unsigned int fps(const struct v4l2_bt_timings *t)
{
if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
return 0;
return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock,
V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
}
static int tc358840_get_detected_timings(struct v4l2_subdev *sd,
struct v4l2_dv_timings *timings)
{
struct v4l2_bt_timings *bt = &timings->bt;
struct tc358840_state *state = to_state(sd);
unsigned int width, height, frame_width, frame_height, frame_interval;
unsigned int fps, pol;
memset(timings, 0, sizeof(struct v4l2_dv_timings));
if (state->test_pattern)
return get_test_pattern_timing(sd, timings);
if (no_signal(sd)) {
v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
return -ENOLINK;
}
if (no_sync(sd)) {
v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
return -ENOLCK;
}
timings->type = V4L2_DV_BT_656_1120;
bt->interlaced = i2c_rd8(sd, VI_STATUS1) &
MASK_S_V_INTERLACE ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
width = ((i2c_rd8(sd, DE_HSIZE_HI) & 0x1f) << 8) +
i2c_rd8(sd, DE_HSIZE_LO);
height = ((i2c_rd8(sd, DE_VSIZE_HI) & 0x1f) << 8) +
i2c_rd8(sd, DE_VSIZE_LO);
frame_width = ((i2c_rd8(sd, IN_HSIZE_HI) & 0x1f) << 8) +
i2c_rd8(sd, IN_HSIZE_LO);
frame_height = (((i2c_rd8(sd, IN_VSIZE_HI) & 0x3f) << 8) +
i2c_rd8(sd, IN_VSIZE_LO)) / 2;
pol = i2c_rd8(sd, CLK_STATUS);
/*
* Frame interval in milliseconds * 10
* Require SYS_FREQ0 and SYS_FREQ1 are precisely set
*/
frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
i2c_rd8(sd, FV_CNT_LO);
fps = (frame_interval > 0) ?
DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
bt->width = width;
bt->height = height;
bt->vsync = frame_height - height;
bt->hsync = frame_width - width;
bt->pixelclock = frame_width * frame_height * fps;
if (pol & MASK_S_V_HPOL)
bt->polarities |= V4L2_DV_HSYNC_POS_POL;
if (pol & MASK_S_V_VPOL)
bt->polarities |= V4L2_DV_VSYNC_POS_POL;
if (bt->interlaced == V4L2_DV_INTERLACED) {
bt->height *= 2;
bt->il_vsync = bt->vsync + 1;
bt->pixelclock /= 2;
}
/* Sanity check */
if (bt->width < 640 || bt->height < 480 ||
(bt->width & 1) || (bt->height & 1) ||
(frame_width & 1) || (frame_width <= width) ||
(frame_height <= height))
return -ENOLCK;
return 0;
}
/* --------------- HOTPLUG / HDCP / EDID --------------- */
static void tc358840_delayed_work_enable_hotplug(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct tc358840_state *state = container_of(dwork,
struct tc358840_state, delayed_work_enable_hotplug);
struct v4l2_subdev *sd = &state->sd;
v4l2_dbg(2, debug, sd, "%s:\n", __func__);
i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
}
static void tc358840_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
{
v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
"enable" : "disable");
i2c_wr8_and_or(sd, HDCP_REG1,
~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
SET_AUTO_P3_RESET_FRAMES(0x0f));
/*
* HDCP is disabled by configuring the receiver as HDCP repeater. The
* repeater mode require software support to work, so HDCP
* authentication will fail.
*/
i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
enable ? (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
/* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth
* second when HDCP is disabled, but the MAX_EXCED bit is handled
* correctly and HDCP is disabled on the HDMI output.
*/
i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
enable ? 0 : MASK_MAX_EXCED);
i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
enable ? 0 : MASK_REPEATER | MASK_READY);
}
static void tc358840_disable_edid(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
v4l2_dbg(2, debug, sd, "%s:\n", __func__);
cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
/*
* DDC access to EDID is also disabled when hotplug is disabled. See
* register DDC_CTL
*/
i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
}
static void tc358840_enable_edid(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
if (state->edid_blocks_written == 0) {
v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
tc358840_s_ctrl_detect_tx_5v(sd);
return;
}
v4l2_dbg(2, debug, sd, "%s:\n", __func__);
/*
* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
* hotplug is enabled. See register DDC_CTL
*/
schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
tc358840_enable_interrupts(sd, true);
tc358840_s_ctrl_detect_tx_5v(sd);
}
static void tc358840_erase_bksv(struct v4l2_subdev *sd)
{
int i;
for (i = 0; i < 5; i++)
i2c_wr8(sd, BKSV + i, 0);
}
/* --------------- infoframe --------------- */
static void print_infoframe(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
union hdmi_infoframe frame;
u8 buffer[HDMI_INFOFRAME_SIZE(SPD)];
if (!is_hdmi(sd)) {
v4l2_info(sd, "DVI-D signal - InfoFrames not supported\n");
return;
}
i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
if (hdmi_infoframe_unpack(&frame, buffer) >= 0)
hdmi_infoframe_log(KERN_INFO, dev, &frame);
/*
* Both the SPD and the Vendor Specific packet sizes are the
* same for the tc358840. Since there is no HDMI_INFOFRAME_SIZE(VENDOR)
* we use HDMI_INFOFRAME_SIZE(SPD) instead.
*/
i2c_rd(sd, PK_VS_0HEAD, buffer, HDMI_INFOFRAME_SIZE(SPD));
if (hdmi_infoframe_unpack(&frame, buffer) >= 0)
hdmi_infoframe_log(KERN_INFO, dev, &frame);
i2c_rd(sd, PK_SPD_0HEAD, buffer, HDMI_INFOFRAME_SIZE(SPD));
if (hdmi_infoframe_unpack(&frame, buffer) >= 0)
hdmi_infoframe_log(KERN_INFO, dev, &frame);
}
/* --------------- CTRLS --------------- */
static int tc358840_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
int tx5v = tx_5v_power_present(sd);
state->detect_tx_5v_ctrl->val = tx5v;
return tx5v;
}
static int tc358840_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
int rate = get_audio_sampling_rate(sd);
state->audio_sampling_rate_ctrl->val = rate;
return rate;
}
static int tc358840_s_ctrl_audio_present(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
int present = audio_present(sd);
state->audio_present_ctrl->val = present;
return present;
}
static int tc358840_update_controls(struct v4l2_subdev *sd)
{
int ret = 0;
ret |= tc358840_s_ctrl_detect_tx_5v(sd);
ret |= tc358840_s_ctrl_audio_sampling_rate(sd);
ret |= tc358840_s_ctrl_audio_present(sd);
return ret;
}
static void set_rgb_quantization_range(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
switch (state->rgb_quantization_range) {
case V4L2_DV_RGB_RANGE_AUTO:
i2c_wr8(sd, VOUT_CSC,
MASK_CSC_MODE_BUILTIN | MASK_COLOR_RGB_FULL);
break;
case V4L2_DV_RGB_RANGE_LIMITED:
i2c_wr8(sd, VOUT_CSC,
MASK_CSC_MODE_BUILTIN | MASK_COLOR_FULL_TO_LIMITED);
break;
case V4L2_DV_RGB_RANGE_FULL:
i2c_wr8(sd, VOUT_CSC,
MASK_CSC_MODE_BUILTIN | MASK_COLOR_LIMITED_TO_FULL);
break;
}
}
/* --------------- INIT --------------- */
static void tc358840_reset_phy(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
v4l2_dbg(1, debug, sd, "%s:\n", __func__);
i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
state->new_fmt_cnt = 0;
}
static void tc358840_reset(struct v4l2_subdev *sd, u16 mask)
{
u16 sysctl = i2c_rd16(sd, SYSCTL);
i2c_wr16(sd, SYSCTL, sysctl | mask);
i2c_wr16(sd, SYSCTL, sysctl & ~mask);
}
static inline void tc358840_sleep_mode(struct v4l2_subdev *sd, bool enable)
{
v4l2_dbg(1, debug, sd, "%s(): %s\n", __func__,
enable ? "enable" : "disable");
i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, enable ? MASK_SLEEP : 0);
}
static int enable_stream(struct v4l2_subdev *sd, bool enable)
{
struct tc358840_state *state = to_state(sd);
struct tc358840_platform_data *pdata = &state->pdata;
u32 sync_timeout_ctr;
v4l2_dbg(2, debug, sd, "%s: %sable\n", __func__, enable ? "en" : "dis");
if (enable == state->enabled)
goto out;
if (enable) {
if (pdata->endpoint.bus.mipi_csi2.flags &
V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) {
i2c_wr32_and_or(sd, FUNCMODE, ~(MASK_CONTCLKMODE),
MASK_FORCESTOP);
} else {
/*
* It is critical for CSI receiver to see lane
* transition LP11->HS. Set to non-continuous mode to
* enable clock lane LP11 state.
*/
i2c_wr32_and_or(sd, FUNCMODE, ~(MASK_CONTCLKMODE), 0);
/*
* Set to continuous mode to trigger LP11->HS
* transition
*/
i2c_wr32_and_or(sd, FUNCMODE, 0, MASK_CONTCLKMODE);
}
/* Unmute video */
i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
/* Signal end of initialization */
i2c_wr8(sd, INIT_END, MASK_INIT_END);
/* Enable testpattern, must use TX1 */
if (state->test_pattern)
i2c_wr16_and_or(sd, CB_CTL,
~(MASK_CB_EN | MASK_CB_CSEL),
MASK_CB_CSEL_CSI_TX1 | MASK_CB_EN);
} else {
/* Enable Registers to be initialized */
i2c_wr8_and_or(sd, INIT_END, ~(MASK_INIT_END), 0x00);
/*
* Mute video so that all data lanes go to LSP11 state.
* No data is output to CSI Tx block.
*/
i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
tc358840_set_csi(sd);
tc358840_set_splitter(sd);
/* Always disable testpattern */
i2c_wr16_and_or(sd, CB_CTL, ~MASK_CB_EN, 0);
}
/* Wait for HDMI input to become stable */
if (enable && !state->test_pattern) {
sync_timeout_ctr = 100;
while (no_sync(sd) && sync_timeout_ctr)
sync_timeout_ctr--;
if (sync_timeout_ctr == 0) {
/* Disable stream again. Probably no cable inserted.. */
v4l2_err(sd, "%s: Timeout: HDMI input sync failed.\n",
__func__);
enable_stream(sd, false);
return -EIO;
}
v4l2_dbg(2, debug, sd,
"%s: Stream enabled! Remaining timeout attempts: %d\n",
__func__, sync_timeout_ctr);
}
mutex_lock(&state->confctl_mutex);
i2c_wr16_and_or(sd, CONFCTL0,
~(MASK_VTX0EN | MASK_VTX1EN | MASK_ABUFEN),
enable ? ((pdata->csi_port & (MASK_VTX0EN | MASK_VTX1EN)) |
MASK_ABUFEN | MASK_TX_MSEL | MASK_AUTOINDEX) :
(MASK_TX_MSEL | MASK_AUTOINDEX));
mutex_unlock(&state->confctl_mutex);
state->enabled = enable;
out:
return 0;
}
static void tc358840_set_splitter(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
v4l2_dbg(3, debug, sd, "%s():\n", __func__);
if (state->timings.bt.width <= 1920) {
i2c_wr16_and_or(sd, SPLITTX0_CTRL,
~(MASK_IFEN | MASK_LCD_CSEL), MASK_SPBP);
i2c_wr16_and_or(sd, SPLITTX1_CTRL,
~(MASK_IFEN | MASK_LCD_CSEL), MASK_SPBP);
i2c_wr16_and_or(sd, SPLITTX0_SPLIT,
(u16)~(MASK_TX1SEL | MASK_EHW), 0);
} else {
i2c_wr16_and_or(sd, SPLITTX0_CTRL,
~(MASK_IFEN | MASK_LCD_CSEL | MASK_SPBP), 0);
i2c_wr16_and_or(sd, SPLITTX1_CTRL,
~(MASK_IFEN | MASK_LCD_CSEL | MASK_SPBP), 0);
i2c_wr16_and_or(sd, SPLITTX0_SPLIT, ~(MASK_TX1SEL), MASK_EHW);
}
}
static int get_hsck_freq(struct tc358840_platform_data *pdata)
{
int hsck = (pdata->refclk_hz / (pdata->pll_prd + 1) *
(pdata->pll_fbd + 1)) / (1 << pdata->pll_frs);
return hsck;
}
static void tc358840_set_pll(struct v4l2_subdev *sd,
enum tc358840_csi_port port)
{
struct tc358840_state *state = to_state(sd);
struct tc358840_platform_data *pdata = &state->pdata;
u16 base_addr;
u32 pllconf;
v4l2_dbg(2, debug, sd, "%s:\n", __func__);
if (WARN_ON((pdata->csi_port <= CSI_TX_NONE) ||
(pdata->csi_port > CSI_TX_BOTH)))
pdata->csi_port = CSI_TX_NONE;
if (pdata->csi_port == CSI_TX_NONE) {
v4l2_err(sd, "%s: No CSI port defined!\n", __func__);
return;
}
base_addr = (port == CSI_TX_0) ? CSITX0_BASE_ADDR :
CSITX1_BASE_ADDR;
pllconf = SET_PLL_PRD(pdata->pll_prd) | SET_PLL_FBD(pdata->pll_fbd) |
SET_PLL_FRS(pdata->pll_frs);
v4l2_dbg(1, debug, sd, "%s: Updating PLL clock of CSI TX%d, hsck=%d\n",
__func__, port-1, get_hsck_freq(pdata));
/* TODO: Set MP_LBW ? */
i2c_wr32_and_or(sd, base_addr+PLLCONF,
~(MASK_PLL_PRD | MASK_PLL_FBD | MASK_PLL_FRS), pllconf);
}
static void tc358840_set_ref_clk(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
struct tc358840_platform_data *pdata = &state->pdata;
u32 sys_freq;
u32 lock_ref_freq;
u16 fh_min;
u16 fh_max;
u32 cec_freq;
u32 nco;
u16 csc;
v4l2_dbg(3, debug, sd, "%s():\n", __func__);
if (WARN_ON((pdata->refclk_hz < 40000000) ||
(pdata->refclk_hz > 50000000)))
pdata->refclk_hz = 42000000;
/* System Frequency */
sys_freq = pdata->refclk_hz / 10000;
i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00FF);
i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xFF00) >> 8);
/* Audio System Frequency */
lock_ref_freq = pdata->refclk_hz / 100;
i2c_wr8(sd, LOCK_REF_FREQA, lock_ref_freq & 0xFF);
i2c_wr8(sd, LOCK_REF_FREQB, (lock_ref_freq >> 8) & 0xFF);
i2c_wr8(sd, LOCK_REF_FREQC, (lock_ref_freq >> 16) & 0x0F);
/* Audio PLL */
i2c_wr8(sd, NCO_F0_MOD, MASK_NCO_F0_MOD_REG);
/* 6.144 * 2^28 = 1649267442 */
nco = (1649267442 / (pdata->refclk_hz / 1000000));
i2c_wr8(sd, NCO_48F0A, nco & 0xFF);
i2c_wr8(sd, NCO_48F0B, (nco >> 8) & 0xFF);
i2c_wr8(sd, NCO_48F0C, (nco >> 16) & 0xFF);
i2c_wr8(sd, NCO_48F0D, (nco >> 24) & 0xFF);
/* 5.6448 * 2^28 = 1515264462 */
nco = (1515264462 / (pdata->refclk_hz / 1000000));
i2c_wr8(sd, NCO_44F0A, nco & 0xFF);
i2c_wr8(sd, NCO_44F0B, (nco >> 8) & 0xFF);
i2c_wr8(sd, NCO_44F0C, (nco >> 16) & 0xFF);
i2c_wr8(sd, NCO_44F0D, (nco >> 24) & 0xFF);
fh_min = pdata->refclk_hz / 100000;
i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
fh_max = (fh_min * 66) / 10;
i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
/* Color Space Conversion */
csc = pdata->refclk_hz / 10000;
i2c_wr8(sd, SCLK_CSC0, csc & 0xFF);
i2c_wr8(sd, SCLK_CSC1, (csc >> 8) & 0xFF);
/*
* Trial and error suggests that the default register value
* of 656 is for a 42 MHz reference clock. Use that to derive
* a new value based on the actual reference clock.
*/
cec_freq = (656 * sys_freq) / 4200;
i2c_wr16(sd, CECHCLK, cec_freq);
i2c_wr16(sd, CECLCLK, cec_freq);
}
static void tc358840_set_csi_mbus_config(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
v4l2_dbg(3, debug, sd, "%s():\n", __func__);
switch (state->mbus_fmt_code) {
case MEDIA_BUS_FMT_UYVY8_1X16:
v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
i2c_wr8(sd, VOUT_FMT, MASK_OUTFMT_422 | MASK_422FMT_NORMAL);
i2c_wr8(sd, VOUT_FIL, MASK_422FIL_3_TAP_444 |
MASK_444FIL_2_TAP);
i2c_wr8(sd, VOUT_SYNC0, MASK_MODE_2);
i2c_wr8(sd, VOUT_CSC, MASK_CSC_MODE_BUILTIN |
MASK_COLOR_601_YCBCR_LIMITED);
mutex_lock(&state->confctl_mutex);
i2c_wr16_and_or(sd, CONFCTL0, ~(MASK_YCBCRFMT),
MASK_YCBCRFMT_YCBCR422_8);
i2c_wr16(sd, CONFCTL1, 0x0);
mutex_unlock(&state->confctl_mutex);
break;
case MEDIA_BUS_FMT_RGB888_1X24:
v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
i2c_wr8(sd, VOUT_FMT, MASK_OUTFMT_444_RGB);
i2c_wr8(sd, VOUT_FIL, MASK_422FIL_3_TAP_444 |
MASK_444FIL_2_TAP);
i2c_wr8(sd, VOUT_SYNC0, MASK_MODE_2);
i2c_wr8(sd, VOUT_CSC, MASK_CSC_MODE_BUILTIN |
MASK_COLOR_RGB_FULL);
set_rgb_quantization_range(sd);
mutex_lock(&state->confctl_mutex);
i2c_wr16_and_or(sd, CONFCTL0, ~(MASK_YCBCRFMT), 0x0);
i2c_wr16_and_or(sd, CONFCTL1, 0x0, MASK_TX_OUT_FMT_RGB888);
mutex_unlock(&state->confctl_mutex);
break;
default:
v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
__func__, state->mbus_fmt_code);
break;
}
}
static unsigned int tc358840_num_csi_lanes_needed(struct v4l2_subdev *sd)
{
/* Always use 4 lanes for one CSI */
return 4;
}
static void tc358840_set_csi(struct v4l2_subdev *sd)
{
struct tc358840_state *state = to_state(sd);
struct tc358840_platform_data *pdata = &state->pdata;
unsigned int lanes = tc358840_num_csi_lanes_needed(sd);
enum tc358840_csi_port port;
u16 base_addr;
v4l2_dbg(3, debug, sd, "%s:\n", __func__);
tc358840_reset(sd, MASK_CTXRST);
for (port = CSI_TX_0; port <= CSI_TX_1; port++) {
base_addr = (port == CSI_TX_0) ? CSITX0_BASE_ADDR :
CSITX1_BASE_ADDR;
/* Test pattern must use TX1: enable it if pattern is active */
if (pdata->csi_port != CSI_TX_BOTH &&
pdata->csi_port != port &&
!state->test_pattern) {
v4l2_dbg(1, debug, sd,
"%s: Disabling CSI TX%d\n", __func__, port-1);
/* Disable CSI lanes (High Z) */
i2c_wr32_and_or(sd, base_addr+LANEEN,
~(MASK_CLANEEN), 0);
continue;
}
v4l2_dbg(1, debug, sd,
"%s: Enabling CSI TX%d\n", __func__, port-1);
/* (0x0108) */
i2c_wr32(sd, base_addr+CSITX_CLKEN, MASK_CSITX_EN);
/*
* PLL has to be enabled between CSITX_CLKEN and
* LANEEN (0x02AC)
*/
tc358840_set_pll(sd, port);
/* (0x02A0) */
i2c_wr32_and_or(sd, base_addr+MIPICLKEN,
~(MASK_MP_CKEN), MASK_MP_ENABLE);
usleep_range(10000, 11000);