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This repository has been archived by the owner on Jun 7, 2023. It is now read-only.

Add: Verilog support; clean up .rst support (already in default). #1363

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Sep 9, 2022

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@bjones1 bjones1 commented Sep 8, 2022

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@bjones1 bjones1 marked this pull request as ready for review September 8, 2022 21:40
@bjones1 bjones1 requested a review from bnmnetp September 8, 2022 21:40
@bnmnetp bnmnetp merged commit 100ff6c into RunestoneInteractive:master Sep 9, 2022
@bjones1 bjones1 deleted the verilog branch September 9, 2022 15:49
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