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vending_machine_timing_report.txt
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024
| Design : vendingmachine
| Device : 7a15t-csg324
| Speed File : -3 PRODUCTION 1.23 2018-06-13
| Design State : Synthesized
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (0)
6. checking no_output_delay (0)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (0)
------------------------------
There are 0 input ports with no input delay specified.
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (0)
-------------------------------
There are 0 ports with no output delay specified.
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
1.896 0.000 0 61 0.332 0.000 0 61 3.500 0.000 0 13
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clock {0.000 4.000} 8.000 125.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clock 3.500 0.000 0 13
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
i2o sys_clock sys_clock 1.896 0.000 0 13 2.193 0.000 0 13
i2r sys_clock sys_clock 5.057 0.000 0 12 0.520 0.000 0 12
r2o sys_clock sys_clock 2.363 0.000 0 14 2.446 0.000 0 14
r2r sys_clock sys_clock 5.460 0.000 0 24 0.492 0.000 0 24
**async_default** sys_clock sys_clock 6.378 0.000 0 12 0.332 0.000 0 12
------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: sys_clock
To Clock: sys_clock
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 3.500ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: sys_clock
Waveform(ns): { 0.000 4.000 }
Period(ns): 8.000
Sources: { clk }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 1.592 8.000 6.408 clk_IBUF_BUFG_inst/I
Min Period n/a FDCE/C n/a 1.000 8.000 7.000 inv_mgr/prod1_count_reg[0]/C
Min Period n/a FDPE/C n/a 1.000 8.000 7.000 inv_mgr/prod1_count_reg[1]/C
Min Period n/a FDCE/C n/a 1.000 8.000 7.000 inv_mgr/prod1_count_reg[2]/C
Min Period n/a FDPE/C n/a 1.000 8.000 7.000 inv_mgr/prod1_count_reg[3]/C
Min Period n/a FDCE/C n/a 1.000 8.000 7.000 inv_mgr/prod2_count_reg[0]/C
Min Period n/a FDPE/C n/a 1.000 8.000 7.000 inv_mgr/prod2_count_reg[1]/C
Min Period n/a FDCE/C n/a 1.000 8.000 7.000 inv_mgr/prod2_count_reg[2]/C
Min Period n/a FDPE/C n/a 1.000 8.000 7.000 inv_mgr/prod2_count_reg[3]/C
Min Period n/a FDCE/C n/a 1.000 8.000 7.000 inv_mgr/prod3_count_reg[0]/C
Min Period n/a FDPE/C n/a 1.000 8.000 7.000 inv_mgr/prod3_count_reg[1]/C
Min Period n/a FDCE/C n/a 1.000 8.000 7.000 inv_mgr/prod3_count_reg[2]/C
Min Period n/a FDPE/C n/a 1.000 8.000 7.000 inv_mgr/prod3_count_reg[3]/C
Low Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[0]/C
Low Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[0]/C
Low Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[1]/C
Low Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[1]/C
Low Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[2]/C
Low Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[2]/C
Low Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[3]/C
Low Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[3]/C
Low Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[0]/C
Low Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[0]/C
Low Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[1]/C
Low Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[1]/C
Low Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[2]/C
Low Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[2]/C
Low Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[3]/C
Low Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[3]/C
Low Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[0]/C
Low Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[0]/C
Low Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[1]/C
Low Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[1]/C
Low Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[2]/C
Low Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[2]/C
Low Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[3]/C
Low Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[3]/C
High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[0]/C
High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[0]/C
High Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[1]/C
High Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[1]/C
High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[2]/C
High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[2]/C
High Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[3]/C
High Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod1_count_reg[3]/C
High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[0]/C
High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[0]/C
High Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[1]/C
High Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[1]/C
High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[2]/C
High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[2]/C
High Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[3]/C
High Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod2_count_reg[3]/C
High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[0]/C
High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[0]/C
High Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[1]/C
High Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[1]/C
High Pulse Width Slow FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[2]/C
High Pulse Width Fast FDCE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[2]/C
High Pulse Width Slow FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[3]/C
High Pulse Width Fast FDPE/C n/a 0.500 4.000 3.500 inv_mgr/prod3_count_reg[3]/C
---------------------------------------------------------------------------------------------------
Path Group: i2o
From Clock: sys_clock
To Clock: sys_clock
Setup : 0 Failing Endpoints, Worst Slack 1.896ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 2.193ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.896ns (required time - arrival time)
Source: cash[4]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: dispense
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 5.368ns (logic 3.373ns (62.829%) route 1.995ns (37.171%))
Logic Levels: 5 (IBUF=1 LUT3=1 LUT4=1 LUT6=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 r cash[4] (IN)
net (fo=0) 0.000 1.400 cash[4]
r cash_IBUF[4]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 r cash_IBUF[4]_inst/O
net (fo=4, unplaced) 0.571 2.794 inv_mgr/cash_IBUF[3]
r inv_mgr/dispense_OBUF_inst_i_5/I5
LUT6 (Prop_lut6_I5_O) 0.097 2.891 r inv_mgr/dispense_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.301 3.192 inv_mgr/dispense_OBUF_inst_i_5_n_0
r inv_mgr/dispense_OBUF_inst_i_2/I0
LUT4 (Prop_lut4_I0_O) 0.097 3.289 r inv_mgr/dispense_OBUF_inst_i_2/O
net (fo=9, unplaced) 0.552 3.841 inv_mgr/sufficient_cash
r inv_mgr/dispense_OBUF_inst_i_1/I0
LUT3 (Prop_lut3_I0_O) 0.097 3.938 r inv_mgr/dispense_OBUF_inst_i_1/O
net (fo=2, unplaced) 0.571 4.509 update_inventory_OBUF
r dispense_OBUF_inst/I
OBUF (Prop_obuf_I_O) 2.259 6.768 r dispense_OBUF_inst/O
net (fo=0) 0.000 6.768 dispense
r dispense (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -6.768
-------------------------------------------------------------------
slack 1.896
Slack (MET) : 1.896ns (required time - arrival time)
Source: cash[4]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: update_inventory
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 5.368ns (logic 3.373ns (62.829%) route 1.995ns (37.171%))
Logic Levels: 5 (IBUF=1 LUT3=1 LUT4=1 LUT6=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 r cash[4] (IN)
net (fo=0) 0.000 1.400 cash[4]
r cash_IBUF[4]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 r cash_IBUF[4]_inst/O
net (fo=4, unplaced) 0.571 2.794 inv_mgr/cash_IBUF[3]
r inv_mgr/dispense_OBUF_inst_i_5/I5
LUT6 (Prop_lut6_I5_O) 0.097 2.891 r inv_mgr/dispense_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.301 3.192 inv_mgr/dispense_OBUF_inst_i_5_n_0
r inv_mgr/dispense_OBUF_inst_i_2/I0
LUT4 (Prop_lut4_I0_O) 0.097 3.289 r inv_mgr/dispense_OBUF_inst_i_2/O
net (fo=9, unplaced) 0.552 3.841 inv_mgr/sufficient_cash
r inv_mgr/dispense_OBUF_inst_i_1/I0
LUT3 (Prop_lut3_I0_O) 0.097 3.938 r inv_mgr/dispense_OBUF_inst_i_1/O
net (fo=2, unplaced) 0.571 4.509 update_inventory_OBUF
r update_inventory_OBUF_inst/I
OBUF (Prop_obuf_I_O) 2.259 6.768 r update_inventory_OBUF_inst/O
net (fo=0) 0.000 6.768 update_inventory
r update_inventory (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -6.768
-------------------------------------------------------------------
slack 1.896
Slack (MET) : 2.098ns (required time - arrival time)
Source: cash[4]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: balance[2]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 5.166ns (logic 3.381ns (65.440%) route 1.785ns (34.560%))
Logic Levels: 5 (IBUF=1 LUT4=1 LUT5=1 LUT6=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 r cash[4] (IN)
net (fo=0) 0.000 1.400 cash[4]
r cash_IBUF[4]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 r cash_IBUF[4]_inst/O
net (fo=4, unplaced) 0.571 2.794 inv_mgr/cash_IBUF[3]
r inv_mgr/dispense_OBUF_inst_i_5/I5
LUT6 (Prop_lut6_I5_O) 0.097 2.891 r inv_mgr/dispense_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.301 3.192 inv_mgr/dispense_OBUF_inst_i_5_n_0
r inv_mgr/dispense_OBUF_inst_i_2/I0
LUT4 (Prop_lut4_I0_O) 0.097 3.289 r inv_mgr/dispense_OBUF_inst_i_2/O
net (fo=9, unplaced) 0.342 3.631 sufficient_cash
r balance_OBUF[2]_inst_i_1/I4
LUT5 (Prop_lut5_I4_O) 0.105 3.736 r balance_OBUF[2]_inst_i_1/O
net (fo=1, unplaced) 0.571 4.307 balance_OBUF[2]
r balance_OBUF[2]_inst/I
OBUF (Prop_obuf_I_O) 2.259 6.566 r balance_OBUF[2]_inst/O
net (fo=0) 0.000 6.566 balance[2]
r balance[2] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -6.566
-------------------------------------------------------------------
slack 2.098
Slack (MET) : 2.106ns (required time - arrival time)
Source: cash[4]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: balance[1]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 5.158ns (logic 3.373ns (65.386%) route 1.785ns (34.614%))
Logic Levels: 5 (IBUF=1 LUT4=2 LUT6=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 r cash[4] (IN)
net (fo=0) 0.000 1.400 cash[4]
r cash_IBUF[4]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 r cash_IBUF[4]_inst/O
net (fo=4, unplaced) 0.571 2.794 inv_mgr/cash_IBUF[3]
r inv_mgr/dispense_OBUF_inst_i_5/I5
LUT6 (Prop_lut6_I5_O) 0.097 2.891 r inv_mgr/dispense_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.301 3.192 inv_mgr/dispense_OBUF_inst_i_5_n_0
r inv_mgr/dispense_OBUF_inst_i_2/I0
LUT4 (Prop_lut4_I0_O) 0.097 3.289 r inv_mgr/dispense_OBUF_inst_i_2/O
net (fo=9, unplaced) 0.342 3.631 sufficient_cash
r balance_OBUF[1]_inst_i_1/I3
LUT4 (Prop_lut4_I3_O) 0.097 3.728 r balance_OBUF[1]_inst_i_1/O
net (fo=1, unplaced) 0.571 4.299 balance_OBUF[1]
r balance_OBUF[1]_inst/I
OBUF (Prop_obuf_I_O) 2.259 6.558 r balance_OBUF[1]_inst/O
net (fo=0) 0.000 6.558 balance[1]
r balance[1] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -6.558
-------------------------------------------------------------------
slack 2.106
Slack (MET) : 2.106ns (required time - arrival time)
Source: cash[4]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: balance[3]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 5.158ns (logic 3.373ns (65.386%) route 1.785ns (34.614%))
Logic Levels: 5 (IBUF=1 LUT4=1 LUT6=2 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 r cash[4] (IN)
net (fo=0) 0.000 1.400 cash[4]
r cash_IBUF[4]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 r cash_IBUF[4]_inst/O
net (fo=4, unplaced) 0.571 2.794 inv_mgr/cash_IBUF[3]
r inv_mgr/dispense_OBUF_inst_i_5/I5
LUT6 (Prop_lut6_I5_O) 0.097 2.891 r inv_mgr/dispense_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.301 3.192 inv_mgr/dispense_OBUF_inst_i_5_n_0
r inv_mgr/dispense_OBUF_inst_i_2/I0
LUT4 (Prop_lut4_I0_O) 0.097 3.289 r inv_mgr/dispense_OBUF_inst_i_2/O
net (fo=9, unplaced) 0.342 3.631 sufficient_cash
r balance_OBUF[3]_inst_i_1/I5
LUT6 (Prop_lut6_I5_O) 0.097 3.728 r balance_OBUF[3]_inst_i_1/O
net (fo=1, unplaced) 0.571 4.299 balance_OBUF[3]
r balance_OBUF[3]_inst/I
OBUF (Prop_obuf_I_O) 2.259 6.558 r balance_OBUF[3]_inst/O
net (fo=0) 0.000 6.558 balance[3]
r balance[3] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -6.558
-------------------------------------------------------------------
slack 2.106
Slack (MET) : 2.106ns (required time - arrival time)
Source: cash[4]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: balance[4]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 5.158ns (logic 3.373ns (65.386%) route 1.785ns (34.614%))
Logic Levels: 5 (IBUF=1 LUT4=1 LUT6=2 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 r cash[4] (IN)
net (fo=0) 0.000 1.400 cash[4]
r cash_IBUF[4]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 r cash_IBUF[4]_inst/O
net (fo=4, unplaced) 0.571 2.794 inv_mgr/cash_IBUF[3]
r inv_mgr/dispense_OBUF_inst_i_5/I5
LUT6 (Prop_lut6_I5_O) 0.097 2.891 r inv_mgr/dispense_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.301 3.192 inv_mgr/dispense_OBUF_inst_i_5_n_0
r inv_mgr/dispense_OBUF_inst_i_2/I0
LUT4 (Prop_lut4_I0_O) 0.097 3.289 r inv_mgr/dispense_OBUF_inst_i_2/O
net (fo=9, unplaced) 0.342 3.631 sufficient_cash
r balance_OBUF[4]_inst_i_1/I5
LUT6 (Prop_lut6_I5_O) 0.097 3.728 r balance_OBUF[4]_inst_i_1/O
net (fo=1, unplaced) 0.571 4.299 balance_OBUF[4]
r balance_OBUF[4]_inst/I
OBUF (Prop_obuf_I_O) 2.259 6.558 r balance_OBUF[4]_inst/O
net (fo=0) 0.000 6.558 balance[4]
r balance[4] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -6.558
-------------------------------------------------------------------
slack 2.106
Slack (MET) : 2.106ns (required time - arrival time)
Source: cash[4]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: balance[5]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 5.158ns (logic 3.373ns (65.386%) route 1.785ns (34.614%))
Logic Levels: 5 (IBUF=1 LUT4=1 LUT6=2 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 r cash[4] (IN)
net (fo=0) 0.000 1.400 cash[4]
r cash_IBUF[4]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 r cash_IBUF[4]_inst/O
net (fo=4, unplaced) 0.571 2.794 inv_mgr/cash_IBUF[3]
r inv_mgr/dispense_OBUF_inst_i_5/I5
LUT6 (Prop_lut6_I5_O) 0.097 2.891 r inv_mgr/dispense_OBUF_inst_i_5/O
net (fo=1, unplaced) 0.301 3.192 inv_mgr/dispense_OBUF_inst_i_5_n_0
r inv_mgr/dispense_OBUF_inst_i_2/I0
LUT4 (Prop_lut4_I0_O) 0.097 3.289 r inv_mgr/dispense_OBUF_inst_i_2/O
net (fo=9, unplaced) 0.342 3.631 sufficient_cash
r balance_OBUF[5]_inst_i_1/I5
LUT6 (Prop_lut6_I5_O) 0.097 3.728 r balance_OBUF[5]_inst_i_1/O
net (fo=1, unplaced) 0.571 4.299 balance_OBUF[5]
r balance_OBUF[5]_inst/I
OBUF (Prop_obuf_I_O) 2.259 6.558 r balance_OBUF[5]_inst/O
net (fo=0) 0.000 6.558 balance[5]
r balance[5] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -6.558
-------------------------------------------------------------------
slack 2.106
Slack (MET) : 2.927ns (required time - arrival time)
Source: product_sel[1]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: product_cost[1]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 4.337ns (logic 3.195ns (73.660%) route 1.142ns (26.340%))
Logic Levels: 3 (IBUF=1 LUT2=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 f product_sel[1] (IN)
net (fo=0) 0.000 1.400 product_sel[1]
f product_sel_IBUF[1]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 f product_sel_IBUF[1]_inst/O
net (fo=19, unplaced) 0.571 2.794 product_sel_IBUF[1]
f product_cost_OBUF[1]_inst_i_1/I0
LUT2 (Prop_lut2_I0_O) 0.113 2.907 r product_cost_OBUF[1]_inst_i_1/O
net (fo=1, unplaced) 0.571 3.478 product_cost_OBUF[1]
r product_cost_OBUF[1]_inst/I
OBUF (Prop_obuf_I_O) 2.259 5.737 r product_cost_OBUF[1]_inst/O
net (fo=0) 0.000 5.737 product_cost[1]
r product_cost[1] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -5.737
-------------------------------------------------------------------
slack 2.927
Slack (MET) : 2.927ns (required time - arrival time)
Source: product_sel[1]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: product_cost[5]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 4.337ns (logic 3.195ns (73.660%) route 1.142ns (26.340%))
Logic Levels: 3 (IBUF=1 LUT2=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 r product_sel[1] (IN)
net (fo=0) 0.000 1.400 product_sel[1]
r product_sel_IBUF[1]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 r product_sel_IBUF[1]_inst/O
net (fo=19, unplaced) 0.571 2.794 product_sel_IBUF[1]
r product_cost_OBUF[5]_inst_i_1/I0
LUT2 (Prop_lut2_I0_O) 0.113 2.907 r product_cost_OBUF[5]_inst_i_1/O
net (fo=1, unplaced) 0.571 3.478 product_cost_OBUF[5]
r product_cost_OBUF[5]_inst/I
OBUF (Prop_obuf_I_O) 2.259 5.737 r product_cost_OBUF[5]_inst/O
net (fo=0) 0.000 5.737 product_cost[5]
r product_cost[5] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -5.737
-------------------------------------------------------------------
slack 2.927
Slack (MET) : 2.943ns (required time - arrival time)
Source: product_sel[1]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: product_cost[2]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 4.321ns (logic 3.179ns (73.562%) route 1.142ns (26.438%))
Logic Levels: 3 (IBUF=1 LUT2=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 f product_sel[1] (IN)
net (fo=0) 0.000 1.400 product_sel[1]
f product_sel_IBUF[1]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 f product_sel_IBUF[1]_inst/O
net (fo=19, unplaced) 0.571 2.794 product_sel_IBUF[1]
f product_cost_OBUF[4]_inst_i_1/I1
LUT2 (Prop_lut2_I1_O) 0.097 2.891 r product_cost_OBUF[4]_inst_i_1/O
net (fo=2, unplaced) 0.571 3.462 product_cost_OBUF[2]
r product_cost_OBUF[2]_inst/I
OBUF (Prop_obuf_I_O) 2.259 5.721 r product_cost_OBUF[2]_inst/O
net (fo=0) 0.000 5.721 product_cost[2]
r product_cost[2] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -5.721
-------------------------------------------------------------------
slack 2.943
Slack (MET) : 2.943ns (required time - arrival time)
Source: product_sel[0]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: product_cost[3]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 4.321ns (logic 3.179ns (73.562%) route 1.142ns (26.438%))
Logic Levels: 3 (IBUF=1 LUT1=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 f product_sel[0] (IN)
net (fo=0) 0.000 1.400 product_sel[0]
f product_sel_IBUF[0]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 f product_sel_IBUF[0]_inst/O
net (fo=20, unplaced) 0.571 2.794 product_sel_IBUF[0]
f product_cost_OBUF[3]_inst_i_1/I0
LUT1 (Prop_lut1_I0_O) 0.097 2.891 r product_cost_OBUF[3]_inst_i_1/O
net (fo=1, unplaced) 0.571 3.462 product_cost_OBUF[3]
r product_cost_OBUF[3]_inst/I
OBUF (Prop_obuf_I_O) 2.259 5.721 r product_cost_OBUF[3]_inst/O
net (fo=0) 0.000 5.721 product_cost[3]
r product_cost[3] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -5.721
-------------------------------------------------------------------
slack 2.943
Slack (MET) : 2.943ns (required time - arrival time)
Source: product_sel[1]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: product_cost[4]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 4.321ns (logic 3.179ns (73.562%) route 1.142ns (26.438%))
Logic Levels: 3 (IBUF=1 LUT2=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns
Clock Path Skew: 1.200ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.200ns = ( 9.200 - 8.000 )
Source Clock Delay (SCD): 0.000ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
0.000 0.000 r
clock source latency 1.200 1.200
input delay 0.200 1.400
0.000 1.400 f product_sel[1] (IN)
net (fo=0) 0.000 1.400 product_sel[1]
f product_sel_IBUF[1]_inst/I
IBUF (Prop_ibuf_I_O) 0.822 2.222 f product_sel_IBUF[1]_inst/O
net (fo=19, unplaced) 0.571 2.794 product_sel_IBUF[1]
f product_cost_OBUF[4]_inst_i_1/I1
LUT2 (Prop_lut2_I1_O) 0.097 2.891 r product_cost_OBUF[4]_inst_i_1/O
net (fo=2, unplaced) 0.571 3.462 product_cost_OBUF[2]
r product_cost_OBUF[4]_inst/I
OBUF (Prop_obuf_I_O) 2.259 5.721 r product_cost_OBUF[4]_inst/O
net (fo=0) 0.000 5.721 product_cost[4]
r product_cost[4] (OUT)
------------------------------------------------------------------- -------------------
(clock sys_clock rise edge)
8.000 8.000 r
clock source latency 1.200 9.200
clock pessimism 0.000 9.200
clock uncertainty -0.035 9.165
output delay -0.500 8.665
-------------------------------------------------------------------
required time 8.665
arrival time -5.721
-------------------------------------------------------------------
slack 2.943
Slack (MET) : 3.612ns (required time - arrival time)
Source: cash[0]
(input port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Destination: balance[0]
(output port clocked by sys_clock {[email protected] [email protected] period=8.000ns})
Path Group: i2o
Path Type: Max at Slow Process Corner
Requirement: 8.000ns (sys_clock [email protected] - sys_clock [email protected])
Data Path Delay: 3.653ns (logic 3.082ns (84.363%) route 0.571ns (15.637%))
Logic Levels: 2 (IBUF=1 OBUF=1)
Input Delay: 0.200ns
Output Delay: 0.500ns