diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala
index 0b71ce64781..5d0d6819c18 100644
--- a/src/main/scala/xiangshan/XSCore.scala
+++ b/src/main/scala/xiangshan/XSCore.scala
@@ -27,13 +27,14 @@ import freechips.rocketchip.tile.HasFPUParameters
 import system.HasSoCParameter
 import utils._
 import utility._
+import xiangshan.frontend._
 import xiangshan.backend._
 import xiangshan.backend.fu.PMPRespBundle
 import xiangshan.backend.trace.TraceCoreInterface
+import xiangshan.mem._
 import xiangshan.cache.mmu._
-import xiangshan.frontend._
-import scala.collection.mutable.ListBuffer
 import xiangshan.cache.mmu.TlbRequestIO
+import scala.collection.mutable.ListBuffer
 
 abstract class XSModule(implicit val p: Parameters) extends Module
   with HasXSParameter
diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
index 3c119b2a720..1053b4725c6 100644
--- a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
@@ -22,13 +22,13 @@ import chisel3.util._
 import difftest._
 import utils._
 import utility._
-import xiangshan.ExceptionNO._
 import xiangshan._
-import xiangshan.backend.MemCoreTopDownIO
+import xiangshan.ExceptionNO._
 import xiangshan.backend.rob.{RobDispatchTopDownIO, RobEnqIO}
-import xiangshan.mem.mdp._
 import xiangshan.backend.Bundles.DynInst
 import xiangshan.backend.fu.FuType
+import xiangshan.mem.mdp._
+import xiangshan.mem.MemCoreTopDownIO
 
 case class DispatchParameters
 (
diff --git a/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala b/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
index 069c3f8551d..4ed7fc9a98b 100644
--- a/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
+++ b/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
@@ -19,18 +19,15 @@ package xiangshan.backend.dispatch
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
+import chisel3.util.experimental.decode._
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utility._
 import xiangshan.ExceptionNO._
 import xiangshan._
-import xiangshan.backend.MemCoreTopDownIO
 import xiangshan.backend.rob.{RobDispatchTopDownIO, RobEnqIO}
-import xiangshan.mem.mdp._
-import xiangshan.mem.{HasVLSUParameters, _}
 import xiangshan.backend.Bundles.{DecodedInst, DynInst, ExuVec, IssueQueueIQWakeUpBundle}
 import xiangshan.backend.fu.{FuConfig, FuType}
 import xiangshan.backend.rename.BusyTable
-import chisel3.util.experimental.decode._
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import xiangshan.backend.fu.{FuConfig, FuType}
 import xiangshan.backend.rename.BusyTableReadIO
 import xiangshan.backend.datapath.DataConfig._
@@ -40,6 +37,9 @@ import xiangshan.backend.datapath.WbConfig.VfWB
 import xiangshan.backend.fu.FuType.FuTypeOrR
 import xiangshan.backend.dispatch.Dispatch2IqFpImp
 import xiangshan.backend.regcache.{RCTagTableReadPort, RegCacheTagTable}
+import xiangshan.mem.MemCoreTopDownIO
+import xiangshan.mem.mdp._
+import xiangshan.mem.{HasVLSUParameters, _}
 
 
 // TODO delete trigger message from frontend to iq
diff --git a/src/main/scala/xiangshan/backend/fu/FuConfig.scala b/src/main/scala/xiangshan/backend/fu/FuConfig.scala
index 3aac56371fe..235ca4f4aec 100644
--- a/src/main/scala/xiangshan/backend/fu/FuConfig.scala
+++ b/src/main/scala/xiangshan/backend/fu/FuConfig.scala
@@ -5,11 +5,11 @@ import chisel3._
 import utils.EnumUtils.OHEnumeration
 import xiangshan.ExceptionNO._
 import xiangshan.SelImm
-import xiangshan.backend.Std
 import xiangshan.backend.fu.fpu.{IntToFP, IntFPToVec}
 import xiangshan.backend.fu.wrapper._
 import xiangshan.backend.Bundles.ExuInput
 import xiangshan.backend.datapath.DataConfig._
+import xiangshan.mem.Std
 
 /**
   *
diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/mem/MemBlock.scala
similarity index 99%
rename from src/main/scala/xiangshan/backend/MemBlock.scala
rename to src/main/scala/xiangshan/mem/MemBlock.scala
index f001bfb6e9e..e02c0b86e04 100644
--- a/src/main/scala/xiangshan/backend/MemBlock.scala
+++ b/src/main/scala/xiangshan/mem/MemBlock.scala
@@ -14,7 +14,7 @@
 * See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
-package xiangshan.backend
+package xiangshan.mem
 
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
@@ -24,29 +24,31 @@ import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModul
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
 import freechips.rocketchip.tile.HasFPUParameters
 import freechips.rocketchip.tilelink._
-import coupledL2.{PrefetchRecv}
 import device.MsiInfoBundle
 import utils._
 import utility._
+import system.SoCParamsKey
 import xiangshan._
+import xiangshan.ExceptionNO._
+import xiangshan.frontend.HasInstrMMIOConst
 import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput}
 import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo}
 import xiangshan.backend.exu.MemExeUnit
 import xiangshan.backend.fu._
 import xiangshan.backend.fu.FuType._
-import xiangshan.backend.rob.{RobDebugRollingIO, RobPtr}
 import xiangshan.backend.fu.util.{HasCSRConst, SdtrigExt}
-import xiangshan.cache._
-import xiangshan.cache.mmu._
+import xiangshan.backend.{BackendToTopBundle, TopToBackendBundle}
+import xiangshan.backend.rob.{RobDebugRollingIO, RobPtr, RobLsqIO}
+import xiangshan.backend.datapath.NewPipelineConnect
+import xiangshan.backend.fu.NewCSR.{CsrTriggerBundle, TriggerUtil}
+import xiangshan.backend.trace.{Itype, TraceCoreInterface}
+import xiangshan.backend.Bundles._
 import xiangshan.mem._
 import xiangshan.mem.mdp._
-import xiangshan.frontend.HasInstrMMIOConst
 import xiangshan.mem.prefetch.{BasePrefecher, L1Prefetcher, SMSParams, SMSPrefetcher}
-import xiangshan.backend.datapath.NewPipelineConnect
-import system.SoCParamsKey
-import xiangshan.backend.fu.NewCSR.TriggerUtil
-import xiangshan.ExceptionNO._
-import xiangshan.backend.trace.{Itype, TraceCoreInterface}
+import xiangshan.cache._
+import xiangshan.cache.mmu._
+import coupledL2.{PrefetchRecv}
 
 trait HasMemBlockParameters extends HasXSParameter {
   // number of memory units
diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
index 289202d46b2..80861fb11f4 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
@@ -28,7 +28,7 @@ import utility._
 import xiangshan.backend.Bundles
 import xiangshan.backend.Bundles.{DynInst, MemExuOutput}
 import xiangshan.backend.fu.FuConfig.LduCfg
-import xiangshan.backend.HasMemBlockParameters
+import xiangshan.mem.HasMemBlockParameters
 
 class UncacheEntry(entryIndex: Int)(implicit p: Parameters) extends XSModule
   with HasCircularQueuePtrHelper
@@ -69,13 +69,13 @@ class UncacheEntry(entryIndex: Int)(implicit p: Parameters) extends XSModule
   val uncacheState = RegInit(s_idle)
   val uncacheData = Reg(io.uncache.resp.bits.data.cloneType)
   val nderr = RegInit(false.B)
-  
+
   val writeback = Mux(req.nc, io.ncOut.fire, io.mmioOut.fire)
   val slaveAck = req_valid && io.uncache.idResp.valid && io.uncache.idResp.bits.mid === entryIndex.U
 
   /**
     * Flush
-    * 
+    *
     * 1. direct flush during idle
     * 2. otherwise delayed flush until receiving uncache resp
     */
@@ -289,7 +289,7 @@ class LoadQueueUncache(implicit p: Parameters) extends XSModule
     // exception generated by outer bus
     val exception = Valid(new LqWriteBundle)
   })
-  
+
   /******************************************************************
    * Structure
    ******************************************************************/
@@ -331,13 +331,13 @@ class LoadQueueUncache(implicit p: Parameters) extends XSModule
 
   /******************************************************************
    * Enqueue
-   * 
+   *
    * s1: hold
    * s2: confirm enqueue and write entry
    *    valid: no redirect, no exception, no replay, is mmio/nc
    *    ready: freelist can allocate
    ******************************************************************/
-  
+
   val s1_sortedVec = HwSort(VecInit(io.req.map { case x => DataWithPtr(x.valid, x.bits, x.bits.uop.robIdx) }))
   val s1_req = VecInit(s1_sortedVec.map(_.bits))
   val s1_valid = VecInit(s1_sortedVec.map(_.valid))
@@ -381,17 +381,17 @@ class LoadQueueUncache(implicit p: Parameters) extends XSModule
 
   /******************************************************************
    * Uncache Transaction
-   * 
+   *
    * 1. uncache req
    * 2. uncache resp
    * 3. writeback
    ******************************************************************/
   private val NC_WB_MOD = NCWBPorts.length
-  
+
   val uncacheReq = Wire(DecoupledIO(io.uncache.req.bits.cloneType))
   val mmioSelect = entries.map(e => e.io.mmioSelect).reduce(_ || _)
   val mmioReq = Wire(DecoupledIO(io.uncache.req.bits.cloneType))
-  // TODO lyq: It's best to choose in robIdx order / the order in which they enter 
+  // TODO lyq: It's best to choose in robIdx order / the order in which they enter
   val ncReqArb = Module(new RRArbiterInit(io.uncache.req.bits.cloneType, LoadUncacheBufferSize))
 
   val mmioOut = Wire(DecoupledIO(io.mmioOut(0).bits.cloneType))
@@ -523,16 +523,16 @@ class LoadQueueUncache(implicit p: Parameters) extends XSModule
 
   /******************************************************************
    * Uncache rollback detection
-   * 
+   *
    * When uncache loads enqueue, it searches uncache loads, They can not enqueue and need re-execution.
-   * 
+   *
    * Cycle 0: uncache enqueue.
    * Cycle 1: Select oldest uncache loads.
    * Cycle 2: Redirect Fire.
    *   Choose the oldest load from LoadPipelineWidth oldest loads.
    *   Prepare redirect request according to the detected rejection.
    *   Fire redirect request (if valid)
-   * 
+   *
    *               Load_S3  .... Load_S3
    * stage 0:        lq            lq
    *                 |             | (can not enqueue)
@@ -543,7 +543,7 @@ class LoadQueueUncache(implicit p: Parameters) extends XSModule
    * stage 2:               lq
    *                        |
    *                     rollback req
-   * 
+   *
    ******************************************************************/
   def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = {
     val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.robIdx, xs(i).bits.robIdx)))