cpu.vhd

-- cpu.vhd: Simple 8-bit CPU (BrainFuck interpreter)
-- Copyright (C) 2024 Brno University of Technology,
--                    Faculty of Information Technology
-- Author(s): Jaromír Hodan <xhodanj00 AT stud.fit.vutbr.cz>
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- ----------------------------------------------------------------------------
--                        Entity declaration
-- ----------------------------------------------------------------------------
entity cpu is
  port (
    CLK : in std_logic; -- hodinovy signal
    RESET : in std_logic; -- asynchronni reset procesoru
    EN : in std_logic; -- povoleni cinnosti procesoru

    -- synchronni pamet RAM
    DATA_ADDR : out std_logic_vector(12 downto 0); -- adresa do pameti
    DATA_WDATA : out std_logic_vector(7 downto 0); -- mem[DATA_ADDR] <- DATA_WDATA pokud DATA_EN='1'
    DATA_RDATA : in std_logic_vector(7 downto 0); -- DATA_RDATA <- ram[DATA_ADDR] pokud DATA_EN='1'
    DATA_RDWR : out std_logic; -- cteni (1) / zapis (0)
    DATA_EN : out std_logic; -- povoleni cinnosti

    -- vstupni port
    IN_DATA : in std_logic_vector(7 downto 0); -- IN_DATA <- stav klavesnice pokud IN_VLD='1' a IN_REQ='1'
    IN_VLD : in std_logic; -- data platna
    IN_REQ : out std_logic; -- pozadavek na vstup data

    -- vystupni port
    OUT_DATA : out std_logic_vector(7 downto 0); -- zapisovana data
    OUT_BUSY : in std_logic; -- LCD je zaneprazdnen (1), nelze zapisovat
    OUT_INV : out std_logic; -- pozadavek na aktivaci inverzniho zobrazeni (1)
    OUT_WE : out std_logic; -- LCD <- OUT_DATA pokud OUT_WE='1' a OUT_BUSY='0'

    -- stavove signaly
    READY : out std_logic; -- hodnota 1 znamena, ze byl procesor inicializovan a zacina vykonavat program
    DONE : out std_logic -- hodnota 1 znamena, ze procesor ukoncil vykonavani programu (narazil na instrukci halt)
  );
end cpu;

-- ----------------------------------------------------------------------------
--                      Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of cpu is
  -- pri tvorbe kodu reflektujte rady ze cviceni INP, zejmena mejte na pameti, ze 
  --   - nelze z vice procesu ovladat stejny signal,
  --   - je vhodne mit jeden proces pro popis jedne hardwarove komponenty, protoze pak
  --      - u synchronnich komponent obsahuje sensitivity list pouze CLK a RESET a 
  --      - u kombinacnich komponent obsahuje sensitivity list vsechny ctene signaly. 

  -- prog. counter 
  signal PC : std_logic_vector(12 downto 0);
  signal PC_INC : std_logic;
  signal PC_DEC : std_logic;
  -- memory pointer
  signal PTR : std_logic_vector(12 downto 0);
  signal PTR_INC : std_logic;
  signal PTR_DEC : std_logic;
  -- cycle cntr
  signal CNT : std_logic_vector(12 downto 0);
  signal CNT_INC : std_logic;
  signal CNT_DEC : std_logic;

  -- multiplexor 1
  signal M1_S : std_logic;
  -- multiplexor 2
  signal M2_S : std_logic_vector(2 downto 0);
  -- tmp value
  signal TMP : std_logic_vector(7 downto 0); -- same size as R/W data
  signal TMP_R : std_logic;
  -------------------- VOLUNTARY PART START --------------------
  signal INV_ACTIVE : std_logic := '0';
  -------------------- VOLUNTARY PART END --------------------
  type allowed_states is (
    BEG,
    IDLE,
    FETCH,
    DECODE,
    -- main executable states
    EXE_MOVE_R, -- >
    EXE_MOVE_L, -- <
    --
    EXE_INC, -- +
    EXE_INC_W, -- write read value
    EXE_DEC, -- -
    EXE_DEC_W, -- write read value
    --
    EXE_WHILE_START, -- [
    EXE_WHILE_COMPARE_MEM_WITH_ZERO,
    EXE_WHILE_CNT_NON_ZERO,
    EXE_WHILE_CNT_MODIFY,
    EXE_WHILE_IS_END_QUESTION,
    --
    EXE_WHILE_END, -- ]
    EXE_WHILE_COMPARE_MEM_WITH_ZERO_E,
    EXE_WHILE_CNT_NON_ZERO_E,
    EXE_WHILE_CNT_MODIFY_E,
    EXE_WHILE_IS_END_QUESTION_E,
    --
    EXE_STORE_TMP, -- [dolar sign]
    EXE_STORE_TMP_FRFR,
    --
    EXE_LOAD_TMP, -- !
    EXE_LOAD_TMP_W,
    --
    EXE_PRINT, -- .
    EXE_PRINT_CHAR,
    --
    EXE_READ_INPUT, -- ,
    EXE_WRITE_INPUT,
    --
    HALT, -- [AT] return
    EXE_NO_OPERATION,
    --
    EXE_SPECIAL_DRAW_MODE
  );
  signal STATE : allowed_states := IDLE; -- present state
  signal NEXT_STATE : allowed_states; -- next state
begin
  -- prog. cnt
  PC_HANDLER : process (CLK, RESET,
    PC_INC, PC_DEC)
  begin
    if (RESET = '1') then
      PC <= (others => '0');
    elsif (CLK'event) and (CLK = '1') then
      if (PC_INC = '1') then
        PC <= PC + 1;
      elsif (PC_DEC = '1') then
        PC <= PC - 1;
      end if;
    end if;
  end process;
  -- ptr to memory
  MEM_PTR : process (CLK, RESET,
    PTR_INC,
    PTR_DEC)
  begin
    if (RESET = '1') then
      PTR <= (others => '0');
    elsif (CLK'event) and (CLK = '1') then
      if (PTR_INC = '1') then
        PTR <= PTR + 1;
      elsif (PTR_DEC = '1') then
        PTR <= PTR - 1;
      end if;
    end if;
  end process;
  -- temp
  TMP_HANDLER : process (CLK, RESET, TMP_R)
  begin
    if (RESET = '1') then
      TMP <= (others => '0');
    elsif (CLK'event) and (CLK = '1') then
      if (TMP_R = '1') then
        TMP <= DATA_RDATA;
      end if;
    end if;
  end process;

  -- cycle cnt
  CNT_HANDLER : process (CLK, RESET,
    CNT_INC, CNT_DEC, CNT)
  begin
    if (RESET = '1') then
      CNT <= (others => '0'); -- null the reg
    elsif (rising_edge(CLK)) then
      if (CNT_INC = '1') then
        CNT <= CNT + 1;
      elsif (CNT_DEC = '1') then
        CNT <= CNT - 1;
      end if;
    end if;
  end process;

  -- 0 prog, 1 mem
  MX1 : process (PC, PTR, M1_S)
  begin
    case M1_S is
      when '0' => DATA_ADDR <= PC;
      when '1' => DATA_ADDR <= PTR;
      when others => null;
    end case;
  end process;

  -- ptr++ 001, ptr-- 010, write temp 011, write input 111
  MX2 : process (DATA_RDATA, M2_S)
  begin
    case M2_S is
      when "001" => DATA_WDATA <= DATA_RDATA - 1;
      when "010" => DATA_WDATA <= DATA_RDATA + 1;
      when "011" => DATA_WDATA <= TMP; -- get data from TMP
      when "111" => DATA_WDATA <= IN_DATA;
      when others => null;
    end case;
  end process;

  PRESENT_STATE_REG : process (CLK, RESET,
    STATE, NEXT_STATE, EN)
  begin
    if (RESET = '1') then
      STATE <= BEG;
    elsif (rising_edge(CLK)) and (EN = '1') then
      STATE <= NEXT_STATE;
    end if;
  end process;

  NEXT_STATE_LOGIC : process (
    CLK, RESET, STATE, NEXT_STATE)
  begin
    if (RESET = '1') then
      OUT_DATA <= (others => '0');
      DONE <= '0';
      READY <= '0';
      DATA_EN <= '0';
      DATA_RDWR <= '0';
      INV_ACTIVE <= '0';
    end if;
    -- default values
    OUT_WE <= '0';
    IN_REQ <= '0';
    if (INV_ACTIVE = '0') then
      OUT_INV <= '0';
    else
      OUT_INV <= '1';
    end if;

    -- multiplex
    M1_S <= '0';
    M2_S <= "000";

    -- tmp value
    TMP_R <= '0';

    -- pc
    PC_INC <= '0';
    PC_DEC <= '0';
    -- ptr
    PTR_INC <= '0';
    PTR_DEC <= '0';
    -- cnt
    CNT_INC <= '0';
    CNT_DEC <= '0';

    case STATE is
      when BEG =>
        NEXT_STATE <= IDLE;
      when IDLE =>
        if DATA_RDATA = x"40" then -- [AT] found
          READY <= '1';
          NEXT_STATE <= FETCH;
        else -- go till find [AT]
          PTR_INC <= '1';
          -- set default
          DATA_EN <= '1';
          DATA_RDWR <= '1';
          M1_S <= '1';
        end if;

      when FETCH =>
        DATA_EN <= '1'; -- allow reading
        DATA_RDWR <= '1'; -- read
        M1_S <= '0'; -- read from mem
        NEXT_STATE <= DECODE;

      when DECODE =>
        case (DATA_RDATA) is
          when X"00" => NEXT_STATE <= HALT;
          when X"3E" => NEXT_STATE <= EXE_MOVE_R; -- >
          when X"3C" => NEXT_STATE <= EXE_MOVE_L; -- <
          when X"2B" => NEXT_STATE <= EXE_INC; -- +
          when X"2D" => NEXT_STATE <= EXE_DEC; -- -
          when X"5B" => NEXT_STATE <= EXE_WHILE_START; -- [
          when X"5D" => NEXT_STATE <= EXE_WHILE_END; -- ]
          when X"24" => NEXT_STATE <= EXE_STORE_TMP; -- $
          when X"21" => NEXT_STATE <= EXE_LOAD_TMP; -- !
          when X"2E" => NEXT_STATE <= EXE_PRINT; -- .
          when X"2C" => NEXT_STATE <= EXE_READ_INPUT; -- ,
          when X"40" => NEXT_STATE <= HALT; -- [AT]
          when X"7E" => NEXT_STATE <= EXE_SPECIAL_DRAW_MODE; -- ~ -- voluntary char
          when others => NEXT_STATE <= EXE_NO_OPERATION;
        end case;

      when HALT => -- 🤚🛑
        DONE <= '1'; -- all done, end
        -------------------- MOV PTR --------------------
      when EXE_MOVE_R =>
        PC_INC <= '1';
        PTR_INC <= '1'; -- ptr++;
        NEXT_STATE <= FETCH;
      when EXE_MOVE_L =>
        PC_INC <= '1';
        PTR_DEC <= '1'; -- ptr--;
        NEXT_STATE <= FETCH;
        -------------------- VAL INC --------------------
      when EXE_INC =>
        M1_S <= '1'; -- data
        DATA_RDWR <= '1'; -- R mode
        DATA_EN <= '1';
        NEXT_STATE <= EXE_INC_W;
      when EXE_INC_W =>
        PC_INC <= '1';
        M1_S <= '1'; -- data
        M2_S <= "010"; -- i++
        DATA_RDWR <= '0'; -- W mode
        DATA_EN <= '1';
        NEXT_STATE <= FETCH;
        -------------------- VAL DEC --------------------
      when EXE_DEC =>
        M1_S <= '1'; -- data
        DATA_RDWR <= '1'; -- R mode
        DATA_EN <= '1';
        NEXT_STATE <= EXE_DEC_W;
      when EXE_DEC_W =>
        PC_INC <= '1';
        DATA_RDWR <= '0'; -- W mode
        M1_S <= '1'; -- data
        M2_S <= "001"; -- i--
        DATA_EN <= '1';
        NEXT_STATE <= FETCH;
        -------------------- WHILE LOOP START --------------------
      when EXE_WHILE_START =>
        PC_INC <= '1';
        DATA_RDWR <= '1'; -- R mode
        M1_S <= '1';
        DATA_EN <= '1';
        NEXT_STATE <= EXE_WHILE_COMPARE_MEM_WITH_ZERO;
      when EXE_WHILE_COMPARE_MEM_WITH_ZERO =>
        if (DATA_RDATA = "00000000") then
          CNT_INC <= '1';
          -- read more
          M1_S <= '0';
          DATA_RDWR <= '1'; -- R mode
          DATA_EN <= '1';
          NEXT_STATE <= EXE_WHILE_CNT_NON_ZERO;
        else
          NEXT_STATE <= FETCH; -- dont loop
        end if;
      when EXE_WHILE_CNT_NON_ZERO =>
        M1_S <= '0';
        DATA_RDWR <= '1'; -- R mode
        DATA_EN <= '1';
        NEXT_STATE <= EXE_WHILE_CNT_MODIFY;
      when EXE_WHILE_CNT_MODIFY =>
        case (DATA_RDATA) is
          when X"5B" => CNT_INC <= '1'; -- [
          when X"5D" => CNT_DEC <= '1'; -- ]
          when others => null;
        end case;
        NEXT_STATE <= EXE_WHILE_IS_END_QUESTION;
      when EXE_WHILE_IS_END_QUESTION =>
        PC_INC <= '1';
        if (CNT = "00000000") then
          NEXT_STATE <= FETCH; -- break;
        else
          NEXT_STATE <= EXE_WHILE_CNT_NON_ZERO; -- continue;
        end if;
        ------------------- WHILE LOOP END --------------------
      when EXE_WHILE_END =>
        DATA_RDWR <= '1'; -- R mode
        M1_S <= '1';
        DATA_EN <= '1';
        NEXT_STATE <= EXE_WHILE_COMPARE_MEM_WITH_ZERO_E;
      when EXE_WHILE_COMPARE_MEM_WITH_ZERO_E =>
        if (DATA_RDATA = "00000000") then
          PC_INC <= '1';
          NEXT_STATE <= FETCH; -- end loop
        else
          CNT_INC <= '1';
          PC_DEC <= '1';
          -- read more
          M1_S <= '0';
          DATA_RDWR <= '1'; -- R mode
          DATA_EN <= '1';
          NEXT_STATE <= EXE_WHILE_CNT_NON_ZERO_E;
        end if;
      when EXE_WHILE_CNT_NON_ZERO_E =>
        M1_S <= '0';
        DATA_RDWR <= '1'; -- R mode
        DATA_EN <= '1';
        NEXT_STATE <= EXE_WHILE_CNT_MODIFY_E;
      when EXE_WHILE_CNT_MODIFY_E =>
        case (DATA_RDATA) is
          when X"5B" => CNT_DEC <= '1'; -- [
          when X"5D" => CNT_INC <= '1'; -- ] 
          when others => null;
        end case;
        NEXT_STATE <= EXE_WHILE_IS_END_QUESTION_E;
      when EXE_WHILE_IS_END_QUESTION_E =>
        if (CNT = "00000000") then
          PC_INC <= '1';
          NEXT_STATE <= FETCH; -- break;
        else
          PC_DEC <= '1';
          NEXT_STATE <= EXE_WHILE_CNT_NON_ZERO_E; -- continue;
        end if;
        -------------------- TEMP STORE --------------------
      when EXE_STORE_TMP =>
        DATA_RDWR <= '1'; -- R mode
        M1_S <= '1';
        DATA_EN <= '1';
        NEXT_STATE <= EXE_STORE_TMP_FRFR;
      when EXE_STORE_TMP_FRFR =>
        PC_INC <= '1';
        M1_S <= '1';
        TMP_R <= '1';
        DATA_EN <= '1';
        NEXT_STATE <= FETCH;
        -------------------- TEMP LOAD --------------------
      when EXE_LOAD_TMP =>
        M1_S <= '1';
        DATA_RDWR <= '1'; -- R mode
        DATA_EN <= '1';
        NEXT_STATE <= EXE_LOAD_TMP_W; -- give it time to load
      when EXE_LOAD_TMP_W =>
        PC_INC <= '1';
        M1_S <= '1';
        M2_S <= "011"; -- get data from tmp
        DATA_RDWR <= '0'; -- W mode
        DATA_EN <= '1';
        NEXT_STATE <= FETCH;
        -------------------- PRINT/OUTPUT --------------------
      when EXE_PRINT =>
        DATA_EN <= '1';
        M1_S <= '1';
        NEXT_STATE <= EXE_PRINT_CHAR;
      when EXE_PRINT_CHAR =>
        if (OUT_BUSY = '1') then
          -- display unavalable
          DATA_EN <= '1';
          M1_S <= '1';
          NEXT_STATE <= EXE_PRINT_CHAR; -- try in next clk
        end if;
        if (OUT_BUSY = '0') then
          PC_INC <= '1';
          OUT_DATA <= DATA_RDATA; -- load data into out
          OUT_WE <= '1'; -- print data from out
          NEXT_STATE <= FETCH; -- continue;
        end if;
        -------------------- READ --------------------
      when EXE_READ_INPUT =>
        IN_REQ <= '1'; -- ask for data
        if (IN_VLD = '1') then
          -- valid data
          NEXT_STATE <= EXE_WRITE_INPUT;
        end if;
        -- else wait for valid data, loop
      when EXE_WRITE_INPUT =>
        PC_INC <= '1';
        DATA_RDWR <= '0'; -- W mode
        DATA_EN <= '1';
        M1_S <= '1';
        M2_S <= "111"; -- W in_data to mem
        NEXT_STATE <= FETCH;
        -------------------- NO OPERATION --------------------
      when EXE_NO_OPERATION =>
        PC_INC <= '1';
        NEXT_STATE <= FETCH;
        -------------------- VOLUNTARY PART START --------------------
      when EXE_SPECIAL_DRAW_MODE =>
        PC_INC <= '1';
        -- invert value
        if (INV_ACTIVE = '0') then
          INV_ACTIVE <= '1';
        else
          INV_ACTIVE <= '0';
        end if;
        NEXT_STATE <= FETCH;
        -------------------- VOLUNTARY PART END --------------------
      when others => -- sussy, non existant exe command
        NEXT_STATE <= IDLE;
    end case; -- end case STATE
  end process;

end behavioral;