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[RISCV] Sink hasSideEffects, mayLoad, mayStore from defs to classes in RISCVInstrInfoXCV.td. NFC (llvm#130714)
This is consistent with how RISCVInstrInfo.td is generally structured.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

+38-30
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@
1010
//
1111
//===----------------------------------------------------------------------===//
1212

13-
let DecoderNamespace = "XCV" in {
13+
let DecoderNamespace = "XCV",
14+
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
1415
class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
1516
string opcodestr, string argstr>
1617
: RVInstIBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
@@ -36,10 +37,9 @@ let DecoderNamespace = "XCV" in {
3637
(ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
3738
let rs2 = 0b00000;
3839
}
39-
}
40+
} // DecoderNamespace = "XCV", hasSideEffects = 0, mayLoad = 0, mayStore = 0
4041

41-
let Predicates = [HasVendorXCVbitmanip, IsRV32],
42-
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
42+
let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
4343
def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
4444
def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
4545

@@ -54,7 +54,8 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32],
5454
def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
5555
(ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
5656
"cv.insert", "$rd, $rs1, $is3, $is2">;
57-
let DecoderNamespace = "XCV" in
57+
let DecoderNamespace = "XCV",
58+
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
5859
def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
5960
(ins GPR:$rd, GPR:$rs1, GPR:$rs2),
6061
"cv.insertr", "$rd, $rs1, $rs2">;
@@ -75,6 +76,9 @@ class CVInstMac<bits<7> funct7, bits<3> funct3, string opcodestr>
7576
(outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
7677
opcodestr, "$rd, $rs1, $rs2"> {
7778
let Constraints = "$rd = $rd_wb";
79+
let hasSideEffects = 0;
80+
let mayLoad = 0;
81+
let mayStore = 0;
7882
let DecoderNamespace = "XCV";
7983
}
8084

@@ -86,6 +90,11 @@ class CVInstMacMulN<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
8690

8791
let Inst{31-30} = funct2;
8892
let Inst{29-25} = imm5;
93+
94+
let hasSideEffects = 0;
95+
let mayLoad = 0;
96+
let mayStore = 0;
97+
8998
let DecoderNamespace = "XCV";
9099
}
91100

@@ -99,8 +108,7 @@ class CVInstMulN<bits<2> funct2, bits<3> funct3, string opcodestr>
99108
: CVInstMacMulN<funct2, funct3, (outs GPR:$rd),
100109
(ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
101110

102-
let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0,
103-
mayStore = 0 in {
111+
let Predicates = [HasVendorXCVmac, IsRV32] in {
104112
// 32x32 bit macs
105113
def CV_MAC : CVInstMac<0b1001000, 0b011, "cv.mac">,
106114
Sched<[]>;
@@ -126,9 +134,7 @@ let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0,
126134
Sched<[]>;
127135
def CV_MACHHURN : CVInstMacN<0b11, 0b111, "cv.machhurn">,
128136
Sched<[]>;
129-
} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0...
130137

131-
let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
132138
// Signed 16x16 bit muls with imm
133139
def CV_MULSN : CVInstMulN<0b00, 0b100, "cv.mulsn">,
134140
Sched<[]>;
@@ -148,9 +154,7 @@ let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, may
148154
Sched<[]>;
149155
def CV_MULHHURN : CVInstMulN<0b11, 0b101, "cv.mulhhurn">,
150156
Sched<[]>;
151-
} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0...
152157

153-
let Predicates = [HasVendorXCVmac, IsRV32] in {
154158
// Xcvmac Pseudo Instructions
155159
// Signed 16x16 bit muls
156160
def : InstAlias<"cv.muls $rd1, $rs1, $rs2",
@@ -165,7 +169,8 @@ let Predicates = [HasVendorXCVmac, IsRV32] in {
165169
(CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
166170
} // Predicates = [HasVendorXCVmac, IsRV32]
167171

168-
let DecoderNamespace = "XCV" in {
172+
let DecoderNamespace = "XCV",
173+
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
169174
class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>
170175
: RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPR:$rd),
171176
(ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
@@ -204,8 +209,7 @@ let DecoderNamespace = "XCV" in {
204209

205210
} // DecoderNamespace = "XCV"
206211

207-
let Predicates = [HasVendorXCValu, IsRV32],
208-
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
212+
let Predicates = [HasVendorXCValu, IsRV32] in {
209213
// General ALU Operations
210214
def CV_ABS : CVInstAluR<0b0101000, 0b011, "cv.abs">,
211215
Sched<[]>;
@@ -255,11 +259,7 @@ let Predicates = [HasVendorXCValu, IsRV32],
255259
Sched<[]>;
256260
def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">,
257261
Sched<[]>;
258-
} // Predicates = [HasVendorXCValu, IsRV32],
259-
// hasSideEffects = 0, mayLoad = 0, mayStore = 0
260262

261-
let Predicates = [HasVendorXCValu, IsRV32],
262-
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
263263
def CV_ADDNR : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">,
264264
Sched<[]>;
265265
def CV_ADDUNR : CVInstAluRRNR<0b1000001, 0b011, "cv.addunr">,
@@ -277,8 +277,7 @@ let Predicates = [HasVendorXCValu, IsRV32],
277277
def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">,
278278
Sched<[]>;
279279

280-
} // Predicates = [HasVendorXCValu, IsRV32],
281-
// hasSideEffects = 0, mayLoad = 0, mayStore = 0,
280+
} // Predicates = [HasVendorXCValu, IsRV32]
282281

283282
let Predicates = [HasVendorXCValu, IsRV32] in {
284283
def : MnemonicAlias<"cv.slet", "cv.sle">;
@@ -307,6 +306,7 @@ class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
307306
let DecoderNamespace = "XCV";
308307
}
309308

309+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
310310
class CVSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
311311
string opcodestr>
312312
: CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
@@ -344,6 +344,7 @@ class CVSIMDR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
344344
(ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
345345
let rs2 = 0b00000;
346346
}
347+
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
347348

348349
multiclass CVSIMDBinarySigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {
349350
def CV_ # NAME # _H : CVSIMDRR<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;
@@ -391,8 +392,7 @@ multiclass CVSIMDBinaryUnsignedWb<bits<5> funct5, bit F, bit funct1, string mnem
391392
}
392393

393394

394-
let Predicates = [HasVendorXCVsimd, IsRV32],
395-
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
395+
let Predicates = [HasVendorXCVsimd, IsRV32] in {
396396
defm ADD : CVSIMDBinarySigned<0b00000, 0, 0, "add">;
397397
defm SUB : CVSIMDBinarySigned<0b00001, 0, 0, "sub">;
398398
defm AVG : CVSIMDBinarySigned<0b00010, 0, 0, "avg">;
@@ -494,11 +494,15 @@ class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
494494
: RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
495495
bits<5> imm5;
496496
let rs2 = imm5;
497+
let isBranch = 1;
498+
let isTerminator = 1;
499+
let hasSideEffects = 0;
500+
let mayLoad = 0;
501+
let mayStore = 0;
497502
let DecoderNamespace = "XCV";
498503
}
499504

500-
let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
501-
mayStore = 0, isBranch = 1, isTerminator = 1 in {
505+
let Predicates = [HasVendorXCVbi, IsRV32] in {
502506
// Immediate branching operations
503507
def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
504508
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
@@ -524,15 +528,18 @@ def CVrr : Operand<i32>,
524528
let MIOperandInfo = (ops GPR:$base, GPR:$offset);
525529
}
526530

531+
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
527532
class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
528-
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, simm12:$imm12),
533+
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
534+
(ins GPRMem:$rs1, simm12:$imm12),
529535
opcodestr, "$rd, (${rs1}), ${imm12}"> {
530536
let Constraints = "$rs1_wb = $rs1";
531537
let DecoderNamespace = "XCV";
532538
}
533539

534540
class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
535-
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, GPR:$rs2),
541+
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb),
542+
(ins GPRMem:$rs1, GPR:$rs2),
536543
opcodestr, "$rd, (${rs1}), ${rs2}"> {
537544
let Constraints = "$rs1_wb = $rs1";
538545
let DecoderNamespace = "XCV";
@@ -551,9 +558,9 @@ class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
551558
let Inst{11-7} = rd;
552559
let DecoderNamespace = "XCV";
553560
}
561+
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
554562

555-
let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, mayLoad = 1,
556-
mayStore = 0 in {
563+
let Predicates = [HasVendorXCVmem, IsRV32] in {
557564
// Register-Immediate load with post-increment
558565
def CV_LB_ri_inc : CVLoad_ri_inc<0b000, "cv.lb">;
559566
def CV_LBU_ri_inc : CVLoad_ri_inc<0b100, "cv.lbu">;
@@ -576,6 +583,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, mayLoad = 1,
576583
def CV_LW_rr : CVLoad_rr<0b0000110, 0b011, "cv.lw">;
577584
}
578585

586+
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
579587
class CVStore_ri_inc<bits<3> funct3, string opcodestr>
580588
: RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),
581589
(ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
@@ -616,9 +624,9 @@ class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
616624
let Inst{6-0} = OPC_CUSTOM_1.Value;
617625
let DecoderNamespace = "XCV";
618626
}
627+
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
619628

620-
let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, mayLoad = 0,
621-
mayStore = 1 in {
629+
let Predicates = [HasVendorXCVmem, IsRV32] in {
622630
// Register-Immediate store with post-increment
623631
def CV_SB_ri_inc : CVStore_ri_inc<0b000, "cv.sb">;
624632
def CV_SH_ri_inc : CVStore_ri_inc<0b001, "cv.sh">;

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