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x393_testbench03.sav
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[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat Apr 30 19:42:21 2016
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160429201645793.fst"
[dumpfile_mtime] "Sat Apr 30 02:59:43 2016"
[dumpfile_size] 259025431
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 0
[size] 1823 1180
[pos] 1917 0
*-25.657038 71773130 107947388 109212388 101070300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.simul_sensor12bits_2_i.
[treeopen] x393_testbench03.x393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.i_csconvert_jp4.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.
[treeopen] x393_testbench03.x393_i.frame_sequencer_block[0].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 402
[signals_width] 428
[sst_expanded] 1
[sst_vpaned_height] 518
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x393_testbench03.x393_i.pclk
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@1001200
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@200
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@800200
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@c00200
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-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol
@1401200
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@1401200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp
@1401200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d
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-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din
@1401200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.din
@1401200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.din
@1401200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.din
@1401200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof
@1401200
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-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run
@1001200
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@800200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re
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-hact_off
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-sens_hispi_clock
@c00200
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@800200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din
@1001200
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-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data
@1401200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout
@1401200
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@800200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din
@1401200
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-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_0_w
@1401200
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@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode
@1401200
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-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_ones
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-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sync_decode
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@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.trigger_mode
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.trig_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.trig
@1401200
-trig
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out_sync
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_late_mclk
@200
-lens_flat
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.lens_pxd_in[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.lens_hact_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.lens_sof_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.lens_eof_in
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_pxd_in[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_hact_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_sof_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_eof_in
@200
-sens_gamma
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_pxd_out[7:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_hact_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_sof_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_eof_out
@200
-sensor_channel_out
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.dout[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.dout_valid
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.last_in_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_late_mclk
@200
-sensor_membuf
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_valid
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.last_in_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.rpage_set
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.rpage_next
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_rd
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_dout[63:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.page_written
@200
-sensor_channel_histogram
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_request
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_grant
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_chn[1:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_dvalid
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_data[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@200
-hist_debug
@c00022
x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
(1)x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
(2)x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
(3)x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.eof_out_pclk[3:0]
@800200
-channels_1_3
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@1000200
-channels_1_3
@800200
-sens_sync_chn0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.prst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.pre_sof_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_dly
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.hact
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.hact_single
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.pre_sof_late
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_late
@200
-
@1000200
-sens_sync_chn0
@c00200
-mcntr_linear_rw_sensor0
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_we
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_a[3:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_data[31:0]
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_r[4:0]
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_page
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pre_want
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.want_r
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_want
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_need
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_grant
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_reject
@800028
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_start_r[2:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_start_r[2:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_start_r[2:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_start_r[2:0]
@1001200
-group_end
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_start_wr
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_start_wr_r
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_row[14:0]
@800022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
@1001200
-group_end
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.busy_r
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_height[16:0]
@c00022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(3)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(4)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(5)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(6)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(7)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(8)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(9)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(10)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(11)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(12)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(13)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(14)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(15)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
(16)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.next_y[16:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.last_row_w
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.last_in_row_w
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.last_block
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_done
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_finished
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_done
@c00022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
@1401200
-group_end
@800022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(3)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(4)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(5)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(6)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(7)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(8)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
@1001200
-group_end
@c00022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
(3)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
(4)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
(5)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
(6)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
(7)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
(8)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.calc_valid
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.skip_run
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_delayed
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_mod
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.busy_r
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pre_want
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.want_r
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending
@800028
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
@1001200
-group_end
@200
-
@1401200
-mcntr_linear_rw_sensor0
-sensor_channel_0
@c00200
-DDR3
@28
x393_testbench03.ddr3_i.SDCLK
x393_testbench03.ddr3_i.SDRAS
x393_testbench03.ddr3_i.SDCAS
x393_testbench03.ddr3_i.SDWE
@22
x393_testbench03.ddr3_i.SDA[14:0]
x393_testbench03.ddr3_i.SDBA[2:0]
x393_testbench03.ddr3_i.SDD_D[15:0]
@200
-
@1401200
-DDR3
@c00200
-simul_sensor_0
@28
x393_testbench03.simul_sensor12bits_2_i.MCLK
x393_testbench03.simul_sensor12bits_2_i.c
x393_testbench03.simul_sensor12bits_2_i.ARO
x393_testbench03.simul_sensor12bits_2_i.ARST
x393_testbench03.simul_sensor12bits_2_i.BPF
x393_testbench03.simul_sensor12bits_2_i.DCLK
@22
x393_testbench03.simul_sensor12bits_2_i.D[11:0]
@28
x393_testbench03.simul_sensor12bits_2_i.HACT
x393_testbench03.simul_sensor12bits_2_i.MCLK
x393_testbench03.simul_sensor12bits_2_i.MRST
x393_testbench03.simul_sensor12bits_2_i.NMRST
x393_testbench03.simul_sensor12bits_2_i.OE
x393_testbench03.simul_sensor12bits_2_i.OFST
x393_testbench03.simul_sensor12bits_2_i.SCL
x393_testbench03.simul_sensor12bits_2_i.SDA
x393_testbench03.simul_sensor12bits_2_i.VACT
x393_testbench03.simul_sensor12bits_2_i.VACT1
x393_testbench03.simul_sensor12bits_2_i.arst1
x393_testbench03.simul_sensor12bits_2_i.c
x393_testbench03.simul_sensor12bits_2_i.c_rand
@22
x393_testbench03.simul_sensor12bits_2_i.cntr[15:0]
x393_testbench03.simul_sensor12bits_2_i.cntrd[15:0]
x393_testbench03.simul_sensor12bits_2_i.col[11:0]
x393_testbench03.simul_sensor12bits_2_i.col_index[5:0]
x393_testbench03.simul_sensor12bits_2_i.cold[11:0]
x393_testbench03.simul_sensor12bits_2_i.d_rand[11:0]
@28
x393_testbench03.simul_sensor12bits_2_i.ibpf
x393_testbench03.simul_sensor12bits_2_i.ihact
x393_testbench03.simul_sensor12bits_2_i.ivact
x393_testbench03.simul_sensor12bits_2_i.ivact1
@22
x393_testbench03.simul_sensor12bits_2_i.r
x393_testbench03.simul_sensor12bits_2_i.row[11:0]
x393_testbench03.simul_sensor12bits_2_i.row_index[5:0]
x393_testbench03.simul_sensor12bits_2_i.rowd[11:0]
x393_testbench03.simul_sensor12bits_2_i.seed
x393_testbench03.simul_sensor12bits_2_i.state[3:0]
x393_testbench03.simul_sensor12bits_2_i.stated[3:0]
@28
x393_testbench03.simul_sensor12bits_2_i.stopped
x393_testbench03.simul_sensor12bits_2_i.stoppedd
@1401200
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@c00200
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@28
x393_testbench03.PX1_MCLK_PRE
x393_testbench03.PX1_MCLK
x393_testbench03.PX1_DCLK
x393_testbench03.PX1_ARO
x393_testbench03.PX1_ARST
@22
x393_testbench03.PX1_D[11:0]
@28
x393_testbench03.PX1_FLASH
x393_testbench03.PX1_HACT
@c00200
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@1401200
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@28
x393_testbench03.PX1_MRST
x393_testbench03.PX1_OFST
x393_testbench03.PX1_SHUTTER
x393_testbench03.PX1_VACT
@1401200
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@c00200
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@28
x393_testbench03.simul_sensor12bits_i.MCLK
@22
x393_testbench03.simul_sensor12bits_i.row_index[5:0]
x393_testbench03.simul_sensor12bits_i.row[11:0]
x393_testbench03.simul_sensor12bits_i.col_index[5:0]
x393_testbench03.simul_sensor12bits_i.col[11:0]
x393_testbench03.simul_sensor12bits_i.cold[11:0]
@28
x393_testbench03.simul_sensor12bits_i.c
@22
x393_testbench03.simul_sensor12bits_i.state[3:0]
@28
x393_testbench03.simul_sensor12bits_i.stoppedd
@22
x393_testbench03.simul_sensor12bits_i.cntrd[15:0]
@200
-
@1401200
-SENSOR0
@c00200
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-par12_hspi_lane0_sel
@200
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@1401200
-par12_hspi_lane0_sel
@c00200
-clk_mult_div
@1401200
-clk_mult_div
-par_hispi_sel
@c00200
-sens_hispi_12l4
-lane0
@800200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp
@1001200
-group_end
@c00200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d
@1401200
-group_end
@800200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din
@1001200
-group_end
@800200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode
@1001200
-group_end
@1401200
-lane0
@800200
-fifo0
@200
-
@1000200
-fifo0
@200
-other
@800200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run
@1001200
-group_end
@800200
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re
-x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r
@1001200
-group_end
-group_end
@200
-
@1401200
-sens_hispi_12l4
@c00200
-par_hspi_0
-x393_testbench03.par12_hispi_psp4l0_i.pxd_d
@1401200
-group_end
-par_hspi_0
@c00200
-scheduler16
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pri_reg[255:0]
@c00022
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
@28
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(153)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(154)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(155)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(156)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(157)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(158)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(159)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(160)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(161)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(162)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(163)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(164)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(165)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(166)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(167)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(168)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(169)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(170)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(171)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(172)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(173)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(174)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(175)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(176)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(177)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(178)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(179)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(180)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(181)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(182)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(183)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(184)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(185)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(186)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(187)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(188)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(189)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(190)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(191)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(192)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(193)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(194)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(195)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(196)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(197)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(198)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(199)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(200)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(201)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(202)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(203)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(204)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(205)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(206)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(207)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(208)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(209)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(210)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(211)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(212)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(213)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(214)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(215)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(216)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(217)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(218)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(219)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(220)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(221)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(222)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(223)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(224)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(225)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(226)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(227)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(228)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(229)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(230)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(231)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(232)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(233)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(234)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(235)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(236)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(237)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(238)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(239)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(240)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(241)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(242)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(243)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(244)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(245)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(246)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(247)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(248)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(249)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(250)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(251)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(252)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(253)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(254)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
(255)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
@1401200
-group_end
@800022
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(1)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(2)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(3)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(4)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(5)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(6)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(7)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(8)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(9)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(10)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(11)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(12)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(13)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(14)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
(15)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
@1001200
-group_end
@c00022
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(1)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(2)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(3)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(4)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(5)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(6)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(7)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(8)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(9)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(10)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(11)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(12)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(13)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(14)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
(15)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(1)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(2)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(3)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(4)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(5)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(6)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(7)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(8)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(9)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(10)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(11)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(12)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(13)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(14)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
(15)x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_set[15:0]
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_conf[15:0]
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn[3:0]
@28