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memmap_bcm53158_a0.h
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/*
* $Id:$
*
* This license is set out in https://raw.githubusercontent.com/Broadcom/Broadcom-Compute-Connectivity-Software-robo2-rsdk/master/Legal/LICENSE file.
*
* $Copyright: (c) 2020 Broadcom Inc.
* All Rights Reserved$
*
* File:
* memmap_bcm53158_a0.h
* Description:
* Contains the memory map
* Note:
* This file is autogenerated based on bcm53158_a0.map. Please do not edit
* this file directly, changes will be lost when regenerated
*
*/
#ifndef __MEMMAP_BCM53158_A0_H
#define __MEMMAP_BCM53158_A0_H
#ifdef BCM_53158_A0
/* Memory Map for LOCAL ITCM */
#define BCM53158_A0_LOCAL_ITCM_BASE_ADDR 0x00000000
#define BCM53158_A0_LOCAL_ITCM_END_ADDR 0x00007FFF
#define BCM53158_A0_LOCAL_ITCM_SIZE (32 * 1024)
/* Memory Map for LOCAL CRU-ROM */
#define BCM53158_A0_LOCAL_CRU_ROM_BASE_ADDR 0x00400000
#define BCM53158_A0_LOCAL_CRU_ROM_END_ADDR 0x005FFFFF
#define BCM53158_A0_LOCAL_CRU_ROM_SIZE (2 * 1024 * 1024)
/* Memory Map for REMOTE ITCM */
#define BCM53158_A0_REMOTE_ITCM_BASE_ADDR 0x04000000
#define BCM53158_A0_REMOTE_ITCM_END_ADDR 0x04007FFF
#define BCM53158_A0_REMOTE_ITCM_SIZE (32 * 1024)
/* Memory Map for LOCAL QSPI FLASH */
#define BCM53158_A0_LOCAL_QSPI_FLASH_BASE_ADDR 0x10000000
#define BCM53158_A0_LOCAL_QSPI_FLASH_END_ADDR 0x1FFFFFFF
#define BCM53158_A0_LOCAL_QSPI_FLASH_SIZE (256 * 1024 * 1024)
/* Memory Map for LOCAL DTCM */
#define BCM53158_A0_LOCAL_DTCM_BASE_ADDR 0x20000000
#define BCM53158_A0_LOCAL_DTCM_END_ADDR 0x2000FFFF
#define BCM53158_A0_LOCAL_DTCM_SIZE (64 * 1024)
/* Memory Map for LOCAL PACKET RAM */
#define BCM53158_A0_LOCAL_PACKET_RAM_BASE_ADDR 0x20800000
#define BCM53158_A0_LOCAL_PACKET_RAM_END_ADDR 0x208FFFFF
#define BCM53158_A0_LOCAL_PACKET_RAM_SIZE (1 * 1024 * 1024)
/* Memory Map for REMOTE DTCM */
#define BCM53158_A0_REMOTE_DTCM_BASE_ADDR 0x24000000
#define BCM53158_A0_REMOTE_DTCM_END_ADDR 0x2400FFFF
#define BCM53158_A0_REMOTE_DTCM_SIZE (64 * 1024)
/* Memory Map for REMOTE PACKET RAM */
#define BCM53158_A0_REMOTE_PACKET_RAM_BASE_ADDR 0x24800000
#define BCM53158_A0_REMOTE_PACKET_RAM_END_ADDR 0x248FFFFF
#define BCM53158_A0_REMOTE_PACKET_RAM_SIZE (1 * 1024 * 1024)
/* Memory Map for CRU-CRU */
#define BCM53158_A0_CRU_CRU_BASE_ADDR 0X40200000
#define BCM53158_A0_CRU_CRU_END_ADDR 0X40200FFF
#define BCM53158_A0_CRU_CRU_SIZE (4 * 1024)
/* Memory Map for CRU-AVS */
#define BCM53158_A0_CRU_AVS_BASE_ADDR 0X40201000
#define BCM53158_A0_CRU_AVS_END_ADDR 0X40201FFF
#define BCM53158_A0_CRU_AVS_SIZE (4 * 1024)
/* Memory Map for CRU-OTP */
#define BCM53158_A0_CRU_OTP_BASE_ADDR 0X40202000
#define BCM53158_A0_CRU_OTP_END_ADDR 0X40202FFF
#define BCM53158_A0_CRU_OTP_SIZE (4 * 1024)
/* Memory Map for CRU-EEPROM */
#define BCM53158_A0_CRU_EEPROM_BASE_ADDR 0X40208000
#define BCM53158_A0_CRU_EEPROM_END_ADDR 0X4020FFFF
#define BCM53158_A0_CRU_EEPROM_SIZE (32 * 1024)
/* Memory Map for CRU-TS0 */
#define BCM53158_A0_CRU_TS0_BASE_ADDR 0X40300000
#define BCM53158_A0_CRU_TS0_END_ADDR 0X40300FFF
#define BCM53158_A0_CRU_TS0_SIZE (4 * 1024)
/* Memory Map for CRU-TS1 */
#define BCM53158_A0_CRU_TS1_BASE_ADDR 0X40301000
#define BCM53158_A0_CRU_TS1_END_ADDR 0X40301FFF
#define BCM53158_A0_CRU_TS1_SIZE (4 * 1024)
/* Memory Map for UNIMAC0 */
#define BCM53158_A0_UNIMAC0_BASE_ADDR 0X41000000
#define BCM53158_A0_UNIMAC0_END_ADDR 0X41000FFF
#define BCM53158_A0_UNIMAC0_SIZE (4 * 1024)
/* Memory Map for UNIMAC1 */
#define BCM53158_A0_UNIMAC1_BASE_ADDR 0X41001000
#define BCM53158_A0_UNIMAC1_END_ADDR 0X41001FFF
#define BCM53158_A0_UNIMAC1_SIZE (4 * 1024)
/* Memory Map for UNIMAC2 */
#define BCM53158_A0_UNIMAC2_BASE_ADDR 0X41002000
#define BCM53158_A0_UNIMAC2_END_ADDR 0X41002FFF
#define BCM53158_A0_UNIMAC2_SIZE (4 * 1024)
/* Memory Map for UNIMAC3 */
#define BCM53158_A0_UNIMAC3_BASE_ADDR 0X41003000
#define BCM53158_A0_UNIMAC3_END_ADDR 0X41003FFF
#define BCM53158_A0_UNIMAC3_SIZE (4 * 1024)
/* Memory Map for GPHY_DIG0 */
#define BCM53158_A0_GPHY_DIG0_BASE_ADDR 0X41004000
#define BCM53158_A0_GPHY_DIG0_END_ADDR 0X41004FFF
#define BCM53158_A0_GPHY_DIG0_SIZE (4 * 1024)
/* Memory Map for UNIMAC4 */
#define BCM53158_A0_UNIMAC4_BASE_ADDR 0X41008000
#define BCM53158_A0_UNIMAC4_END_ADDR 0X41008FFF
#define BCM53158_A0_UNIMAC4_SIZE (4 * 1024)
/* Memory Map for UNIMAC5 */
#define BCM53158_A0_UNIMAC5_BASE_ADDR 0X41009000
#define BCM53158_A0_UNIMAC5_END_ADDR 0X41009FFF
#define BCM53158_A0_UNIMAC5_SIZE (4 * 1024)
/* Memory Map for UNIMAC6 */
#define BCM53158_A0_UNIMAC6_BASE_ADDR 0X4100A000
#define BCM53158_A0_UNIMAC6_END_ADDR 0X4100AFFF
#define BCM53158_A0_UNIMAC6_SIZE (4 * 1024)
/* Memory Map for UNIMAC7 */
#define BCM53158_A0_UNIMAC7_BASE_ADDR 0X4100B000
#define BCM53158_A0_UNIMAC7_END_ADDR 0X4100BFFF
#define BCM53158_A0_UNIMAC7_SIZE (4 * 1024)
/* Memory Map for GPHY_DIG1 */
#define BCM53158_A0_GPHY_DIG1_BASE_ADDR 0X4100C000
#define BCM53158_A0_GPHY_DIG1_END_ADDR 0X4100CFFF
#define BCM53158_A0_GPHY_DIG1_SIZE (4 * 1024)
/* Memory Map for UNIMAC8 */
#define BCM53158_A0_UNIMAC8_BASE_ADDR 0X41010000
#define BCM53158_A0_UNIMAC8_END_ADDR 0X41010FFF
#define BCM53158_A0_UNIMAC8_SIZE (4 * 1024)
/* Memory Map for UNIMAC9 */
#define BCM53158_A0_UNIMAC9_BASE_ADDR 0X41011000
#define BCM53158_A0_UNIMAC9_END_ADDR 0X41011FFF
#define BCM53158_A0_UNIMAC9_SIZE (4 * 1024)
/* Memory Map for QSGMII_COMBO */
#define BCM53158_A0_QSGMII_COMBO_BASE_ADDR 0X41012000
#define BCM53158_A0_QSGMII_COMBO_END_ADDR 0X41012FFF
#define BCM53158_A0_QSGMII_COMBO_SIZE (4 * 1024)
/* Memory Map for LED */
#define BCM53158_A0_LED_BASE_ADDR 0X41014000
#define BCM53158_A0_LED_END_ADDR 0X41014FFF
#define BCM53158_A0_LED_SIZE (4 * 1024)
/* Memory Map for PORT MACRO */
#define BCM53158_A0_PORT_MACRO_BASE_ADDR 0X41015000
#define BCM53158_A0_PORT_MACRO_END_ADDR 0X41015FFF
#define BCM53158_A0_PORT_MACRO_SIZE (4 * 1024)
/* Memory Map for UNIMAC14 */
#define BCM53158_A0_UNIMAC14_BASE_ADDR 0X41018000
#define BCM53158_A0_UNIMAC14_END_ADDR 0X41018FFF
#define BCM53158_A0_UNIMAC14_SIZE (4 * 1024)
/* Memory Map for NPA */
#define BCM53158_A0_NPA_BASE_ADDR 0X4101A000
#define BCM53158_A0_NPA_END_ADDR 0X4101AFFF
#define BCM53158_A0_NPA_SIZE (4 * 1024)
/* Memory Map for HPA */
#define BCM53158_A0_HPA_BASE_ADDR 0X4101C000
#define BCM53158_A0_HPA_END_ADDR 0X4101CFFF
#define BCM53158_A0_HPA_SIZE (4 * 1024)
/* Memory Map for M7SC */
#define BCM53158_A0_M7SC_BASE_ADDR 0X41020000
#define BCM53158_A0_M7SC_END_ADDR 0X41020FFF
#define BCM53158_A0_M7SC_SIZE (4 * 1024)
/* Memory Map for QSPI */
#define BCM53158_A0_QSPI_BASE_ADDR 0X41021000
#define BCM53158_A0_QSPI_END_ADDR 0X41021FFF
#define BCM53158_A0_QSPI_SIZE (4 * 1024)
/* Memory Map for SPI */
#define BCM53158_A0_SPI_BASE_ADDR 0X41022000
#define BCM53158_A0_SPI_END_ADDR 0X41022FFF
#define BCM53158_A0_SPI_SIZE (4 * 1024)
/* Memory Map for WDT */
#define BCM53158_A0_WDT_BASE_ADDR 0X41023000
#define BCM53158_A0_WDT_END_ADDR 0X41023FFF
#define BCM53158_A0_WDT_SIZE (4 * 1024)
/* Memory Map for TIM */
#define BCM53158_A0_TIM_BASE_ADDR 0X41024000
#define BCM53158_A0_TIM_END_ADDR 0X41024FFF
#define BCM53158_A0_TIM_SIZE (4 * 1024)
/* Memory Map for I2C */
#define BCM53158_A0_I2C_BASE_ADDR 0X41025000
#define BCM53158_A0_I2C_END_ADDR 0X41025FFF
#define BCM53158_A0_I2C_SIZE (4 * 1024)
/* Memory Map for MDIO */
#define BCM53158_A0_MDIO_BASE_ADDR 0X41026000
#define BCM53158_A0_MDIO_END_ADDR 0X41026FFF
#define BCM53158_A0_MDIO_SIZE (4 * 1024)
/* Memory Map for UART */
#define BCM53158_A0_UART_BASE_ADDR 0X41027000
#define BCM53158_A0_UART_END_ADDR 0X41027FFF
#define BCM53158_A0_UART_SIZE (4 * 1024)
/* Memory Map for GPIO */
#define BCM53158_A0_GPIO_BASE_ADDR 0X41028000
#define BCM53158_A0_GPIO_END_ADDR 0X41028FFF
#define BCM53158_A0_GPIO_SIZE (4 * 1024)
/* Memory Map for RNG */
#define BCM53158_A0_RNG_BASE_ADDR 0X41029000
#define BCM53158_A0_RNG_END_ADDR 0X41029FFF
#define BCM53158_A0_RNG_SIZE (4 * 1024)
/* Memory Map for WRP_SLAVE_S_SPIM */
#define BCM53158_A0_WRP_SLAVE_S_SPIM_BASE_ADDR 0X4102A000
#define BCM53158_A0_WRP_SLAVE_S_SPIM_END_ADDR 0X4102AFFF
#define BCM53158_A0_WRP_SLAVE_S_SPIM_SIZE (4 * 1024)
/* Memory Map for WRP_SLAVE_S_CB */
#define BCM53158_A0_WRP_SLAVE_S_CB_BASE_ADDR 0X4102B000
#define BCM53158_A0_WRP_SLAVE_S_CB_END_ADDR 0X4102BFFF
#define BCM53158_A0_WRP_SLAVE_S_CB_SIZE (4 * 1024)
/* Memory Map for PWM_0 */
#define BCM53158_A0_PWM_0_BASE_ADDR 0X4102C000
#define BCM53158_A0_PWM_0_END_ADDR 0X4102CFFF
#define BCM53158_A0_PWM_0_SIZE (4 * 1024)
/* Memory Map for WRP_DS_DS_0 */
#define BCM53158_A0_WRP_DS_DS_0_BASE_ADDR 0X4102F000
#define BCM53158_A0_WRP_DS_DS_0_END_ADDR 0X4102FFFF
#define BCM53158_A0_WRP_DS_DS_0_SIZE (4 * 1024)
/* Memory Map for CB */
#define BCM53158_A0_CB_BASE_ADDR 0X41100000
#define BCM53158_A0_CB_END_ADDR 0X411FFFFF
#define BCM53158_A0_CB_SIZE (1 * 1024 * 1024)
/* Memory Map for REMOTE PERIPHERAL */
#define BCM53158_A0_REMOTE_PERIPHERAL_BASE_ADDR 0x44000000
#define BCM53158_A0_REMOTE_PERIPHERAL_END_ADDR 0x45FFFFFF
#define BCM53158_A0_REMOTE_PERIPHERAL_SIZE (32 * 1024 * 1024)
/* Memory Regions */
#define BCM53158_A0_MM_REGION_0_BASE_ADDR 0x00000000
#define BCM53158_A0_MM_REGION_0_END_ADDR 0x7FFF
#define BCM53158_A0_MM_REGION_0_SIZE 0x8000
#define BCM53158_A0_MM_REGION_1_BASE_ADDR 0x00400000
#define BCM53158_A0_MM_REGION_1_END_ADDR 0x5FFFFF
#define BCM53158_A0_MM_REGION_1_SIZE 0x200000
#define BCM53158_A0_MM_REGION_2_BASE_ADDR 0x04000000
#define BCM53158_A0_MM_REGION_2_END_ADDR 0x4007FFF
#define BCM53158_A0_MM_REGION_2_SIZE 0x8000
#define BCM53158_A0_MM_REGION_3_BASE_ADDR 0x10000000
#define BCM53158_A0_MM_REGION_3_END_ADDR 0x2000FFFF
#define BCM53158_A0_MM_REGION_3_SIZE 0x10010000
#define BCM53158_A0_MM_REGION_4_BASE_ADDR 0x20800000
#define BCM53158_A0_MM_REGION_4_END_ADDR 0x208FFFFF
#define BCM53158_A0_MM_REGION_4_SIZE 0x100000
#define BCM53158_A0_MM_REGION_5_BASE_ADDR 0x24000000
#define BCM53158_A0_MM_REGION_5_END_ADDR 0x2400FFFF
#define BCM53158_A0_MM_REGION_5_SIZE 0x10000
#define BCM53158_A0_MM_REGION_6_BASE_ADDR 0x24800000
#define BCM53158_A0_MM_REGION_6_END_ADDR 0x248FFFFF
#define BCM53158_A0_MM_REGION_6_SIZE 0x100000
#define BCM53158_A0_MM_REGION_7_BASE_ADDR 0x40200000
#define BCM53158_A0_MM_REGION_7_END_ADDR 0x40202FFF
#define BCM53158_A0_MM_REGION_7_SIZE 0x3000
#define BCM53158_A0_MM_REGION_8_BASE_ADDR 0x40208000
#define BCM53158_A0_MM_REGION_8_END_ADDR 0x4020FFFF
#define BCM53158_A0_MM_REGION_8_SIZE 0x8000
#define BCM53158_A0_MM_REGION_9_BASE_ADDR 0x40300000
#define BCM53158_A0_MM_REGION_9_END_ADDR 0x40301FFF
#define BCM53158_A0_MM_REGION_9_SIZE 0x2000
#define BCM53158_A0_MM_REGION_10_BASE_ADDR 0x41000000
#define BCM53158_A0_MM_REGION_10_END_ADDR 0x41004FFF
#define BCM53158_A0_MM_REGION_10_SIZE 0x5000
#define BCM53158_A0_MM_REGION_11_BASE_ADDR 0x41008000
#define BCM53158_A0_MM_REGION_11_END_ADDR 0x4100CFFF
#define BCM53158_A0_MM_REGION_11_SIZE 0x5000
#define BCM53158_A0_MM_REGION_12_BASE_ADDR 0x41010000
#define BCM53158_A0_MM_REGION_12_END_ADDR 0x41012FFF
#define BCM53158_A0_MM_REGION_12_SIZE 0x3000
#define BCM53158_A0_MM_REGION_13_BASE_ADDR 0x41014000
#define BCM53158_A0_MM_REGION_13_END_ADDR 0x41015FFF
#define BCM53158_A0_MM_REGION_13_SIZE 0x2000
#define BCM53158_A0_MM_REGION_14_BASE_ADDR 0x41018000
#define BCM53158_A0_MM_REGION_14_END_ADDR 0x41018FFF
#define BCM53158_A0_MM_REGION_14_SIZE 0x1000
#define BCM53158_A0_MM_REGION_15_BASE_ADDR 0x4101A000
#define BCM53158_A0_MM_REGION_15_END_ADDR 0x4101AFFF
#define BCM53158_A0_MM_REGION_15_SIZE 0x1000
#define BCM53158_A0_MM_REGION_16_BASE_ADDR 0x4101C000
#define BCM53158_A0_MM_REGION_16_END_ADDR 0x4101CFFF
#define BCM53158_A0_MM_REGION_16_SIZE 0x1000
#define BCM53158_A0_MM_REGION_17_BASE_ADDR 0x41020000
#define BCM53158_A0_MM_REGION_17_END_ADDR 0x4102CFFF
#define BCM53158_A0_MM_REGION_17_SIZE 0xD000
#define BCM53158_A0_MM_REGION_18_BASE_ADDR 0x4102F000
#define BCM53158_A0_MM_REGION_18_END_ADDR 0x4102FFFF
#define BCM53158_A0_MM_REGION_18_SIZE 0x1000
#define BCM53158_A0_MM_REGION_19_BASE_ADDR 0x41100000
#define BCM53158_A0_MM_REGION_19_END_ADDR 0x411FFFFF
#define BCM53158_A0_MM_REGION_19_SIZE 0x100000
#define BCM53158_A0_MM_REGION_20_BASE_ADDR 0x44000000
#define BCM53158_A0_MM_REGION_20_END_ADDR 0x45FFFFFF
#define BCM53158_A0_MM_REGION_20_SIZE 0x2000000
#define BCM53158_A0_MM_REGION_COUNT 21
#define BCM53158_A0_MM_BASE_ADDR 0x00000000
#define BCM53158_A0_MM_END_ADDR 0x45FFFFFF
#endif /* BCM_53158_A0 */
#endif /* __MEMMAP_BCM53158_A0_H */