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UsersGuide.toc
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\contentsline {section}{\numberline {1}Introduction}{7}
\contentsline {section}{\numberline {2}Pixel DAQ System}{7}
\contentsline {subsection}{\numberline {2.1}Overview of DAQ components}{7}
\contentsline {subsubsection}{\numberline {2.1.1}The Read Out Chip}{9}
\contentsline {subsubsection}{\numberline {2.1.2}The Token Bit Manager}{10}
\contentsline {subsubsection}{\numberline {2.1.3}The Pixel FED}{11}
\contentsline {subsubsection}{\numberline {2.1.4}The Pixel FEC}{12}
\contentsline {subsection}{\numberline {2.2}Installation at P5}{13}
\contentsline {section}{\numberline {3}Online Software Overview}{13}
\contentsline {section}{\numberline {4}Package structure}{15}
\contentsline {subsection}{\numberline {4.1}Pixel Function Manager}{16}
\contentsline {subsubsection}{\numberline {4.1.1}FSM Implementation Status}{16}
\contentsline {subsubsection}{\numberline {4.1.2}Control of the L1FM}{18}
\contentsline {subsubsection}{\numberline {4.1.3}Outline of L1FM implementation}{18}
\contentsline {subsection}{\numberline {4.2}PixelSupervisor}{19}
\contentsline {subsubsection}{\numberline {4.2.1}Functions}{19}
\contentsline {subsubsection}{\numberline {4.2.2}Interface}{19}
\contentsline {subsection}{\numberline {4.3}PixelFECSupervisor}{20}
\contentsline {subsection}{\numberline {4.4}PixelFEDSupervisor}{20}
\contentsline {section}{\numberline {5}Coding practices}{20}
\contentsline {subsection}{\numberline {5.1}Makefile}{20}
\contentsline {subsection}{\numberline {5.2}Include files}{20}
\contentsline {subsection}{\numberline {5.3}CVS tags}{20}
\contentsline {subsection}{\numberline {5.4}Building RPMs}{20}
\contentsline {section}{\numberline {6}Configuration Data Management}{22}
\contentsline {section}{\numberline {7}Configuration Database Interface}{22}
\contentsline {subsection}{\numberline {7.1}C++ Configuration Data Access API}{22}
\contentsline {subsubsection}{\numberline {7.1.1}Retrieving data from the database}{22}
\contentsline {subsubsection}{\numberline {7.1.2}Storing data in the database}{24}
\contentsline {subsubsection}{\numberline {7.1.3}Configuration keys}{24}
\contentsline {subsubsection}{\numberline {7.1.4}Alias manipulation}{25}
\contentsline {subsubsection}{\numberline {7.1.5}Support of polymorphism}{26}
\contentsline {subsection}{\numberline {7.2}Command line interface to configuration data}{26}
\contentsline {subsubsection}{\numberline {7.2.1}Inserting new data}{26}
\contentsline {subsubsection}{\numberline {7.2.2}Retrieving data}{27}
\contentsline {subsubsection}{\numberline {7.2.3}Creating new configurations}{27}
\contentsline {subsubsection}{\numberline {7.2.4}Alias manipulation}{28}
\contentsline {subsubsection}{\numberline {7.2.5}Use cases}{28}
\contentsline {subsection}{\numberline {7.3}Managing Configurations}{29}
\contentsline {subsection}{\numberline {7.4}Configuration DB Implementation}{30}
\contentsline {section}{\numberline {8}Configuration Objects}{30}
\contentsline {subsection}{\numberline {8.1}Introduction}{30}
\contentsline {subsection}{\numberline {8.2}Trim and mask bits}{33}
\contentsline {subsection}{\numberline {8.3}ROC DACs}{37}
\contentsline {subsection}{\numberline {8.4}PixelDetectorConfig}{38}
\contentsline {subsection}{\numberline {8.5}PixelROCStatus}{39}
\contentsline {subsection}{\numberline {8.6}PixelNameTranslation}{40}
\contentsline {subsection}{\numberline {8.7}PixelFECConfig}{41}
\contentsline {subsection}{\numberline {8.8}PixelTKFECConfig}{41}
\contentsline {subsection}{\numberline {8.9}PixelFEDConfig}{41}
\contentsline {subsection}{\numberline {8.10}PixelCalibConfiguration}{42}
\contentsline {subsection}{\numberline {8.11}PixelFedCard}{45}
\contentsline {subsection}{\numberline {8.12}PixelTBMSettings}{45}
\contentsline {subsection}{\numberline {8.13}PixelPortcardMap}{46}
\contentsline {subsection}{\numberline {8.14}PixelPortCardConfig}{46}
\contentsline {subsection}{\numberline {8.15}PixelDelay25Calibration}{47}
\contentsline {subsection}{\numberline {8.16}PixelGlobalDelay25}{48}
\contentsline {section}{\numberline {9}Usage of configuration data in xdaq applications}{48}
\contentsline {subsection}{\numberline {9.1}Global delay 25 usage}{50}
\contentsline {section}{\numberline {10}Configuration}{52}
\contentsline {subsection}{\numberline {10.1}Configuration Sequence}{52}
\contentsline {subsubsection}{\numberline {10.1.1}Possible modifications to the configuration Sequence}{53}
\contentsline {subsection}{\numberline {10.2}Configuration steps of the underlying supervisors}{54}
\contentsline {subsubsection}{\numberline {10.2.1}PixelDCSFSMInterface and PixelDCStoTrkFECDpInterface}{54}
\contentsline {subsubsection}{\numberline {10.2.2}PixelTKFECSupervisor}{54}
\contentsline {subsubsection}{\numberline {10.2.3}PixelFEDSupervisor}{54}
\contentsline {subsubsection}{\numberline {10.2.4}PixelFECSupervisor}{54}
\contentsline {subsection}{\numberline {10.3}Quick reconfiguration for the fine delay scan}{54}
\contentsline {subsubsection}{\numberline {10.3.1}Relevant settings}{54}
\contentsline {subsubsection}{\numberline {10.3.2}Implementation}{55}
\contentsline {subsubsection}{\numberline {10.3.3}Limitations}{55}
\contentsline {section}{\numberline {11}Event builder configurations}{55}
\contentsline {section}{\numberline {12}Directory Structure}{56}
\contentsline {subsection}{\numberline {12.1}Tree structure}{56}
\contentsline {section}{\numberline {13}Calibration Algorithms}{59}
\contentsline {subsection}{\numberline {13.1}AOH and FED channel mapping test}{59}
\contentsline {subsubsection}{\numberline {13.1.1}Mapping test steps}{59}
\contentsline {subsubsection}{\numberline {13.1.2}Parameters}{60}
\contentsline {subsection}{\numberline {13.2}FED phase and delay scan}{61}
\contentsline {subsubsection}{\numberline {13.2.1}Output}{61}
\contentsline {subsubsection}{\numberline {13.2.2}Example configuration}{62}
\contentsline {subsection}{\numberline {13.3}Delay25 settings for send data and return data}{62}
\contentsline {subsubsection}{\numberline {13.3.1}Output}{62}
\contentsline {subsection}{\numberline {13.4}Delay25 trigger setting}{62}
\contentsline {subsection}{\numberline {13.5}FED baseline calibration}{64}
\contentsline {subsection}{\numberline {13.6}AOH bias settings}{64}
\contentsline {subsubsection}{\numberline {13.6.1}Introduction and discussion}{64}
\contentsline {subsubsection}{\numberline {13.6.2}AOH bias calibration steps}{66}
\contentsline {subsubsection}{\numberline {13.6.3}Parameters}{68}
\contentsline {subsection}{\numberline {13.7}AOH gain calibration}{68}
\contentsline {subsubsection}{\numberline {13.7.1}Introduction and discussion}{68}
\contentsline {subsubsection}{\numberline {13.7.2}AOH gain calibration steps}{69}
\contentsline {subsubsection}{\numberline {13.7.3}Parameters}{70}
\contentsline {subsection}{\numberline {13.8}TBM UB calibration}{70}
\contentsline {subsubsection}{\numberline {13.8.1}Introduction and discussion}{70}
\contentsline {subsubsection}{\numberline {13.8.2}TBM UB calibration steps}{72}
\contentsline {subsubsection}{\numberline {13.8.3}Parameters}{73}
\contentsline {subsection}{\numberline {13.9}ROC UB equalization calibration}{73}
\contentsline {subsubsection}{\numberline {13.9.1}Introduction and discussion}{73}
\contentsline {subsubsection}{\numberline {13.9.2}ROC UB equalization calibration steps}{73}
\contentsline {subsubsection}{\numberline {13.9.3}Parameters}{75}
\contentsline {subsection}{\numberline {13.10}Address level determination}{76}
\contentsline {subsubsection}{\numberline {13.10.1}Data volume and time estimate}{76}
\contentsline {subsection}{\numberline {13.11}Pixel alive, Scurve, and Gain calibration}{76}
\contentsline {subsubsection}{\numberline {13.11.1}Practical issues}{77}
\contentsline {subsection}{\numberline {13.12}Iana vs. Vana Calibration}{77}
\contentsline {subsection}{\numberline {13.13}Settings of CalDelay and VcThreshold}{79}
\contentsline {subsubsection}{\numberline {13.13.1}Output}{79}
\contentsline {subsubsection}{\numberline {13.13.2}Example}{79}
\contentsline {subsection}{\numberline {13.14}CalDel calibation}{81}
\contentsline {subsubsection}{\numberline {13.14.1}Output}{81}
\contentsline {subsubsection}{\numberline {13.14.2}Example}{81}
\contentsline {subsection}{\numberline {13.15}Idigi vs. Vsf}{83}
\contentsline {subsubsection}{\numberline {13.15.1}Output}{83}
\contentsline {subsubsection}{\numberline {13.15.2}Example}{83}
\contentsline {subsection}{\numberline {13.16}Linearity vs.\nobreakspace {}Vsf}{85}
\contentsline {subsubsection}{\numberline {13.16.1}Introduction and discussion}{85}
\contentsline {subsubsection}{\numberline {13.16.2}Linearity vs.\nobreakspace {}Vsf calibration steps}{86}
\contentsline {subsubsection}{\numberline {13.16.3}Parameters}{87}
\contentsline {subsection}{\numberline {13.17}Vsf and VHldDel}{88}
\contentsline {subsubsection}{\numberline {13.17.1}Introduction and discussion}{88}
\contentsline {subsubsection}{\numberline {13.17.2}Vsf and VHldDel calibration steps}{88}
\contentsline {subsubsection}{\numberline {13.17.3}Parameters}{90}
\contentsline {subsection}{\numberline {13.18}Pulse height range calibration}{91}
\contentsline {subsubsection}{\numberline {13.18.1}Introduction and discussion}{91}
\contentsline {subsubsection}{\numberline {13.18.2}Pulse height calibration procedure}{91}
\contentsline {subsubsection}{\numberline {13.18.3}Parameters}{92}
\contentsline {subsection}{\numberline {13.19}Vana and time walk}{92}
\contentsline {subsection}{\numberline {13.20}Trim bit determination}{93}
\contentsline {subsection}{\numberline {13.21}Trim bit analysis}{94}
\contentsline {subsubsection}{\numberline {13.21.1}Running the threshold analysis}{94}
\contentsline {subsubsection}{\numberline {13.21.2}Quality of trimming}{95}
\contentsline {subsubsection}{\numberline {13.21.3}Determining new VcThr settings}{96}
\contentsline {subsubsection}{\numberline {13.21.4}Make simple plots of thresholds}{96}
\contentsline {subsubsection}{\numberline {13.21.5}Full trim bit determination}{96}
\contentsline {subsubsection}{\numberline {13.21.6}Determining all trimbits}{97}
\contentsline {subsection}{\numberline {13.22}Emulated physics}{97}
\contentsline {subsection}{\numberline {13.23}Baseline with emulated data}{98}
\contentsline {subsection}{\numberline {13.24}Address levels with emulated data}{98}
\contentsline {section}{\numberline {14}Calibration Procedure}{98}
\contentsline {subsection}{\numberline {14.1}Useful Tools, Background Knowledge}{98}
\contentsline {subsection}{\numberline {14.2}Starting Point}{98}
\contentsline {subsection}{\numberline {14.3}AOH and FED Channel Mapping}{99}
\contentsline {subsection}{\numberline {14.4}Achieving Successful Programming}{99}
\contentsline {subsection}{\numberline {14.5}Basic Signal Properties}{100}
\contentsline {subsubsection}{\numberline {14.5.1}FEDBaseline}{100}
\contentsline {subsubsection}{\numberline {14.5.2}AOH Settings}{102}
\contentsline {subsubsection}{\numberline {14.5.3}Ultrablacks}{103}
\contentsline {subsubsection}{\numberline {14.5.4}Clock Phase}{104}
\contentsline {subsection}{\numberline {14.6}Getting Hits}{105}
\contentsline {subsection}{\numberline {14.7}Address Levels}{105}
\contentsline {subsection}{\numberline {14.8}Initial Trimming}{106}
\contentsline {subsection}{\numberline {14.9}Vana Calibration}{106}
\contentsline {subsection}{\numberline {14.10}Final Trimming}{108}
\contentsline {subsection}{\numberline {14.11}Threshold Minimization}{109}
\contentsline {subsection}{\numberline {14.12}Pulse Height Optimizations}{112}
\contentsline {subsubsection}{\numberline {14.12.1}Vsf}{112}
\contentsline {subsubsection}{\numberline {14.12.2}VHldDel}{112}
\contentsline {subsubsection}{\numberline {14.12.3}PHRange}{113}
\contentsline {subsubsection}{\numberline {14.12.4}Gain Calibration}{113}
\contentsline {section}{\numberline {15}XDAQ-DCS Interaction}{115}
\contentsline {subsection}{\numberline {15.1}PSX Server}{115}
\contentsline {subsection}{\numberline {15.2}PixelDCSFSMInterface}{116}
\contentsline {subsection}{\numberline {15.3}Use of DCS information by the supervisors}{117}
\contentsline {subsection}{\numberline {15.4}Configuration}{117}
\contentsline {subsection}{\numberline {15.5}HV-dependent DAC programming}{120}
\contentsline {subsection}{\numberline {15.6}Start and Resume transitions}{121}
\contentsline {subsection}{\numberline {15.7}Pause, Stop, and Halt transitions}{121}
\contentsline {subsection}{\numberline {15.8}Expected behavior}{121}
\contentsline {subsection}{\numberline {15.9}Notes on hardcoding of information}{122}
\contentsline {section}{\numberline {16}Procedures to follow when hardware components are replaced}{122}
\contentsline {subsection}{\numberline {16.1}FED board}{122}
\contentsline {subsection}{\numberline {16.2}Pixel FEC including mFECs}{123}
\contentsline {subsection}{\numberline {16.3}TKFEC}{123}
\contentsline {section}{\numberline {17}Low-level commands}{123}
\contentsline {subsection}{\numberline {17.1}Resets}{123}
\contentsline {section}{\numberline {A}FED phase and delay calibration}{125}
\contentsline {section}{\numberline {B}Calibration Organization}{130}
\contentsline {subsection}{\numberline {B.1}PixelSupervisor calibration code}{130}
\contentsline {subsection}{\numberline {B.2}PixelFEDSupervisor calibration code}{134}
\contentsline {subsection}{\numberline {B.3}Implementation of algorithms}{135}
\contentsline {section}{\numberline {C}Outstanding tasks and improvements}{136}
\contentsline {subsection}{\numberline {C.1}Calibration development}{136}
\contentsline {subsection}{\numberline {C.2}Operation improvements}{136}
\contentsline {subsection}{\numberline {C.3}Code improvements}{137}